A communication simulation device for simulating a front-end chip in a battery management system

Abstract

The present application discloses a communication simulation device for simulating a front-end chip in a battery management system, and relates to the field of communication test technology. The communication simulation device includes: a microcontroller unit, a field programmable logic gate array, and a daisy chain conversion module connected in sequence; the field programmable logic gate array is used to simulate the register and daisy chain communication timing of the front-end chip in the battery management system based on the register configuration parameters; the microcontroller unit is used to communicate with a host computer, receive a register configuration parameter modification instruction of the host computer, modify the register configuration parameters in the field programmable logic gate array according to the register configuration parameter modification instruction, and upload the register configuration parameters in the field programmable logic gate array to the host computer; the daisy chain conversion module is used for communication between the field programmable logic gate array and the battery control unit being tested. The present application can improve the safety of the test.

Description

Technical Field

[0001] The present application relates to the field of communication testing technology, and in particular to a communication simulation device for simulating a front-end chip in a battery management system. Background Art

[0002] The hardware of the Battery Management System (BMS) consists of two parts: the Battery Control Unit (BCU) and the Battery Management Unit (BMU). The BCU and BMU communicate through a daisy chain architecture. The BMU consists of multiple analog front-end (AFE) chips and peripheral circuits. The BMU is installed inside the module and is used to detect single cell voltage, current and balance control; the BCU installation position is relatively flexible and is used for relay control, state of charge (SOC) estimation and electrical damage protection. The BMU and BCU communicate through multiple communication protocols. Semi-physical simulation tests are required during the design of the BMS control strategy. Currently, battery simulators are used to simulate the battery cells. The battery simulator is connected to the BMU to simulate the battery and BMU parts. There are problems such as complex wiring in the physical circuit and high risk. Summary of the invention

[0003] The purpose of this application is to provide a communication simulation device for simulating a front-end chip in a battery management system, which can improve the safety of testing.

[0004] To achieve the above objectives, this application provides the following solutions:

[0005] In a first aspect, the present application provides a communication simulation device for simulating a front-end chip in a battery management system, comprising: a microcontroller unit, a field programmable logic gate array, and a daisy chain conversion module connected in sequence;

[0006] The field programmable logic gate array is used to simulate the registers and daisy chain communication timing of the analog front-end chip in the battery management system based on the register configuration parameters;

[0007] The microcontroller unit is used to communicate with the host computer, receive the register configuration parameter modification instruction of the host computer, modify the register configuration parameters in the field programmable logic gate array according to the register configuration parameter modification instruction, and upload the register configuration parameters in the field programmable logic gate array to the host computer;

[0008] The daisy chain conversion module is used for communication between the field programmable logic gate array and the battery control unit under test.

[0009] Optionally, the communication simulation device of the simulated front-end chip in the battery management system includes an Ethernet interface, a serial port, a bus, PCIE and EtherCAT, and the Ethernet interface, serial port, bus, PCIE and EtherCAT are used for the microcontroller unit to communicate with the host computer; wherein the bus is a CAN bus or a CANFD bus.

[0010] Optionally, the communication simulation device of the analog front-end chip in the battery management system also includes a Flash memory, which is communicatively connected to the microcontroller unit, and is used to store a first algorithm in the microcontroller unit and a second algorithm in the field programmable logic gate array, wherein the first algorithm is used to modify register configuration parameters, and the second algorithm is used to simulate the registers and daisy chain communication timing of the analog front-end chip.

[0011] Optionally, the communication simulation device for simulating the front-end chip in the battery management system further includes a mode switching module, and the mode switching module is used to switch the startup mode of the microcontroller unit, and the startup mode includes a program upgrade mode and a local program running mode;

[0012] When the microcontroller unit is started in a program upgrade mode, the microcontroller unit receives an algorithm file after receiving a program update instruction from the host computer, updates the first algorithm and the second algorithm corresponding to the algorithm file, and stores the updated first algorithm and the second algorithm in corresponding locations of the Flash memory;

[0013] When the startup mode of the micro control unit is the local program running mode, the micro control unit loads the first algorithm in the Flash memory, and sends the register configuration parameters modified by the first algorithm to the field programmable logic gate array;

[0014] The field programmable logic gate array runs the second algorithm after loading the second algorithm in the Flash memory, and modifies the register according to the register configuration parameters.

[0015] Optionally, the communication simulation device of the analog front-end chip in the battery management system also includes a JTAG interface, DDR3 and an SD card, the JTAG interface is used to connect the debugging pins of the microcontroller unit and the field programmable gate array, the DDR3 is used to connect to the memory pins of the microcontroller unit, and the SD card is used to store the algorithm file.

[0016] Optionally, when the startup mode of the microcontroller unit is the local program running mode, the host computer is used to connect to the microcontroller unit through the Ethernet interface and send an acquisition instruction to the microcontroller unit; after receiving the acquisition instruction, the microcontroller unit sends the relevant configuration parameters of the first algorithm to the host computer, and the relevant configuration parameters of the first algorithm include the number of analog front-end chips, the fault location of the analog front-end chip, the IP address of the Ethernet interface, the subnet mask of the Ethernet interface, the port number of the Ethernet interface, the baud rate of the bus and the register configuration parameters.

[0017] Optionally, when the microcontroller unit is started in a local program running mode, the host computer is also used to send a configuration parameter modification instruction to the microcontroller unit through an Ethernet interface, serial port, bus, PCIE or EtherCAT. After receiving the configuration parameter modification instruction, the microcontroller unit modifies the relevant configuration parameters of the first algorithm.

[0018] Optionally, when the microcontroller unit is started in a local program running mode, the host computer is further used to receive the register configuration parameters in the first algorithm uploaded by the microcontroller unit through an Ethernet interface, a serial port, a bus, PCIE or EtherCAT.

[0019] Optionally, when the host computer modifies the register configuration parameters in the first algorithm through the bus, it specifically includes:

[0020] The ID of each bus corresponds to a register configuration parameter. After the microcontroller receives the register read instruction CAN message or the register read instruction CANFD message sent by the host computer, the microcontroller sends the register configuration parameter to the host computer through the CAN bus interface or the CANFD bus interface according to the corresponding ID;

[0021] After the microcontroller receives a register write instruction CAN message or a register write instruction CANFD message, it sends the register configuration parameters in the register write instruction CAN message or the register write instruction CANFD message to the field programmable gate array. After the field programmable gate array modifies the register configuration parameters, the microcontroller sends the write completion instruction to the host computer according to the corresponding ID through the CAN bus interface or the CANFD bus interface.

[0022] Optionally, when the host computer modifies the register configuration parameter in the first algorithm through the PCIE, it specifically includes:

[0023] The host computer is used to change the corresponding register configuration parameters by writing the value of the address space of the PCIE, and the host computer is used to obtain the corresponding register configuration parameters by reading the value of the address space of the PCIE.

[0024] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0025] The present application provides a communication simulation device for simulating a front-end chip in a battery management system, which simulates the registers and daisy chain communication timing of the front-end chip in the battery management system through a field programmable gate array (FPGA), communicates with a host computer through a microcontroller unit (MCU), receives a register configuration parameter modification instruction of the host computer, and modifies the register configuration parameters in the field programmable gate array according to the register configuration parameter modification instruction, thereby avoiding physical circuit wiring and high voltage, and ensuring the safety of battery management system testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of the structure of a communication simulation device for simulating a front-end chip in a battery management system provided in one embodiment of the present application;

[0028] Figure 2 A schematic diagram of the algorithm module structure in a communication simulation device for simulating a front-end chip in a battery management system provided in one embodiment of the present application;

[0029] Figure 3 A block diagram of a communication simulation device provided in an embodiment of the present application in a working state;

[0030] Figure 4 A schematic diagram of the working process of a communication simulation device for simulating a front-end chip in a battery management system provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] The present application provides a communication simulation device for simulating a front-end chip in a battery management system, such as Figure 1 As shown, the communication simulation device of the analog front-end chip in the battery management system includes: a micro control unit, a field programmable logic gate array and a daisy chain conversion module connected in sequence.

[0034] The field programmable logic gate array is used to simulate the registers and daisy chain communication timing of the analog front-end chip in the battery management system based on the register configuration parameters.

[0035] The microcontroller unit is used to communicate with a host computer, receive a register configuration parameter modification instruction from the host computer, modify the register configuration parameters in the field programmable logic gate array according to the register configuration parameter modification instruction, and upload the register configuration parameters in the field programmable logic gate array to the host computer.

[0036] The daisy chain conversion module is used for communication between the field programmable logic gate array and the battery control unit under test.

[0037] This application uses a microcontroller unit and a field programmable logic gate array

[0038] In an exemplary embodiment, the communication simulation device of the analog front-end chip in the battery management system includes an Ethernet interface, a serial port, a bus, a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) and Ethernet control automation technology (Ether Control Automation Technology, EtherCAT), and the Ethernet interface, serial port, bus, PCIE and EtherCAT are used for the micro control unit to communicate with the host computer; wherein the bus is a controller area network (Controller Area Network, CAN) bus or a controller area network with a flexible data rate (CAN with Flexible Data-Rate, CANFD) bus.

[0039] The Ethernet interface is used to communicate with the host computer of the analog front-end chip simulation device, receive the configuration parameters sent by the host computer, and upload the configuration parameters to the host computer; the MCU has its own Ethernet controller, and the Ethernet interface is connected to the MCU's dedicated Ethernet interface pin.

[0040] The serial port transmits the configuration information related to the analog front-end chip analog device with the serial port of other devices; the serial port is connected to the dedicated serial port pin of the MCU.

[0041] The CAN bus and the CAN communication interface of other devices simulate the transmission of relevant configuration information of the front-end chip simulation device; the MCU has its own CAN controller, and the CAN bus is connected to the MCU's dedicated CAN interface pins.

[0042] The CANFD bus transmits the configuration information related to the AFE analog front-end chip analog device through the CANFD communication interface of other devices; the MCU has its own CANFD controller, and the CANFD bus is connected to the MCU's dedicated CAN interface pins.

[0043] PCIE communicates with other devices through the PCIE communication interface to simulate the transmission of configuration information related to the front-end chip simulation device; FPGA has its own PCIE IP (Intellectual Property) core, and PCIE is connected to the FPGA's dedicated PCIE interface pins.

[0044] EtherCAT, that is, the EtherCAT interface communicates with the EtherCAT master interface of other devices to receive and send configuration information related to the AFE analog front-end chip analog device; EtherCAT communicates with the MCU using the SPI communication protocol and is connected to the MCU's dedicated SPI pin. Other devices are host computers, which are specifically computers or real-time machines, such as Figure 3 shown.

[0045] In an exemplary embodiment, the communication simulation device of the analog front-end chip in the battery management system also includes a Flash memory, which is communicatively connected to the microcontroller unit, and the Flash memory is used to store a first algorithm in the microcontroller unit and a second algorithm in the field programmable logic gate array, the first algorithm is used to modify register configuration parameters, and the second algorithm is used to simulate the registers and daisy chain communication timing of the analog front-end chip.

[0046] The Flsah memory is a non-volatile memory that stores the MCU algorithm and the FPGA algorithm. The MCU algorithm is the first algorithm and the FPGA algorithm is the second algorithm. The MCU communicates with the Flash via the SPI communication method, and the Flash is connected to the dedicated Flash pin of the MCU.

[0047] The MCU receives and sends the relevant register configuration parameter instructions of the host computer, modifies the relevant register parameters in the MCU, and then sends them to the FPGA. The FPGA modifies the registers and daisy chain communication timing of the simulated analog front-end chip according to the instructions sent by the MCU, and sends the relevant configuration parameters to the host computer.

[0048] The field programmable gate array is used to run the analog front-end chip simulation algorithm, obtain relevant configuration parameters of the second algorithm from the microcontroller unit, and communicate with the daisy chain conversion module; the microcontroller unit and the field programmable gate array perform inter-board high-speed communication, and the communication methods between the microcontroller unit and the field programmable gate array include but are not limited to: Flexible Static Memory Controller (FSMC) bus communication, Serial Peripheral Interface (SPI) bus communication, and Inter-Integrated Circuit (I2C) bus communication.

[0049] The daisy chain conversion module is used to convert SPI signals and differential signals to each other: convert differential signals into SPI signals and send them to FPGA, and convert FPGA's SPI signals into differential signals and send them to the device under test; the daisy chain conversion module and FPGA communicate via SPI.

[0050] In an exemplary embodiment, the communication simulation device of the analog front-end chip in the battery management system also includes a power module, which is used to provide a DC power supply to the microcontroller unit, the field programmable logic gate array and the daisy chain conversion module.

[0051] In an exemplary embodiment, the communication simulation device of the analog front-end chip in the battery management system also includes JTAG, DDR3 and SD card, JTAG, that is, the JTAG interface is used to connect the debugging pins of the microcontroller unit and the field programmable logic gate array, the DDR3 is used to connect to the memory pins of the microcontroller unit, and the SD card is used to store algorithm files.

[0052] The JTAG interface is a serial interface used for algorithm testing and debugging of MCU and FPGA. JTAG is connected to the dedicated programming and debugging pins of MCU and FPGA.

[0053] DR3 is used for MCU and FPGA related data storage and data transmission; DDR3 is connected to the dedicated memory pin of MCU, and MCU has built-in related communication drivers.

[0054] The SD card has an algorithm for storing MCU program upgrades via Ethernet; it communicates with the MCU via the SD protocol, and the SD card is connected to the MCU's dedicated SD interface pins. The SD card is used to load the code for updating the program in the Flash through the network port to update the device program to meet the requirements of simulating different types of AFE chips and daisy chain communication timing.

[0055] In an exemplary embodiment, the communication simulation device of the analog front-end chip in the battery management system also includes a mode switching module, and the mode switching module is used to switch the startup mode of the microcontroller unit, and the startup mode includes a program upgrade mode and a local program running mode.

[0056] The mode switching module switches the startup mode of the MCU through the analog switch. When the analog switch is turned on, the MCU starts from the SD card, and when the analog switch is turned off, the MCU starts from the Flash. The mode switching switch is connected to the startup mode selection pin of the MCU through physical wiring.

[0057] When the microcontroller unit is started in a program upgrade mode, the microcontroller unit receives the algorithm file sent by the host computer after receiving the program update instruction of the host computer, updates the first algorithm and the second algorithm corresponding to the algorithm file, and stores the updated first algorithm and the second algorithm in the corresponding position of the Flash memory. The program upgrade mode is specifically an Ethernet program upgrade mode.

[0058] When the micro control unit is started in a local program running mode, the micro control unit loads the first algorithm in the Flash memory, and sends the register configuration parameters modified by the first algorithm to the field programmable logic gate array.

[0059] The field programmable logic gate array runs the second algorithm after loading the second algorithm in the Flash memory, and modifies the register according to the register configuration parameters.

[0060] like Figure 2As shown, the microcontroller unit includes a data processing module and a CAN / CANFD module, a serial port module, an EtherCAT module, a data processing module and an Ethernet module connected to the data processing module. The field programmable gate array includes an FPGA register configuration module, a daisy chain communication timing simulation module and a PCIE module. The data processing module is connected to the FPGA register configuration module through an inter-board high-speed bus. The DB9 interface of the CAN / CANFD module, the TYPE-C interface of the serial port module, the RJ45 interface of the EtherCAT module, the RJ45 interface of the Ethernet module and the PCIE interface of the PCIE module are all used to connect to a host computer.

[0061] like Figure 4 As shown, the working process of the communication simulation device of the present application is: when the device is turned on, the MCU chooses to enter the local program running mode or the Ethernet port program upgrade mode according to the mode switching switch. When the mode switching switch is turned on, it enters the Ethernet program upgrade mode; when the mode switching switch is turned off, it enters the local program running mode.

[0062] First, the working process of Ethernet program upgrade mode is:

[0063] Step 1: The MCU runs the Ethernet program upgrade algorithm stored in the SD card; the FPGA synchronously runs the simulation algorithm of the solidified AFE analog front-end chip.

[0064] Step 2: MCU initializes the Ethernet interface and serial port. The initialization information includes the serial port outputting the relevant configuration parameters in the MCU and the Ethernet IP (Internet Protocol Address), subnet mask, and port number. After the MCU runs the Ethernet upgrade algorithm, the external device needs to know the relevant configuration parameters of the Ethernet before it can connect to the communication simulation device. Therefore, all Ethernet devices will confirm the Ethernet IP address, subnet mask, and port number in advance during the connection process.

[0065] Step 3: The external device connects to the MCU via Ethernet and sends a program update instruction; then it sends a new algorithm (compiled binary file) file, and the MCU completes the reception of the algorithm file.

[0066] Step 4: The external device sends a program solidification instruction via Ethernet, the MCU erases the corresponding location of the Flash, and solidifies the algorithm file at the specified location of the Flash to complete the program update.

[0067] Second, the working process of local program operation is:

[0068] Step 1: The MCU starts the algorithm from the specified location in Flash, and the FPGA synchronously runs the simulation algorithm of the solidified AFE analog front-end chip.

[0069] Step 2: MCU initializes Flash, loads relevant configuration parameters of the algorithm through Flash, and initializes the serial port, Ethernet, EtherCAT, CAN, CANFD and PCIE interface.

[0070] Step 3: The serial port outputs the relevant configuration parameters of the algorithm in the MCU to facilitate connection with external devices.

[0071] Step 4: The external device is connected to the communication simulation device of this application through the Ethernet interface, and the external device sends and obtains configuration parameter instructions. More specifically, the external device is used to obtain the relevant configuration parameters of the MCU sending algorithm and receive the relevant configuration parameters uploaded by the MCU; the external device can change the configuration parameters as needed.

[0072] Step 5: External devices can change the register configuration parameters of the algorithm in the MCU and obtain the register configuration parameters of the algorithm in the MCU through the serial port, CAN, CANFD, PCIE, and EtherCAT.

[0073] In an exemplary embodiment, when the startup mode of the microcontroller unit is the local program running mode, the host computer is used to connect to the microcontroller unit through the Ethernet interface and send an acquisition instruction to the microcontroller unit; after receiving the acquisition instruction, the microcontroller unit sends the relevant configuration parameters of the first algorithm to the host computer, and the relevant configuration parameters of the first algorithm include the number of analog front-end chips, the fault location of the analog front-end chip, the IP address of the Ethernet interface, the subnet mask of the Ethernet interface, the port number of the Ethernet interface, the baud rate of the bus and the register configuration parameters.

[0074] In an exemplary embodiment, when the microcontroller unit is started in a local program running mode, the host computer is also used to send a configuration parameter modification instruction to the microcontroller unit through an Ethernet interface, serial port, bus, PCIE or EtherCAT. After receiving the configuration parameter modification instruction, the microcontroller unit modifies the relevant configuration parameters of the first algorithm.

[0075] In an exemplary embodiment, when the microcontroller unit is started in a local program running mode, the host computer is also used to receive the register configuration parameters in the first algorithm uploaded by the microcontroller unit through an Ethernet interface, serial port, bus, PCIE or EtherCAT.

[0076] In an exemplary embodiment, when the host computer modifies the register configuration parameters in the first algorithm through the bus, it specifically includes: each ID of the bus corresponds to a register configuration parameter, and after the microcontroller unit receives the register read instruction CAN message or the register read instruction CANFD message sent by the host computer, the register configuration parameter is sent to the host computer through the CAN bus interface or the CANFD bus interface according to the corresponding ID.

[0077] After the microcontroller receives a register write instruction CAN message or a register write instruction CANFD message, it sends the register configuration parameters in the register write instruction CAN message or the register write instruction CANFD message to the field programmable gate array, and the field programmable gate array dynamically updates the corresponding register configuration parameters. After the field programmable gate array modifies the register configuration parameters, the microcontroller sends the write completion instruction to the host computer according to the corresponding ID through the CAN bus interface or the CANFD bus interface.

[0078] In an exemplary embodiment, when the host computer modifies the register configuration parameters in the first algorithm through the PCIE, it specifically includes: the host computer is used to change the corresponding register configuration parameters by writing the value of the address space of the PCIE, and the host computer is used to obtain the corresponding register configuration parameters by reading the value of the address space of the PCIE, and has the function of real-time application.

[0079] In an exemplary embodiment, when the host computer modifies the register configuration parameters in the first algorithm through the EtherCAT interface, it specifically includes: the microcontroller receives the process data object (PDO) message of the EtherCAT interface of the host computer at fixed intervals, the microcontroller obtains the register configuration parameters of the FPGA according to the address field of the PDO, and the corresponding register configuration parameters are sent to the FPGA, and the FPGA dynamically updates the register configuration parameters specified in the algorithm; the microcontroller sends the FPGA register configuration parameters to the host computer through the EtherCAT interface in the form of a PDO message with a specified address at fixed intervals. The host computer can obtain and change all the register configuration parameters of the FPGA at fixed intervals, with a minimum interval of 1ms, and has the function of real-time application.

[0080] In an exemplary embodiment, when the host computer modifies the register configuration parameters in the first algorithm through the serial port, it specifically includes: the host computer changes the register configuration parameters through the serial port, the first 4 bytes of each serial port message represent the register address and read / write instructions of the corresponding FPGA, and the subsequent bytes represent the corresponding register configuration parameters. The MCU receives the FPGA register read instruction serial port message, and sends the relevant FPGA register configuration parameters to the host computer through the serial port; the MCU receives the register write instruction serial port message, and the MCU sends the relevant FPGA register configuration parameters to the FPGA, the FPGA dynamically updates the register configuration parameters specified in the algorithm, and the MCU sends the write completion instruction to the host computer through the serial port.

[0081] The present application can also adopt the ARM (Advanced RISC Machine, RISC microprocessor) + FPGA architecture to implement the communication simulation device of the analog front-end chip in the battery management system of the present application. The ARM+FPGA architecture combines the advantages of the ARM processor and the FPGA. The ARM+FPGA architecture includes two parts: the processing system and the programmable logic. The processing system part, namely ARM, specifically adopts a dual-core ARM Cortex-A9 processor, which is responsible for running the operating system and software applications, which is equivalent to the microprocessing unit in the present application. The programmable logic part adopts programmable logic based on the Xilinx 7 series FPGA architecture, which is used to realize hardware acceleration and customization functions, which is equivalent to the FPGA in the present application. ARM and FPGA communicate through the Advanced Extensible Interface (AXI) bus.

[0082] This application uses FPGA to simulate AFE chips to solve the shortcomings of insufficient resources and inaccurate timing in existing AFE chip simulation solutions. The MCU of X86 architecture or ARM architecture is responsible for processing the communication data between external devices, and the FPGA is responsible for simulating the register data and daisy chain communication timing of the AFE chip. It can simulate multiple AFE chips and their mutual communication timing. The host computer is one of the external devices.

[0083] This application simulates the real cell voltage by simulating the register value of the relevant AFE chip, avoiding physical circuit wiring and high voltage, and ensuring the safety of the battery management system test.

[0084] The EtherCAT and PCIE interfaces of this application have high-speed real-time effects, can meet the needs of real-time changes of all register configuration parameters, have high-speed real-time effects, and at the same time have network ports, and CAN bus or CANFD bus interfaces, can meet non-real-time applications, and achieve compatibility with real-time and non-real-time applications.

[0085] This application avoids the real physical circuit by simulating the register value and daisy chain communication process of the AFE chip, and has high security. At the same time, the real-time interface can be connected to the semi-physical simulation bench for automated testing, which is highly efficient.

[0086] This application implements the program update function through the mode switching module, has the function of simulating different types of AFE chips, and updates the ARM and FPGA programs through the network port, which can meet the needs of simulating different AFE chips.

[0087] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A communication simulation device for simulating a front-end chip in a battery management system, characterized in that: The communication simulation device for simulating the front-end chip in the battery management system comprises: a micro control unit, a field programmable logic gate array and a daisy chain conversion module connected in sequence; The field programmable logic gate array is used to simulate the registers and daisy chain communication timing of the analog front-end chip in the battery management system based on the register configuration parameters; The microcontroller unit is used to communicate with the host computer, receive the register configuration parameter modification instruction of the host computer, modify the register configuration parameters in the field programmable logic gate array according to the register configuration parameter modification instruction, and upload the register configuration parameters in the field programmable logic gate array to the host computer; The daisy chain conversion module is used for communication between the field programmable logic gate array and the battery control unit under test; The communication simulation device for simulating the front-end chip in the battery management system further includes a Flash memory, which is communicatively connected to the microcontroller unit, and is used to store a first algorithm in the microcontroller unit and a second algorithm in the field programmable logic gate array, wherein the first algorithm is used to modify register configuration parameters, and the second algorithm is used to simulate the register and daisy chain communication timing of the analog front-end chip; The Flash memory is a non-volatile memory, storing an MCU algorithm and an FPGA algorithm, the MCU algorithm is a first algorithm, and the FPGA algorithm is a second algorithm; the microcontroller unit communicates with the Flash memory through an SPI communication mode, and the Flash memory is connected to a dedicated Flash pin of the microcontroller unit; The microcontroller unit receives and sends the relevant register configuration parameter instructions of the host computer, modifies the relevant register parameters in the microcontroller unit, and then sends them to the field programmable logic gate array. The field programmable logic gate array modifies the registers and daisy chain communication timing of the simulated analog front-end chip according to the instructions sent by the microcontroller unit, and sends the relevant configuration parameters to the host computer.

2. The communication simulation device for simulating a front-end chip in a battery management system according to claim 1, characterized in that: The communication simulation device for simulating the front-end chip in the battery management system includes an Ethernet interface, a serial port, a bus, PCIE and EtherCAT, and the Ethernet interface, serial port, bus, PCIE and EtherCAT are used for the microcontroller unit to communicate with the host computer; wherein the bus is a CAN bus or a CANFD bus.

3. The communication simulation device for simulating a front-end chip in a battery management system according to claim 2, characterized in that: The communication simulation device for simulating the front-end chip in the battery management system further includes a mode switching module, and the mode switching module is used to switch the startup mode of the micro control unit, and the startup mode includes a program upgrade mode and a local program running mode; When the microcontroller unit is started in a program upgrade mode, the microcontroller unit receives an algorithm file after receiving a program update instruction from the host computer, updates the first algorithm and the second algorithm corresponding to the algorithm file, and stores the updated first algorithm and the second algorithm in corresponding locations of the Flash memory; When the startup mode of the micro control unit is the local program running mode, the micro control unit loads the first algorithm in the Flash memory, and sends the register configuration parameters modified by the first algorithm to the field programmable logic gate array; The field programmable logic gate array runs the second algorithm after loading the second algorithm in the Flash memory, and modifies the register according to the register configuration parameters.

4. The communication simulation device for simulating a front-end chip in a battery management system according to claim 3, characterized in that: The communication simulation device of the analog front-end chip in the battery management system also includes a JTAG interface, DDR3 and an SD card. The JTAG interface is used to connect the debugging pins of the microcontroller unit and the field programmable logic gate array, the DDR3 is used to connect to the memory pins of the microcontroller unit, and the SD card is used to store the algorithm file.

5. The communication simulation device for simulating a front-end chip in a battery management system according to claim 3, characterized in that: When the startup mode of the microcontroller unit is the local program running mode, the host computer is used to connect to the microcontroller unit through the Ethernet interface and send an acquisition instruction to the microcontroller unit; after receiving the acquisition instruction, the microcontroller unit sends the relevant configuration parameters of the first algorithm to the host computer, and the relevant configuration parameters of the first algorithm include the number of analog front-end chips, the fault location of the analog front-end chip, the IP address of the Ethernet interface, the subnet mask of the Ethernet interface, the port number of the Ethernet interface, the baud rate of the bus and the register configuration parameters.

6. The communication simulation device for simulating a front-end chip in a battery management system according to claim 5, characterized in that: When the startup mode of the micro control unit is the local program running mode, the host computer is also used to send a configuration parameter modification instruction to the micro control unit through an Ethernet interface, serial port, bus, PCIE or EtherCAT. After receiving the configuration parameter modification instruction, the micro control unit modifies the relevant configuration parameters of the first algorithm.

7. The communication simulation device for simulating a front-end chip in a battery management system according to claim 6, characterized in that: When the startup mode of the micro control unit is the local program running mode, the host computer is also used to receive the register configuration parameters in the first algorithm uploaded by the micro control unit through an Ethernet interface, a serial port, a bus, PCIE or EtherCAT.

8. The communication simulation device for simulating a front-end chip in a battery management system according to claim 7, characterized in that: When the host computer modifies the register configuration parameters in the first algorithm through the bus, it specifically includes: The ID of each bus corresponds to a register configuration parameter. After the microcontroller receives the register read instruction CAN message or the register read instruction CANFD message sent by the host computer, the microcontroller sends the register configuration parameter to the host computer through the CAN bus interface or the CANFD bus interface according to the corresponding ID; After the microcontroller receives a register write instruction CAN message or a register write instruction CANFD message, it sends the register configuration parameters in the register write instruction CAN message or the register write instruction CANFD message to the field programmable gate array. After the field programmable gate array modifies the register configuration parameters, the microcontroller sends the write completion instruction to the host computer according to the corresponding ID through the CAN bus interface or the CANFD bus interface.

9. The communication simulation device for simulating a front-end chip in a battery management system according to claim 7, characterized in that: When the host computer modifies the register configuration parameters in the first algorithm through the PCIE, it specifically includes: The host computer is used to change the corresponding register configuration parameters by writing the value of the address space of the PCIE, and the host computer is used to obtain the corresponding register configuration parameters by reading the value of the address space of the PCIE.

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