HEMT transistor, manufacturing method thereof and radio frequency module
By setting up the first plate structure between the gate and the drain of the HEMT transistor, the problem of the peak distribution of the medium -electric field of the thin buffer extension layer is solved, and the resistance and power level of the nitride -nitride frequency frequency device is improved.
Patent Information
- Application Number
- CN202411299025.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-01-24
AI Technical Summary
In gallium nitride radio frequency devices, the thin Buffer epitaxial layer causes the electric field peak to be concentratedly distributed in the boundary area of the drain ohmic region, affecting the device's voltage withstand capacity and power level.
Set the first plate structure between the gate and the drain of the HEMT transistor to make it close to the drain. The electrical field is modulated through this structure to ensure that the electric field is distributed more evenly in the ditch.
By introducing the first field plate structure, the peak electric field near the boundary of the drain ohmic region is effectively reduced, and the voltage withstand capability and power level of the gallium nitride RF device are improved.
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Figure CN119364799A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a HEMT transistor and a manufacturing method thereof, and a radio frequency module including the HEMT transistor. Background Art
[0002] High Electron Mobility Transistor (HEMT) has the advantages of high frequency, high voltage, and high temperature. The third-generation semiconductor material GaN (gallium nitride) has become a current research hotspot due to its large bandgap, high electron saturation rate, high breakdown electric field, high thermal conductivity, strong corrosion resistance and radiation resistance, and has broad application prospects. In particular, the high electron mobility transistor (HEMT) with AlGaN / GaN heterojunction structure has the advantages of high frequency, high power density, and high operating temperature, and has shown great advantages in high-temperature devices and high-power microwave devices, and has attracted a lot of research in the pursuit of high frequency, high voltage, and high power in semiconductor devices.
[0003] At present, in order to improve the performance of GaN RF devices under high electrical and thermal stress, the thin buffer technology route is gradually gaining favor among more and more companies in the industry. Compared with traditional GaN epitaxy, this technology route has significant differences in growth mode and material properties, and the corresponding chip process technology and device physical properties are also different. In RF devices using GaN thin buffer technology, the electric field distribution under actual working conditions requires a dedicated modulation method that is different from that of traditional thick GaN epitaxial RF devices.
[0004] Since the impurity concentration and thickness in the thin buffer epitaxial layer are significantly different from those in the traditional thick buffer, the electric field peak of the RF device under high voltage stress changes from being distributed at the bottom of the gate near the drain to being distributed at the boundary of the drain ohmic region. Therefore, in the thin buffer technology, it is necessary to solve the problem of the electric field peak being concentrated in the boundary area of the drain ohmic region on the basis of improving the performance of the GaN RF device under high electrical stress, so as to further improve the voltage resistance and power level of the GaN RF device. Summary of the invention
[0005] A HEMT transistor provided by the present invention comprises a semiconductor epitaxial layer arranged on a substrate, a source, a drain and a gate arranged on the semiconductor epitaxial layer, the source and the drain are arranged opposite to each other, the gate is arranged between the source and the drain, the transistor also comprises a first field plate structure and a first passivation layer, the first passivation layer covers the gate, the first field plate structure is arranged on the first passivation layer, the first field plate structure is arranged between the gate and the drain, the shortest distance from the first field plate structure to the drain is shorter than the shortest distance from the first field plate structure to the gate; the first passivation layer is arranged between the first field plate structure and the gate.
[0006] The present invention also provides a method for manufacturing a HEMT transistor, comprising the following steps: forming a semiconductor epitaxial layer; forming a source electrode and a drain electrode opposite to each other on the semiconductor epitaxial layer; forming a gate; Covering the gate with a first passivation layer; A second photoresist layer is formed, and a fourth window and a fifth window are formed by a photolithography process; metals are deposited in the fourth window and the fifth window to form a first field plate structure and a second field plate structure, respectively, and the shortest distance from the first field plate structure to the drain is shorter than the shortest distance from the first field plate structure to the gate.
[0007] The present invention also provides a radio frequency module, comprising the HEMT transistor as described above.
[0008] Compared with the prior art, the present invention provides a HEMT transistor in which a first field plate structure is arranged between the gate and the drain, and the first field plate structure is arranged close to the drain, so that the electric field concentrated in the boundary area of the drain ohmic region can be uniformly modulated, thereby improving the voltage resistance and power level of the gallium nitride radio frequency device. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0010] Figure 1 A schematic diagram of the structure of a HEMT transistor provided in Embodiment 1 of the present invention; Figure 2 for Figure 1 A magnified view of part A in FIG. Figure 3 for Figure 1 A schematic structural diagram of a HEMT transistor of a first variation; Figure 4 for Figure 3 A magnified view of part B in FIG. Figure 5 for Figure 1 A schematic diagram of the structure of a HEMT transistor of a second variation; Figure 6 for Figure 5 Enlarged view of the middle C part; Figure 7 A comparison diagram of electric field distribution of HEMT transistors of the present invention and a comparative example provided in Example 1 of the present invention; Figure 8 A schematic diagram of the manufacturing process of the semiconductor epitaxial layer and the source and drain provided in the second embodiment of the present invention; Fig. 9 A schematic diagram of the manufacturing process of the second passivation layer provided in the second embodiment of the present invention; Fig.10 A schematic diagram of a manufacturing process of a first photoresist layer provided in Embodiment 2 of the present invention; Fig.11 A schematic diagram of a manufacturing process of a gate metal layer provided in the second embodiment of the present invention; Fig.12 A schematic diagram of the structure of a gate electrode provided in the second embodiment of the present invention after being manufactured; Fig.13 A schematic diagram of the manufacturing process of the first passivation layer provided in the second embodiment of the present invention; Fig.14 A schematic diagram of the manufacturing process of the first field plate structure and the second field plate structure provided in the second embodiment of the present invention; Fig.15 A schematic diagram of the manufacturing process of the first field plate structure and the second field plate structure provided in the second embodiment of the present invention; Fig.16 A schematic diagram of the manufacturing process of the third passivation layer provided in the second embodiment of the present invention; Fig.17 A schematic diagram of a manufacturing process of a first field plate structure and a second field plate structure of another shape provided in the second embodiment of the present invention; Fig.18 A schematic diagram of a manufacturing process of a first field plate structure and a second field plate structure of another shape provided in the second embodiment of the present invention; Fig.19 This is a schematic diagram of the manufacturing process of the third passivation layer provided in the second embodiment of the present invention.
[0011] Reference numerals: DETAILED DESCRIPTION
[0012] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0013] In the description of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. Example 1 See also Figure 1 The present invention provides a HEMT transistor, comprising a substrate 10, a semiconductor epitaxial layer 20, a source 30, a drain 40 and a gate 50 arranged on the semiconductor epitaxial layer 20, wherein the source 30 and the drain 40 are arranged opposite to each other, and the gate 50 is arranged between the source 30 and the drain 40. The HEMT transistor is further provided with a substrate 10 below the semiconductor epitaxial layer 20, and the semiconductor epitaxial layer 20 comprises a buffer layer 21, a channel layer 22 and a barrier layer 23 which are sequentially stacked from bottom to top.
[0014] The substrate 10 may be a base material for carrying semiconductor integrated circuit components, such as silicon (Si), silicon carbide (SiC), sapphire (Saphhire), gallium nitride (GaN), etc. The buffer layer 21 is disposed between the substrate 10 and the channel layer 22 to avoid lattice mismatch between the substrate 10 and the channel layer 22. The buffer layer 21 is a thin buffer layer 21 with a thickness ranging from 50nm to 800nm.
[0015] A heterojunction is formed between the channel layer 22 and the barrier layer 23 to form a two-dimensional electron gas. As an example, the barrier layer 23 can be a layer or a stack of aluminum gallium nitride, aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride or aluminum indium gallium nitride. Of course, according to the actual needs of the HEMT device, the semiconductor epitaxial layer 20 can also be provided with at least one of the functional layers (not shown in the figure) such as a nucleation layer, a transition layer, and an insertion layer, which is not limited here.
[0016] The source 30 and the drain 40 are arranged on the semiconductor epitaxial layer 20, and the gate 50 is located between the source 30 and the drain 40. The gate 50 can be a T-type gate structure, including a gate cap and a gate foot, or a gate structure with a rectangular cross section. The direction from the source 30 to the drain 40 is the x direction, also called the gate length direction; the direction from the substrate 10 to the semiconductor epitaxial layer 20 is the y direction, and the x direction and the y direction are perpendicular to each other.
[0017] The thickness of the semiconductor epitaxial layer 20 of the present embodiment is 0.1 μm to 0.5 μm. The semiconductor epitaxial layer 20 is thinner than the conventional gallium nitride epitaxial layer 20. This makes the electric field distribution of the HEMT transistor of the present invention different from that of the conventional HEMT transistor under actual working conditions. It is necessary to perform exclusive modulation on the HEMT transistor structure of the thin epitaxial layer so that the electric field distribution meets the requirements of the thin epitaxial layer HEMT transistor.
[0018] Specifically, the HEMT transistor provided by the present invention further includes a first field plate structure 60 and a first passivation layer 82, wherein the first passivation layer 82 covers the gate 50, and the first field plate structure 60 is disposed on the first passivation layer 82; the first field plate structure 60 is disposed between the gate 50 and the drain 40, and the shortest distance from the first field plate structure 60 to the drain 40 is smaller than the shortest distance from the first field plate structure 60 to the gate 50. The shortest distance is the shortest straight-line distance from the first field plate structure 60 to the gate 50 and the drain 60.
[0019] Preferably, the first field plate structure 60 is electrically connected to the metal of the source 30. Preferably, an ion implantation region is provided below the source 30 and the drain 40. Specifically, it can be seen from the TCAD simulation of the electric field distribution of the gallium nitride RF device under high voltage that as the thickness of the gallium nitride epitaxial layer decreases, the peak value of the electric field in the channel gradually shifts from below the root of the gate 50 close to the drain 40 to the vicinity of the boundary of the injection region of the drain 40. Therefore, above the high electric field region in the thin buffer device, by introducing the first field plate structure 60 electrically connected to the metal of the source 30, it is possible to more effectively enhance the withstand voltage capability, reduce the peak electric field near the boundary of the injection region of the drain 40, and improve the uniformity of the electric field distribution in the channel, thereby increasing the operating voltage of the device.
[0020] See also Figure 1 and Figure 2 In the gate length direction, the cross-sectional shape of the first field plate structure 60 is a trapezoid. Preferably, it is a regular trapezoid, a quasi-regular trapezoid, an inverted trapezoid or a quasi-inverted trapezoid. It should be noted that in the gate length direction, the cross-sectional shape of the first field plate structure 60 is not limited to a trapezoid, and can also be a rectangular, square or other shapes.
[0021] See also Figure 3 and Figure 4The first field plate structure 60 includes a first lateral portion 61, a second lateral portion 62 and a first longitudinal portion 63, the first longitudinal portion 63 connects the first lateral portion 61 and the second lateral portion 62; the first lateral portion 61 is located above the drain 40, and the second lateral portion 62 is located between the drain 40 and the gate 50 and is arranged on the first passivation layer 82 in the opposite direction of the x-direction.
[0022] See also Figure 2 and Figure 4 In one embodiment, the distance from the bottom of the first field plate structure 60 to the semiconductor epitaxial layer 20 is denoted as d1, and d1 is 20nm to 200nm. When d1 is greater than 20nm, it can avoid the phenomenon that the parasitic capacitance generated between the source and drain 40 is too large to reduce the radio frequency performance of the HEMT transistor; when d1 is less than 200nm, the modulation effect of the first field plate structure 60 on the electric field distribution of the HEMT transistor can be guaranteed.
[0023] See also Figure 2 and Figure 4 , the shortest distance from the first field plate structure 60 to the gate 50 is recorded as d2, and d2 is greater than 0.5 μm. d2 greater than 0.5 μm can effectively avoid excessive parasitic capacitance between the source and drain 40, and improve the RF performance of the HEMT transistor. The maximum distance of d2 is determined by the size of the first field plate structure 60 in the gate length direction, the shortest distance from the first field plate structure 60 to the drain 40, and the distance from the gate 50 to the drain 40.
[0024] See also Figure 2 and Figure 4 , in the gate length direction, the size of the first field plate structure 60 is denoted as d3, and the range of d3 is 0.5μm to 2μm. When d3 is greater than 0.5μm, the first field plate structure 60 can completely cover the electric field peak on one side of the drain 40, and can effectively adjust the electric field distribution of the thin epitaxial layer HEMT transistor; when d3 is less than 2μm, the source-drain parasitic capacitance formed by the first field plate structure 60 and the epitaxial layer can be reduced, which is beneficial to maintaining the RF performance of the device. Otherwise, the source-drain parasitic capacitance formed by the first field plate structure 60 and the epitaxial layer is not conducive to the RF performance of the device.
[0025] See also Figure 2 and Figure 4 , the shortest distance from the first field plate structure 60 to the drain 40 is denoted as d4, and d4 is 300nm to 1μm. When the distance d4 is greater than 300nm, the overlapping area between the first field plate structure 60 and the semiconductor epitaxial layer 20 can be reduced, and the parasitic capacitance between the source and drain 40 can be avoided to be too large, thereby reducing the RF performance of the HEMT transistor; when the distance d4 is less than 1μm, the first field plate structure 60 can cover the electric field peak near the drain 40 to the greatest extent, which can effectively improve the withstand voltage performance of the HEMT transistor.
[0026] See also Figure 2 and Figure 4 , the ratio of the shortest distance d4 from the first field plate structure 60 to the drain 40 to the shortest distance d2 from the first field plate structure 60 to the gate 50, the size d3 of the first field plate structure 60, and the shortest distance d4 from the first field plate structure 60 to the drain 40 is in the range of 10% to 50%. The specific relationship is: d4: (d2 + d3 + d4) = 10% to 50%. If d4: (d2 + d3 + d4) < 10%, the distance between the first field plate structure 60 and the drain 40 is too small, the parasitic capacitance Cds is too large, and the electric field of the passivation layer between the two is too large, and the risk of breakdown during high-voltage operation is high. If d4: (d2 + d3 + d4) > 50%, the distance between the first field plate structure 60 and the drain 40 is too far, and the first field plate structure 60 cannot effectively adjust the electric field peak of the semiconductor epitaxial layer 20 close to the drain 40.
[0027] See also Figure 5 and Figure 6 The HEMT transistor further includes a second field plate structure 70, which is located between the gate 50 and the first field plate structure 60. The second field plate structure 70 includes a third lateral portion 71, a fourth lateral portion 72 and a second longitudinal portion 73, and the second longitudinal portion 73 connects the third lateral portion 71 and the fourth lateral portion 72; the third lateral portion 71 is located above the gate 50, the fourth lateral portion 72 is located between the gate 50 and the first field plate structure 60 and is arranged on the first passivation layer 82 in the x direction; the x direction is the direction from the source 30 to the drain 40.
[0028] Specifically, the second field plate structure 70 is electrically connected to the source electrode 30 by metal.
[0029] Optionally, the first field plate structure 60 and the second field plate structure 70 may be composed of a single metal layer or a multi-layer metal stack, wherein the metal material is gold. The first field plate structure 60 and the second field plate structure 70 may also include an anti-diffusion layer to prevent the diffusion of gold, and the metal material of the anti-diffusion layer may be platinum, nickel, molybdenum, palladium, tungsten, vanadium, and a material of the adhesion enhancing metal layer, such as metal titanium, nickel, aluminum, chromium, and vanadium. The adhesion enhancing metal layer, the anti-diffusion layer, the gold layer, and the protective metal layer are sequentially deposited to form a field plate structure.
[0030] Figure 7 The comparison diagram of the electric field distribution of the conventional thin epitaxial layer HEMT transistor and the thin epitaxial layer HEMT transistor of the present invention obtained by TCAD simulation of the GaN RF device under high voltage is shown in FIG. Figure 7 It can be seen that the present invention effectively enhances the voltage resistance of the HEMT transistor by introducing the first field plate structure 60 electrically connected to the source 30 metal, reduces the peak electric field near the injection region of the drain 40, and makes the electric field more evenly distributed in the channel, thereby achieving a higher operating voltage.
[0031] Embodiment 2 The present invention also provides a method for manufacturing a HEMT transistor, comprising the following steps: Forming a semiconductor epitaxial layer 20: Forming a semiconductor epitaxial layer 20 on a substrate 10. The semiconductor epitaxial layer 20 includes a buffer layer 21, a channel layer 22 and a barrier layer 23 which are stacked in sequence.
[0032] See also Figure 8 , forming a source electrode 30 and a drain electrode 40 oppositely disposed on the semiconductor epitaxial layer 20. Fig. 9 If the gate 50 is a T-type gate structure, a second passivation layer 81 can be deposited on the semiconductor epitaxial layer 20 at the bottom of the gate cap and on the source 30 and the drain 40, and the second passivation layer 81 is etched by a photolithography process to form a first window 51 between the source 30 and the drain 40 to expose the semiconductor epitaxial layer 20; the second passivation layer 81 can be composed of a single layer or multiple layers of dielectric layers, and the formed material can be SiN, SiO 2 、AlN、Al 2 O 3 Any dielectric material.
[0033] See also Fig.10 , forming a first photoresist layer 91, and forming a second window 52 by photolithography. In the gate length direction, the second window 52 is larger than the first window 51. Depositing the gate metal layer 54 by magnetron sputtering. Fig.11 , and a gate metal layer 54 is formed at the first window 51 and the second window 52, and a third window 53 is formed on the gate metal layer 54. Fig.12 , remove the first photoresist layer 91 and the gate metal layer 54 on the first photoresist layer 91 to form the gate 50.
[0034] See also Fig.13 , the first passivation layer 82 is covered on the gate 50 and the second passivation layer 81. Fig.14 and Fig.17 , forming a second photoresist layer 92 on the first passivation layer 82, and forming a fourth window 64 and a fifth window 74 by a photolithography process to expose the first passivation layer 82; see Fig.15 and Fig.18 , metals are deposited in the fourth window 64 and the fifth window 74 to form the first field plate structure 60 and the second field plate structure 70. Fig.16 and Fig.19 A third passivation layer 83 is deposited on top of the first field plate structure 60 and the second field plate structure 70 .
[0035] pass Fig.14 , Fig.15 and Fig.16The first field plate structure 60 obtained in the step has a trapezoidal cross-section in the gate length direction. It should be noted that the cross-section of the first field plate structure 60 in the gate length direction is not limited to a trapezoid, but can also be a rectangle, a square, or the like.
[0036] pass Fig.17 , Fig.18 and Fig.19 The first field plate structure 60 obtained by the steps includes a first transverse portion 61, a second transverse portion 62 and a first longitudinal portion 63, wherein the first longitudinal portion 63 connects the first transverse portion 61 and the second transverse portion 62; the first transverse portion 61 is located above the drain 40, and the second transverse portion 62 is located between the drain 40 and the gate 50 and is disposed on the first passivation layer 82 in the opposite direction of the x-direction. The x-direction is the direction from the source 30 to the drain 40.
[0037] Specifically, the shortest distance from the first field plate structure to the drain is shorter than the shortest distance from the first field plate structure to the gate. Fig.19 , the shortest distance from the first field plate structure to the drain is recorded as d4; the shortest distance from the first field plate structure to the gate is recorded as d2, where d4<d2.
[0038] Optionally, the second passivation layer 81, the first passivation layer 82 and the third passivation layer 83 may be composed of a single layer or multiple layers of dielectric layers, and may be made of SiN, SiO 2 、AlN、Al 2 O 3 Any dielectric material.
[0039] The present invention also provides a radio frequency module, comprising the HEMT transistor as described above. The radio frequency module can be applied to communication terminal equipment such as base stations and mobile phones.
[0040] Although the terms such as substrate, semiconductor epitaxial layer, buffer layer, channel layer, barrier layer, source, drain, gate, first window, second window, third window, gate metal layer, first field plate structure, first lateral portion, second lateral portion, first longitudinal portion, fourth window, second field plate structure, third lateral portion, fourth lateral portion, second longitudinal portion, fifth window, passivation layer, first passivation layer, second passivation layer, third passivation layer, first photoresist layer and second photoresist layer are used more frequently in this article, the possibility of using other terms is not excluded. The use of these terms is only for more convenient description and explanation of the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.
[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A HEMT transistor, comprising a semiconductor epitaxial layer, a source, a drain and a gate arranged on the semiconductor epitaxial layer, wherein the source and the drain are arranged opposite to each other, and the gate is arranged between the source and the drain, characterized in that: The HEMT transistor further includes a first field plate structure and a first passivation layer, wherein the first passivation layer covers the gate, the first field plate structure is arranged on the first passivation layer, the first field plate structure is arranged between the gate and the drain, and the shortest distance from the first field plate structure to the drain is shorter than the shortest distance from the first field plate structure to the gate.
2. The HEMT transistor according to claim 1, characterized in that: In the gate length direction, the cross-section shape of the first field plate structure is a trapezoid.
3. The HEMT transistor according to claim 1, wherein: The first field plate structure comprises a first transverse portion, a second transverse portion and a first longitudinal portion, wherein the first longitudinal portion connects the first transverse portion and the second transverse portion; the first transverse portion is located above the drain, and the second transverse portion is located between the drain and the gate and is disposed on the first passivation layer in the opposite direction of the x-direction; The x direction is the direction from the source to the drain.
4. The HEMT transistor according to any one of claims 2 or 3, characterized in that: In the gate length direction, the size of the first field plate structure ranges from 0.5 μm to 2 μm.
5. The HEMT transistor according to any one of claims 2 or 3, characterized in that: The distance from the bottom of the first field plate structure to the semiconductor epitaxial layer is 20 nm to 200 nm.
6. The HEMT transistor according to any one of claims 2 or 3, characterized in that: The shortest distance from the first field plate structure to the gate is greater than 0.5 μm.
7. The HEMT transistor according to any one of claims 2 or 3, characterized in that: The shortest distance from the first field plate structure to the drain electrode is in the range of 300 nm to 1 μm.
8. The HEMT transistor according to any one of claims 2 or 3, characterized in that: In the gate field direction, the ratio of the shortest distance from the first field plate structure to the drain to the sum of the shortest distance from the first field plate structure to the gate, the size of the first field plate structure and the shortest distance from the first field plate structure to the drain is in a range of 10% to 50%.
9. The HEMT transistor according to claim 1, characterized in that: The HEMT transistor further includes a second field plate structure, the second field plate structure is located between the gate and the first field plate structure, the second field plate structure includes a third lateral portion, a fourth lateral portion and a second longitudinal portion, the second longitudinal portion connects the third lateral portion and the fourth lateral portion; the third lateral portion is located above the gate, the fourth lateral portion is located between the gate and the first field plate structure and is disposed on the first passivation layer in the x direction; The x direction is the direction from the source to the drain.
10. A method for manufacturing a HEMT transistor, characterized in that: The steps include: forming a semiconductor epitaxial layer; forming a source electrode and a drain electrode opposite to each other on the semiconductor epitaxial layer; forming a gate; Covering the gate with a first passivation layer; forming a second photoresist layer, and forming a fourth window and a fifth window by a photolithography process; Metals are deposited in the fourth window and the fifth window to form a first field plate structure and a second field plate structure, respectively. The shortest distance from the first field plate structure to the drain is shorter than the shortest distance from the first field plate structure to the gate.
11. A radio frequency module, characterized in that: A HEMT transistor comprising the steps of: