Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a display area and a light-transmitting area located in the display area. The display panel comprises a driving circuit layer and a light-emitting layer. The driving circuit layer comprises a first pixel driving circuit and a second pixel driving circuit which are located in a display area and are arranged away from a light-transmitting area. A first pixel driving circuit is connected with a plurality of sub-pixels with the same color of the light-emitting layer, and a second pixel driving circuit is connected with one sub-pixel of the light-emitting layer; the first pixel driving circuit comprises a first driving transistor, and the second pixel driving circuit comprises a second driving transistor; the first driving transistor is connected with the anode ends of the plurality of corresponding sub-pixels, the second driving transistor is connected with the anode end of one corresponding sub-pixel, and the amount of current flowing through the first driving transistor in unit time is larger than the amount of current flowing through the second driving transistor. The local light transmittance is effectively improved on the basis that the overall display effect of the display panel is not affected.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The Pol-Less (PLP) technology can significantly improve the light output efficiency of the display panel by removing the polarizer on the light output side of the display panel, thereby increasing the display brightness and reducing the panel power consumption. However, after the polarization is cancelled, the reflectivity of the light output side of the display panel remains high, which seriously affects the display effect. In order to reduce the reflectivity, the PLP display panel uses a whole black pixel definition layer (Black Pixel Define Layer, BPDL) with a black matrix (Black Matrix, BM) to block the metal pattern and cathode, and only sets pixel openings corresponding to the light-emitting pixels on the BDPL for light output. This design causes the transmittance of the PLP display panel to light in each band to be almost zero. If a special design is not adopted, various types of light sensors (sensors) cannot be applied to the whole machine.

[0003] At present, in order to improve the local transmittance of PLP type display panels, an array wiring winding design is usually adopted to form at least one light-transmitting area, and holes are opened on BPDL and BM corresponding to the light-transmitting area to improve the transmittance of the light-transmitting area. However, with the continuous improvement of the pixel resolution (PPI) of display panels, the winding space on the array substrate of high-definition panel products such as FHD and WQ is insufficient, resulting in poor improvement of the local transmittance of the panel. Therefore, it is necessary to provide a solution that can effectively improve the local transmittance without affecting the display effect of the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device, which effectively improve the local light transmittance without affecting the overall display effect of the display panel.

[0005] In order to achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, comprising a first display area and a second display area, wherein at least one light-transmitting area is provided in the first display area;

[0006] The display panel comprises:

[0007] a driving circuit layer, comprising a plurality of first pixel driving circuits located in the first display area and avoiding the light-transmitting area, and a plurality of second pixel driving circuits located at least in the second display area; and

[0008] a light-emitting layer, located on one side of the driving circuit layer, and comprising a plurality of pixel units located in the first display area and the second display area, wherein the pixel unit comprises at least three sub-pixels of different colors; in the first display area, at least two of the pixel units, at least two of the sub-pixels of at least one same color are electrically connected to the same first pixel driving circuit; in the second display area, each of the second pixel driving circuits is electrically connected to only one sub-pixel;

[0009] Among them, the first pixel driving circuit includes a first driving transistor, and the second pixel driving circuit includes a second driving transistor; when the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode ends of the corresponding multiple sub-pixels, and the second driving transistor is electrically connected to the anode end of a corresponding one of the sub-pixels, and the current flowing through the first driving transistor per unit time is greater than the current flowing through the second driving transistor.

[0010] According to a second aspect of the present application, a display device is provided, comprising an optical element and the above-mentioned display panel, wherein the optical element is arranged corresponding to the light-transmitting area.

[0011] In the display panel and display device of the present application, a light-transmitting area is provided in the first display area, and by performing a "one-drive-many" design on at least part of the pixel driving circuits located in the first display area, a first pixel driving circuit in the first display area can simultaneously drive multiple sub-pixels of the same color to emit light, effectively reducing the number of pixel driving circuits in the first display area, thereby reducing the coverage area of ​​the pixel driving circuits in the first display area, and then increasing the area of ​​the light-transmitting area in the first display area, which is beneficial to improving the local light transmittance of the first display area. At the same time, in order to avoid the brightness of the sub-pixels in the first display area not meeting the requirements due to the "one-drive-many" design, thereby causing uneven display brightness in the first display area and the second display area, the embodiment of the present application performs a differentiated design on the current amount flowing through the first driving transistor of the first pixel driving circuit and the second driving transistor of the second pixel driving circuit per unit time, so that the current amount flowing through the first driving transistor per unit time is larger, thereby improving the current output capacity of the first pixel driving circuit, which is beneficial to improving the display brightness of the sub-pixels electrically connected to the first pixel driving circuit in the first display area, so that the display brightness of the first display area and the second display area is consistent, thereby improving the overall display effect of the display panel. Therefore, the embodiments of the present application can effectively improve the local light transmittance of the display panel without affecting the overall display effect of the display panel.

[0012] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0014] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0015] Figure 1 is a schematic diagram of an exemplary winding design on an array substrate;

[0016] Figure 2 is a top view of a display panel provided in an embodiment of the present application;

[0017] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at M-M';

[0018] Figure 4 yes Figure 2 Schematic diagram of the cross-sectional structure at N-N';

[0019] Figure 5 is a schematic diagram of a first pixel driving circuit provided in an embodiment of the present application;

[0020] Figure 6 is a schematic diagram of a second pixel driving circuit provided in an embodiment of the present application;

[0021] Figure 7 is a distribution diagram of the first pixel driving circuit and the second pixel driving circuit in the first display area and the second display area provided in an embodiment of the present application;

[0022] Figure 8 is another distribution schematic diagram of the first pixel driving circuit and the second pixel driving circuit in the first display area and the second display area provided in an embodiment of the present application;

[0023] Fig. 9 is a schematic diagram of the arrangement of sub-pixels in the first display area and the second display area provided in an embodiment of the present application;

[0024] Fig.10 This is a distribution diagram of a pixel driving circuit of an 8T3C architecture provided in an embodiment of the present application;

[0025] Fig.11It is a schematic structural diagram of a first driving transistor and a first switching transistor in a first pixel driving circuit, and a second driving transistor and a second switching transistor in a second pixel driving circuit provided in an embodiment of the present application;

[0026] Fig.12 It is a structural schematic diagram of a first storage capacitor, a first boost capacitor and a first adjustment capacitor in a first pixel driving circuit, and a second storage capacitor, a second boost capacitor and a second adjustment capacitor in a second pixel driving circuit provided in an embodiment of the present application;

[0027] Fig.13 is a distribution diagram of a first high potential signal line, a second high potential signal line, and a first reset signal line provided in an embodiment of the present application;

[0028] Fig.14 is a schematic diagram of the distribution of the second high potential signal line and the first reset signal line provided in an embodiment of the present application;

[0029] Fig.15 is a timing diagram of the first pixel driving circuit provided in an embodiment of the present application when it is working;

[0030] Fig.16 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] Figure 1 It shows an exemplary winding design on the array substrate. Figure 1 As shown, a high-transmittance area 4 is reserved by winding the horizontal wiring 2 (such as a scan line) and the vertical wiring 3 (such as a data line or a power signal line) on the array substrate 1, thereby achieving local light transmittance. This solution has a high feasibility for pixel designs below 420PPI. However, with the increase in PPI or the complexity of the pixel drive circuit design (such as 8T drive circuit design / FIAA design / Ramless design, etc.), the wiring density in the display area continues to increase, resulting in limited winding space for the wiring on the array substrate, making it impossible to improve the local light transmittance of the display panel through the winding design. In addition, while solving the local light transmittance of the display panel, the display brightness of different areas should also be kept consistent.

[0033] In order to solve the above technical problems, the embodiments of the present application improve a display panel and a display device, by driving at least part of the multiple sub-pixels of the same color in the display area where the high-transmittance area is located with the same pixel driving circuit (i.e., a "one-drive-many" design), thereby reducing the number of pixel driving circuits in the area, and further reducing the area occupied by the pixel driving circuits in the area. The saved space can be used as a light-transmittance area, thereby effectively solving the problem of local light transmittance of the display panel.

[0034] At the same time, the "one drive multiple" design will cause the corresponding sub-pixels to fail to reach high brightness, that is, when a single pixel driving circuit drives multiple sub-pixels of the same color at the same time, its current output capacity is limited, resulting in the multiple sub-pixels connected to it being unable to reach the preset high brightness value, thereby causing the display brightness of this area to be inconsistent with the display brightness of other display areas driven normally (such as the "one drive one" design), thereby affecting the overall display effect. In order to solve this problem, the embodiment of the present application also optimizes the design of part of the film layer of the display area corresponding to the "one drive multiple" pixel driving circuit, so that the display brightness of different areas of the display panel is consistent, effectively improving the overall display effect of the display panel.

[0035] like Figures 2 to 9 As shown, the embodiment of the present application provides a display panel 10, which includes a first display area 11 and a second display area 12, wherein at least one light-transmitting area 13 is provided in the first display area 11. It can be understood that the light-transmitting area 13 is used to set an optical element, and the light-transmitting area 13 has a large light transmittance, which can provide sufficient light for the optical element, and is conducive to improving the sensitivity of the optical element.

[0036] Specifically, Figure 3 and Figure 4 As shown, the display panel 10 includes a substrate layer 14 and a driving circuit layer 15 , a light emitting layer 16 and an encapsulation layer 17 stacked on the substrate layer 14 .

[0037] In some embodiments, the display panel 10 is an OLED panel, but is not limited thereto. The present application embodiment will be described by taking the OLED panel as an example.

[0038] In some embodiments, the substrate layer 14 includes a rigid substrate or a flexible substrate, which is not limited here. When the substrate layer 14 is a rigid substrate, the substrate layer 14 includes a glass substrate, but is not limited thereto. When the substrate layer 14 is a flexible substrate, the substrate layer 14 includes at least one polyimide (PI) layer, but is not limited thereto.

[0039] In some embodiments, the display panel 10 further includes a buffer layer (not shown) located between the substrate layer 14 and the driving circuit layer 15 .

[0040] Specifically, Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the driving circuit layer 15 includes a plurality of first pixel driving circuits 18 located in the first display area 11 and away from the light-transmitting area 13, and a plurality of second pixel driving circuits 19 located at least in the second display area 12. Figure 3 , Figure 4 and Fig. 9 As shown, the light emitting layer 16 is located on the side of the driving circuit layer 15 away from the substrate layer 14, and the light emitting layer 16 includes a plurality of pixel units 26 located in the first display area 11 and the second display area 12, and the pixel unit 26 includes at least three sub-pixels of different colors. In the first display area 11, at least two sub-pixels of at least one same color in at least two pixel units 26 are electrically connected to the same first pixel driving circuit 18. At least in the second display area 12, each second pixel driving circuit 19 is electrically connected to only one sub-pixel.

[0041] That is, each first pixel driving circuit 18 is connected to multiple sub-pixels with the same luminous color and is used to drive these sub-pixels to emit light simultaneously; each second pixel driving circuit 19 is connected to a sub-pixel and is used to drive this sub-pixel to emit light.

[0042] For the convenience of description, the sub-pixels connected to the first pixel driving circuit 18 are referred to as first-type sub-pixels 22, and the sub-pixels connected to the second pixel driving circuit 19 are referred to as second-type sub-pixels 21. Since each sub-pixel is a light-emitting unit or a light-emitting element, each first-type sub-pixel and each second-type sub-pixel is a light-emitting unit or a light-emitting element.

[0043] It can be understood that at least part of the pixel driving circuits located in the first display area 11 are of one-drive-many design, and all the pixel driving circuits located in the second display area 12 are of one-drive-one design.

[0044] For example, combined with Figure 7 and Fig. 9As shown, each pixel unit 26 includes a first sub-pixel 26a, a second sub-pixel 26b and a third sub-pixel 26c, wherein the first sub-pixel 26a is a blue sub-pixel (B), the second sub-pixel 26b is a red sub-pixel (R), and the third sub-pixel 26c is a green sub-pixel (G). The first sub-pixel 26a located in the first display area 11 is a first-type sub-pixel 22, and the first sub-pixel 26a located in the second display area 12, the second sub-pixel 26b and the third sub-pixel 26c located in the first display area 11 and the second display area 12 are second-type sub-pixels 21. In the first display area 11, each first pixel driving circuit 18 is electrically connected to two blue sub-pixels (B) in the column direction; in the second display area 12, each blue sub-pixel (B) is connected to a corresponding second pixel driving circuit 19; in the first display area 11 and the second display area 12, each red sub-pixel (R) is connected to a corresponding second pixel driving circuit 19, and each green sub-pixel (G) is connected to a corresponding second pixel driving circuit 19. Therefore, in the first display area 11 , there is a blank area between two adjacent first pixel driving circuits 18 in the column direction, which is used to set the light-transmitting area 13 .

[0045] Understandably, Figure 7 and Figure 8 The difference lies in that the distribution position of the first pixel driving circuit 18 is different, and correspondingly, the distribution position of the blue sub-pixels (B) electrically connected to the first pixel driving circuit 18 is different.

[0046] Combination Figures 3 to 5 As shown, the first pixel driving circuit 18 includes a first driving transistor T11, a first electrode of the first driving transistor T11 is connected to the node A1, and a second electrode of the first driving transistor T11 is connected to the node B1. Figure 6 As shown, the second pixel driving circuit 19 includes a second driving transistor T12, a first electrode of the second driving transistor T12 is connected to the node A2, and a second electrode of the second driving transistor T12 is connected to the node B2.

[0047] like Figure 5 and Figure 6 As shown, when the display panel is in the light-emitting stage, the first electrode of the first driving transistor T11 is electrically connected to the first high-potential signal terminal VDD1, and the second electrode of the first driving transistor T11 is electrically connected to the anode terminals of the corresponding multiple first-type sub-pixels 22. At the same time, the first electrode of the second driving transistor T12 is electrically connected to the second high-potential signal terminal VDD2, and the second electrode of the second driving transistor T12 is electrically connected to the anode terminal of a corresponding second-type sub-pixel 21, and the current flowing through the first driving transistor T11 per unit time is greater than the current flowing through the second driving transistor T12.

[0048] It can be understood that by increasing the amount of current flowing through the first driving transistor T11 per unit time, the current output capacity of the first pixel driving circuit 18 can be improved, which is beneficial to improving the luminous brightness of multiple sub-pixels connected thereto, so that the display brightness of the first display area 11 and the second display area 12 tends to be consistent.

[0049] In a specific embodiment, Fig.11 As shown, the first driving transistor T11 includes a first active portion 23, and the second driving transistor T12 includes a second active portion 24; the ratio of the channel width W1 to the channel length L1 of the first active portion 23 is greater than the ratio of the channel width W2 to the channel length L2 of the second active portion 24, so that the amount of current flowing through the first driving transistor T11 per unit time is greater than the amount of current flowing through the second driving transistor T12.

[0050] It can be understood that the embodiment of the present application makes a differentiated design for the ratio of the channel width to the channel length of the driving transistors of the first pixel driving circuit 18 and the second pixel driving circuit 19, so that the current flowing through the first driving transistor T11 of the first pixel driving circuit 18 is greater than the current flowing through the second driving transistor T12 of the second pixel driving circuit 19 in the same period of time, which can effectively increase the current flowing through the first driving transistor T11 when it is working, thereby effectively improving the current output capacity of the first pixel driving circuit 18, which is beneficial to improving the display brightness of multiple sub-pixels connected to the first pixel driving circuit 18, thereby facilitating the display brightness of the first display area 11 and the second display area 12 to be consistent.

[0051] Specifically, the first electrode is one of a source electrode and a drain electrode, and the second electrode is one of a source electrode and a drain electrode that is different from the first electrode. The embodiment of the present application is described by taking the first electrode as a source electrode and the second electrode as a drain electrode as an example.

[0052] Specifically, Figure 5 and Figure 6 As shown, the gate of the first driving transistor T11 is connected to the Q1 node for receiving a first driving gate signal, and the gate of the second driving transistor T12 is connected to the Q2 node for receiving a second driving gate signal. The first driving gate signal and the second driving gate signal may be the same or different.

[0053] Specifically, Figure 5 As shown, the anode terminal of the first type of sub-pixel 22 is connected to the C1 node in the first pixel driving circuit 18, and the cathode terminal of the first type of sub-pixel 22 is connected to the first low potential signal terminal VSS1 for receiving the first low potential power signal. Figure 6As shown, the anode terminal of the second type of sub-pixel 21 is connected to the C2 node in the second pixel driving circuit 19, and the cathode terminal of the second type of sub-pixel 21 is connected to the second low potential signal terminal VSS2 for receiving the second low potential power signal. The first low potential power signal and the second low potential power signal may be the same or different.

[0054] When the display panel is in the light-emitting stage, the C1 node is turned on and the B1 node is turned on, so that the current flowing through the first driving transistor T11 can pass through the B1 node and the C1 node to reach the anode end of the corresponding first-type sub-pixel 22, thereby driving the first-type sub-pixel 22 to emit light. At the same time, the C2 node is turned on and the B2 node is turned on, so that the current flowing through the second driving transistor T12 can pass through the B2 node and the C2 node to reach the anode end of the corresponding second-type sub-pixel 21, thereby driving the second-type sub-pixel 21 to emit light.

[0055] In some embodiments, Fig.11 As shown, the channel of the first active portion 23 is arranged in a straight line, and the channel of the second active portion 24 is arranged in a bent or curved shape. This design can effectively reduce the channel length L1 of the first active portion 23 and effectively increase the channel length L2 of the second active portion 24, so that it is relatively easy to achieve that the ratio of the channel width W1 of the first active portion 23 to the channel length L1 is greater than the ratio of the channel width W2 of the second active portion 24 to the channel length L2.

[0056] Of course, in other embodiments, the ratio of the channel width W1 of the first active portion 23 to the channel length L1 can be greater than the ratio of the channel width W2 of the second active portion 24 to the channel length L2 by increasing the channel width W1 of the first active portion 23 and / or reducing the channel width W2 of the second active portion 24 .

[0057] In a specific embodiment, the ratio of the channel width W1 to the channel length L1 of the first active portion 23 is 3.5 / 12, and the ratio of the channel width W2 to the channel length L2 of the second active portion 24 is 3 / 25, wherein the units of the channel width and the channel length may be micrometers, but are not limited thereto.

[0058] In some embodiments, the architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19 is the same, and only some devices (such as transistors and / or capacitors) or routings in the circuit are designed differently. This design allows the pixel driving circuits of the first display area 11 and the second display area 12 to be formed in the same process, which is conducive to simplifying the difficulty of making the driving circuit layer 15. The embodiment of the present application does not limit the architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19, which can be a 7T (containing 7 transistors) circuit architecture or an 8T (containing 8 transistors) circuit architecture, but is not limited to this. The embodiment of the present application will take the 8T3C architecture as an example to specifically describe the structure of the first pixel driving circuit 18 and the second pixel driving circuit 19.

[0059] In some embodiments, Figure 5 As shown, the first pixel driving circuit 18 further includes a first switch transistor T21, a first electrode of the first switch transistor T21 is connected to the first data signal terminal Data1, and a second electrode of the first switch transistor T21 is connected to the first electrode of the first driving transistor T11, for example, the two are connected at a node A1. Figure 6 As shown, the second pixel driving circuit 19 further includes a second switch transistor T22, a first electrode of the second switch transistor T22 is connected to the second data signal terminal Data2, and a second electrode of the second switch transistor T22 is connected to the first electrode of the second driving transistor T12, for example, the two are connected at a node A2. Fig.11 As shown, the first switch transistor T21 includes a third active portion 57, and the second switch transistor T22 includes a fourth active portion 58. The first drive transistor T11 and the second drive transistor T12 are both P-type thin film transistors, and the ratio of the channel width W3 to the channel length L3 of the third active portion 57 is smaller than the ratio of the channel width W4 to the channel length L4 of the fourth active portion 58.

[0060] It can be understood that the P-type thin film transistor is turned on at a low potential and turned off at a high potential, so the driving gate terminals of the first driving transistor T11 and the second driving transistor T12 can be turned on when a low voltage value is connected. The embodiment of the present application also makes a differentiated design for the ratio of the channel width to the channel length of the switch transistors of the first pixel driving circuit 18 and the second pixel driving circuit 19, which can weaken the writing ability of the first data signal terminal to the Q1 node (i.e., the gate terminal of the first driving transistor T11), thereby reducing the working potential of the Q1 node, making the first driving transistor T11 more fully turned on, which is conducive to further improving the current output capacity of the first pixel driving circuit 18.

[0061] In some embodiments, Fig.11As shown, the differentiated design of the active portion channel width-to-length ratios of the first switch transistor T21 and the second switch transistor T22 can be achieved by reducing the channel width W3 of the third active portion 57 and / or increasing the channel length L3 of the third active portion 57 .

[0062] In a specific embodiment, the ratio of the channel width W3 to the channel length L3 of the third active portion 57 is 1.6 / 6, and the ratio of the channel width W4 to the channel length L4 of the fourth active portion 58 is 1.8 / 4, wherein the units of the channel width and the channel length may be micrometers, but are not limited thereto.

[0063] In some embodiments, Figure 5 As shown, the first pixel driving circuit 18 also includes a first storage capacitor C11 and a first boost capacitor C21. One end of the first storage capacitor C11 is connected to the first high potential signal terminal VDD1, and the other end is connected to the gate of the first driving transistor T11. The first end of the first boost capacitor C21 is connected to the gate of the first switching transistor T21, and the other end is connected to the gate of the first driving transistor T11. Figure 6 As shown, the second pixel driving circuit 19 also includes a second storage capacitor C12 and a second boost capacitor C22. One end of the second storage capacitor C12 is connected to the second high potential signal terminal VDD2, and the other end is connected to the gate of the second driving transistor T12. The first end of the second boost capacitor C22 is connected to the gate of the second switch transistor T22, and the other end is connected to the gate of the second driving transistor T12. The first switch transistor T21 and the second switch transistor T22 are both P-type thin film transistors, the capacitance value of the first storage capacitor C11 is greater than the capacitance value of the second storage capacitor C12, and the capacitance value of the first boost capacitor C21 is less than the capacitance value of the second boost capacitor C22.

[0064] Specifically, the gate of the first switch transistor T21 is connected to the first scan control signal terminal Pscan11, and the gate of the second switch transistor T22 is connected to the second scan control signal terminal Pscan12. Since the first switch transistor T21 and the second switch transistor T22 are both P-type thin film transistors, when the first scan control signal terminal Pscan11 and the second scan control signal terminal Pscan12 provide a low-level scan signal, the first switch transistor T21 and the second switch transistor T22 are turned on, and when the first scan control signal terminal Pscan11 and the second scan control signal terminal Pscan12 provide a high-level scan signal, the first switch transistor T21 and the second switch transistor T22 are turned off.

[0065] It can be understood that, compared with the second pixel driving circuit 19, the storage capacitor in the first pixel driving circuit 18 is increased, and the boost capacitor in the first pixel driving circuit 18 is reduced. By increasing the first storage capacitor C11 in the first pixel driving circuit 18, the duration of the working potential of the Q1 node is increased, which is conducive to increasing the amount of current flowing through the first driving transistor T11 when it is working, thereby facilitating further improving the current output capacity of the first pixel driving circuit 18. By reducing the first boost capacitor C21, the gate terminal control signal of the first switching transistor T21 reduces the coupling amplitude of the potential pull-up of the Q1 node when it jumps, which is conducive to reducing the working potential of the Q1 node, so that the first driving transistor T11 is turned on more fully, which is conducive to further improving the current output capacity of the first pixel driving circuit 18.

[0066] It should be noted that the above-mentioned differentiated design of the ratio of the channel width to the channel length of the active part of the driving transistor and the differentiated design of the capacitance value of the storage capacitor and the boost capacitor can be implemented one by one or at the same time, and their purpose is to improve the current output capacity of the first pixel driving circuit 18.

[0067] In some embodiments, Figure 5 As shown, the first pixel driving circuit 18 further includes a first compensation transistor T31 and a first adjustment capacitor C31. The first electrode of the first compensation transistor T31 is connected to the second electrode of the first driving transistor T11, and the second electrode of the first compensation transistor T31 is connected to the gate of the first driving transistor T11. One end of the first adjustment capacitor C31 is connected to the gate of the first driving transistor T11, and the other end is connected to the gate of the first compensation transistor T31. Figure 6 As shown, the second pixel driving circuit 19 also includes a second compensation transistor T32 and a second adjustment capacitor C32. The first electrode of the second compensation transistor T32 is connected to the second electrode of the second driving transistor T12, and the second electrode of the second compensation transistor T32 is connected to the gate of the second driving transistor T12. One end of the second adjustment capacitor C32 is connected to the gate of the second driving transistor T12, and the other end is connected to the gate of the second compensation transistor T32. The first compensation transistor T31 and the second compensation transistor T32 are both N-type thin film transistors, and the capacitance value of the first adjustment capacitor C31 is greater than the capacitance value of the second adjustment capacitor C32.

[0068] Specifically, the gate of the first compensation transistor T31 is connected to the third scan control signal terminal Nscan11, and the gate of the second compensation transistor T32 is connected to the fourth scan control signal terminal Nscan12. Since the first compensation transistor T31 and the second compensation transistor T32 are both N-type thin film transistors, when the third scan control signal terminal Nscan11 and the fourth scan control signal terminal Nscan12 provide a high-level scan signal, the first compensation transistor T31 and the second compensation transistor T32 are turned on, and when the third scan control signal terminal Nscan11 and the fourth scan control signal terminal Nscan12 provide a low-level scan signal, the first compensation transistor T31 and the second compensation transistor T32 are turned off.

[0069] Specifically, the first compensation transistor T31 and the second compensation transistor T32 are in an on state during the data signal writing stage. On the one hand, the first compensation transistor T31 is used to compensate for the threshold voltage of the first driving transistor T11, and the second compensation transistor T32 is used to compensate for the threshold voltage of the second driving transistor T12; on the other hand, the first compensation transistor T31 is used to provide a path for data writing of the first pixel driving circuit 18, and the second compensation transistor T32 is used to provide a path for data writing of the second pixel driving circuit 19.

[0070] Specifically, a first regulating capacitor C31 is arranged between the gate of the first compensation transistor T31 and the gate of the first driving transistor T11, so that when the gate terminal of the first compensation transistor T31 jumps from a high potential to a low potential, it has a pull-down coupling effect on the potential of the Q1 node; a second regulating capacitor C32 is arranged between the gate of the second compensation transistor T32 and the gate of the second driving transistor T12, so that when the gate terminal of the second compensation transistor T32 jumps from a high potential to a low potential, it has a pull-down coupling effect on the potential of the Q2 node. This design is conducive to reducing the working potential of the Q1 node and the Q2 node, thereby facilitating the corresponding driving transistor to turn on.

[0071] It can be understood that the adjustment capacitor in the first pixel driving circuit 18 is increased compared with the second pixel driving circuit 19. By increasing the first adjustment capacitor C31, the coupling amplitude of the potential of the Q1 node when the gate terminal control signal of the first compensation transistor T31 jumps can be increased, so that the working potential of the Q1 node is further reduced, so that the first driving transistor T11 is turned on more fully, which is conducive to further improving the current output capacity of the first pixel driving circuit 18.

[0072] It should be noted that the differentiated design of the capacitance values ​​of the first adjustment capacitor C31 in the first pixel driving circuit 18 and the second adjustment capacitor C32 in the second pixel driving circuit 19 can be implemented separately or simultaneously with the other aforementioned schemes, and the purpose is to improve the current output capacity of the first pixel driving circuit 18.

[0073] In one embodiment, the capacitance of each capacitor is adjusted by adjusting the electrode coverage area of ​​each capacitor. Fig.12 As shown, the area of ​​the orthographic projection of the first storage capacitor C11 in the thickness direction of the display panel 10 is greater than the area of ​​the orthographic projection of the second storage capacitor C12 in the thickness direction of the display panel 10, so that the capacitance value of the first storage capacitor C11 is greater than the capacitance value of the second storage capacitor C12. The area of ​​the orthographic projection of the first boost capacitor C21 in the thickness direction of the display panel 10 is smaller than the area of ​​the orthographic projection of the second boost capacitor C22 in the thickness direction of the display panel 10, so that the capacitance value of the first boost capacitor C21 is smaller than the capacitance value of the second boost capacitor C22. The area of ​​the orthographic projection of the first adjustment capacitor C31 in the thickness direction of the display panel 10 is greater than the area of ​​the orthographic projection of the second adjustment capacitor C32 in the thickness direction of the display panel 10, so that the capacitance value of the first adjustment capacitor C31 is greater than the capacitance value of the second adjustment capacitor C32. Of course, in other embodiments, the capacitance value can also be adjusted by adjusting the spacing between the two electrodes of the capacitor.

[0074] In some embodiments, when the display panel 10 is in the light-emitting stage, the power supply voltage value connected to the first high-potential signal terminal VDD1 is greater than the power supply voltage value connected to the second high-potential signal terminal VDD2, and the power supply voltage value connected to the second high-potential signal terminal VDD2 is greater than 0. By increasing the power supply voltage value connected to the first high-potential signal terminal VDD1, it is beneficial to further improve the driving capability of the first pixel driving circuit 18.

[0075] It should be noted that the differentiated design of the power supply voltage values ​​connected to the first high potential signal terminal VDD1 and the second high potential signal terminal VDD2 can be implemented separately or simultaneously with the other aforementioned solutions, and the purpose is to improve the current output capability of the first pixel driving circuit 18.

[0076] In some embodiments, Fig.13As shown, the driving circuit layer 15 further includes a first high potential signal line LVDD1 and a second high potential signal line LVDD2 which are spaced apart from each other, the first high potential signal line LVDD1 is connected to the first high potential signal terminal VDD1, and the second high potential signal line LVDD2 is connected to the second high potential signal terminal VDD2. When the display panel 10 is in the light-emitting stage, the first high potential signal line LVDD1 provides a first high potential power supply voltage to the first high potential signal terminal VDD1, and the second high potential signal line LVDD2 provides a second high potential power supply voltage to the second high potential signal terminal VDD2, and the first high potential power supply voltage value is greater than the second high potential power supply voltage value.

[0077] In a specific embodiment, Fig.13 As shown, the first high potential signal line LVDD1 and the second high potential signal line LVDD2 extend in the same direction and are disposed in the same layer.

[0078] This design enables the high-potential power supply signals of the first pixel driving circuit 18 and the second pixel driving circuit 19 to be independently provided through two different high-potential signal lines, thereby providing different high-potential power supply signals to the first pixel driving circuit 18 and the second pixel driving circuit 19, which is conducive to achieving consistent display brightness in the first display area 11 and the second display area 12.

[0079] In some embodiments, in combination Figure 5 , Figure 6 and Fig.14 As shown, the first pixel driving circuit 18 also includes a first reset transistor T81, the second pixel driving circuit 19 also includes a second reset transistor T82, and the driving circuit layer 15 also includes a second high potential signal line LVDD2, a first reset signal line 25, and a second reset signal line (not shown in the figure). The first electrode of the first reset transistor T81 is connected to the first reset signal line 25, and the second electrode of the first reset transistor T81 is connected to the first electrode of the first driving transistor T11. The first electrode of the second reset transistor T82 is connected to the second reset signal line, and the second electrode of the second reset transistor T82 is connected to the first electrode of the second driving transistor T12. The first reset signal line 25 is also connected to the first high potential signal terminal VDD1; the second high potential signal line LVDD2 is connected to the second high potential signal terminal VDD2.

[0080] When the display panel 10 is in the light-emitting stage, the first reset signal line 25 provides a first high potential power supply voltage to the first high potential signal terminal VDD1, and the second high potential signal line LVDD2 provides a second high potential power supply voltage to the second high potential signal terminal VDD2, and the first high potential power supply voltage value is greater than the second high potential power supply voltage value.

[0081] It can be understood that in this embodiment, there is no need to additionally set a high-potential signal line for the first pixel driving circuit 18. Instead, the first reset signal line 25 is multiplexed as the high-potential signal line of the first pixel driving circuit 18, thereby further saving pixel space and facilitating further increasing the area of ​​the light-transmitting area 13, thereby further improving the transmittance of the first display area 11.

[0082] In some embodiments, the first reset transistor T81 and the second reset transistor T82 are both P-type thin film transistors, the gate of the first reset transistor T81 is connected to the fifth scan control signal terminal Pscan21, and the gate of the second reset transistor T82 is connected to the sixth scan control signal terminal Pscan22.

[0083] In some embodiments, Figure 5 As shown, the first pixel driving circuit 18 further includes a third reset transistor T41, a fourth reset transistor T71, a first light emission control transistor T51 and a second light emission control transistor T61. Figure 6 As shown, the second pixel driving circuit 19 further includes a fifth reset transistor T42, a sixth reset transistor T72, a third light emission control transistor T52 and a fourth light emission control transistor T62.

[0084] like Figure 5 As shown, the first electrode of the third reset transistor T41 is connected to the first reset signal terminal Vi_11, and the second electrode of the third reset transistor T41 is connected to the Q1 node. The first electrode of the fourth reset transistor T71 is connected to the second reset signal terminal Vi_21, and the second electrode of the fourth reset transistor T71 is connected to the C1 node. The first electrode of the first light-emitting control transistor T51 is connected to the first high potential signal terminal VDD1, the second electrode of the first light-emitting control transistor T51 is connected to the A1 node, and the first electrode of the first driving transistor T11 is connected to the A1 node. The first electrode of the second light-emitting control transistor T61 and the second electrode of the first driving transistor T11 are both connected to the B1 node, and the second electrode of the second light-emitting control transistor T61 is connected to the C1 node.

[0085] like Figure 6As shown, the first electrode of the fifth reset transistor T42 is connected to the third reset signal terminal Vi_12, and the second electrode of the fifth reset transistor T42 is connected to the Q2 node. The first electrode of the sixth reset transistor T72 is connected to the fourth reset signal terminal Vi_22, and the second electrode of the sixth reset transistor T72 is connected to the C2 node. The first electrode of the third light-emitting control transistor T52 is connected to the second high potential signal terminal VDD2, the second electrode of the third light-emitting control transistor T52 is connected to the A2 node, and the first electrode of the second driving transistor T12 is connected to the A2 node. The first electrode of the fourth light-emitting control transistor T62 and the second electrode of the second driving transistor T12 are both connected to the B2 node, and the second electrode of the fourth light-emitting control transistor T62 is connected to the C2 node.

[0086] In some embodiments, the third reset transistor T41 and the fifth reset transistor T42 are both N-type thin film transistors, and the fourth reset transistor T71, the first light emission control transistor T51, the second light emission control transistor T61, the sixth reset transistor T72, the third light emission control transistor T52 and the fourth light emission control transistor T62 are all P-type thin film transistors.

[0087] The gate of the third reset transistor T41 is connected to the seventh scan control signal terminal Nscan21, the gate of the fourth reset transistor T71 is connected to the fifth scan control signal terminal Pscan21, the gate of the fifth reset transistor T42 is connected to the eighth scan control signal terminal Nscan22, the gate of the sixth reset transistor T72 is connected to the sixth scan control signal terminal Pscan22, the gate of the first light-emitting control transistor T51 and the gate of the second light-emitting control transistor T61 are both connected to the first light-emitting control signal terminal EM1, and the gate of the third light-emitting control transistor T52 and the gate of the fourth light-emitting control transistor T62 are both connected to the second light-emitting control signal terminal EM2.

[0088] The first electrode of the first reset transistor T81 is connected to the fifth reset signal terminal Vi_31, and the first reset signal line 25 inputs an electrical signal to the first reset transistor T81 through the fifth reset signal terminal Vi_31; the first electrode of the second reset transistor T82 is connected to the sixth reset signal terminal Vi_32, and the second reset signal line inputs an electrical signal to the second reset transistor T82 through the sixth reset signal terminal Vi_32.

[0089] As can be seen from the above, the architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19 are the same. The embodiment of the present application can differentiate the channel width-to-length ratio of the active part of the driving thin film transistor and / or the switching thin film transistor in the first pixel driving circuit 18 and the second pixel driving circuit 19, and can also differentiate the capacitance values ​​of the three capacitors in the first pixel driving circuit 18 and the second pixel driving circuit 19. The voltage value of the high-potential signal end can also be differentiated. The purpose of the differentiated design is to improve the driving capability of the "one-drive-many" pixel driving circuit, thereby improving the consistency of the display brightness of the first display area 11 and the second display area 12.

[0090] Fig.10 FIG. 1 is a schematic diagram of wiring distribution of an exemplary 8T3C architecture pixel driving circuit. The architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19 in the embodiment of the present application is similar to FIG. Fig.10 The architecture is the same as described above. Specifically, Fig.10 T1 is a driving transistor, T2 is a switching transistor, T3 is a compensation transistor, T4 is a second reset transistor, T5 is a first light-emitting control transistor, T6 is a second light-emitting control transistor, T7 is a third reset transistor, T8 is a first reset transistor, C1 is a storage capacitor, C2 is a boost capacitor, and C3 is an adjustment capacitor.

[0091] It should be noted that the wiring distribution diagram of the second pixel driving circuit 19 in the embodiment of the present application can refer to Fig.10 , but not limited to this. The present application embodiment is based on Fig.10 The pixel driving circuit shown is taken as an example of the second pixel driving circuit 19 to describe the difference between the first pixel driving circuit 18 and the second pixel driving circuit 19.

[0092] like Fig.15 As shown, the working process of the first pixel driving circuit 18 of the 8T3C architecture described above includes the first reset stage, the data writing and compensation stage, the second reset stage and the light emitting stage in sequence. The first reset stage includes the first stage, the 1-1 stage, the 2nd stage and the 2-1 stage in the timing diagram, the data writing and compensation stage is the 3rd stage in the timing diagram, the second reset stage is the 4th stage in the timing diagram, and the light emitting stage is the 5th stage in the timing diagram.

[0093] In the first stage of the first reset stage, the fifth scan control signal terminal Pscan21 is connected to a low potential signal, controls the first reset transistor T81 and the fourth reset transistor T71 to turn on, resets the A1 node and the B1 node through the fifth reset signal terminal Vi_31, and resets the C1 node through the second reset signal terminal Vi_21. In the 1-1 stage of the first reset stage, the third scan control signal terminal Nscan11 is connected to a high potential signal, and the fifth scan control signal terminal Pscan21 is connected to a low potential signal, controls the first compensation transistor T31 to turn on, and resets the Q1 node through the fifth reset signal terminal Vi_31. In the second stage of the first reset stage, the seventh scan control signal terminal Nscan21 is connected to a high potential signal, controls the third reset transistor T41 to turn on, and resets the Q1 node. In the 2-1 stage of the first reset stage, the third scan control signal terminal Nscan11 and the seventh scan control signal terminal Nscan21 are simultaneously connected to high potential signals, controls the first compensation transistor T31 and the third reset transistor T41 to turn on, and resets the Q1 node and the B1 node.

[0094] In the data writing and compensation stage, the third scan control signal terminal Nscan11 is connected to a high potential signal, and the first scan control signal terminal Pscan11 is connected to a low potential signal, controlling the first driving transistor T11, the first switching transistor T21 and the first compensation transistor T31 to turn on, and the data signal is written to the Q1 node.

[0095] In the second reset stage, the fifth scan control signal terminal Pscan21 receives a low potential signal to control the first reset transistor T81 and the fourth reset transistor T71 to turn on, reset the A1 node and the B1 node through the fifth reset signal terminal Vi_31, and reset the C1 node through the second reset signal terminal Vi_21.

[0096] In the light-emitting stage, the first light-emitting control signal terminal EM1 is connected to a low-potential signal to control the first light-emitting control transistor T51 and the second light-emitting control transistor T61 to turn on, and the first high-potential signal flows to the anode end of the corresponding sub-pixel through the A1 node, the B1 node and the C1 node in sequence, and drives the sub-pixel to emit light.

[0097] It can be understood that the structure of the second pixel driving circuit 19 is the same as the architecture of the first pixel driving circuit 18, so the working processes of the two are the same. The working process of the second pixel driving circuit 19 can refer to the working process of the first pixel driving circuit 18 mentioned above, and will not be repeated here.

[0098] In some embodiments, Figure 3 and Figure 4As shown, the driving circuit layer 15 includes a first semiconductor layer 27, a first gate insulating layer 28, a first gate layer 29, a second gate insulating layer 30, a second gate layer 31, a first interlayer insulating layer 32, a second semiconductor layer 33, a third gate insulating layer 34, a third gate layer 35, a second interlayer insulating layer 36, a first source-drain electrode layer 37, a first organic planarization layer 38, a second source-drain electrode layer 39, a second planarization layer 40 and a third planarization layer 41 stacked on the substrate layer 14.

[0099] The first electrode and the second electrode mentioned above may be located in the first source-drain electrode layer 37 , the gate may be located in any one of the first gate layer 29 , the second gate layer 31 and the third gate layer 35 , and the active portion may be located in the first semiconductor layer 27 or the second semiconductor layer 33 .

[0100] In some embodiments, the first driving transistor T11 is a dual-gate low-temperature polysilicon thin film transistor, which includes an active portion 27a located in the first semiconductor layer 27, a first gate 29a located in the first gate layer 29, a second gate 31a located in the second gate layer 31, and a source and a drain located in the first source-drain electrode layer 37. The first compensation thin film transistor T31 is a metal oxide thin film transistor, which includes an active portion located in the second semiconductor layer 33, a third gate 31b located in the second gate layer 31, a fourth gate 35a located in the third gate layer 35, and a source and a drain located in the first source-drain electrode layer 37.

[0101] In some embodiments, the material of the first semiconductor layer 27 is polysilicon (poly), and the material of the second semiconductor layer 33 includes indium gallium zinc oxide (IGZO).

[0102] In some embodiments, the second driving transistor T12 is disposed in the same layer as the first driving transistor T11, for example, the active portion, gate, source and drain of the second driving transistor T12 correspond to the active portion, gate, source and drain of the first driving transistor T11 in a one-to-one manner and are located in the same film layer. Similarly, the second compensation thin film transistor T32 is also disposed in the same layer as the first compensation thin film transistor T31.

[0103] In some embodiments, the light emitting layer 16 is located on the third planarization layer 41 .

[0104] In some embodiments, Figure 3As shown, the light-emitting layer 16 includes a pixel defining layer 42 located in the first display area 11 and the second display area 12, and the pixel defining layer 42 is provided with a plurality of pixel openings located in the first display area 11 and the second display area 12, and a plurality of first light-transmitting openings 44 located in the first display area 11. Specifically, according to different types of pixel driving circuits, the pixel openings can be divided into a plurality of first pixel openings 43 located in the first display area 11 and a plurality of second pixel openings 45 located in the second display area 12. The first-type sub-pixel 22 is located in the first pixel opening 43, the second-type sub-pixel 21 is located in the second-type sub-pixel 21, and the first light-transmitting opening 44 is arranged in alignment with the light-transmitting area 13. The first-type sub-pixel 22 includes a first-type anode block 46 at least exposed in the first pixel opening 43, and the first-type anode blocks 46 of the plurality of first-type sub-pixels 22 electrically connected to the same first pixel driving circuit 18 are arranged in the same layer and connected to each other. The second type of sub-pixel 21 includes a second type of anode block 47 exposed in the second pixel opening 45 , and the second type of anode blocks 47 of a plurality of second type of sub-pixels 21 electrically connected to different second pixel driving circuits 19 are arranged spaced apart from each other.

[0105] When the display panel 10 is in the light emitting stage, the first driving transistor T11 is electrically connected to the first type anode blocks 46 of the corresponding plurality of first type sub-pixels 22 , and the second driving transistor T12 is electrically connected to the second type anode block 47 of the corresponding one second type sub-pixel 21 .

[0106] In some embodiments, the sub-pixels in the light-emitting layer 16 include OLED devices, but are not limited thereto. The present application embodiment is described by taking the sub-pixels as OLED devices as an example. In this case, each sub-pixel includes an anode, a light-emitting functional layer, and a cathode. Depending on the material of the light-emitting functional layer, the sub-pixels emit light of different colors.

[0107] In some embodiments, the display panel 10 further includes a color filter layer 48 located on the side of the light emitting layer 16 away from the driving circuit layer 15, and the color filter layer 48 includes a light shielding layer 49 and a color resist layer 50. The light shielding layer 49 is provided with a light outlet opening aligned with the pixel opening and a second light transparent opening 51 aligned with the first light transparent opening 44. Specifically, the light outlet opening can be divided into a first light outlet opening aligned with the first pixel opening 43 and a second light outlet opening aligned with the second pixel opening 45. The color resist layer 50 includes a first color resist unit 50a located in the first pixel opening 43 and a second color resist unit 50b located in the second pixel opening 45.

[0108] It can be understood that the color of each color-resistance unit is the same as the color of the sub-pixel in the corresponding pixel opening.

[0109] Among the multiple color resist units of the same color, the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the first pixel driving circuit 18 is smaller than the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the second pixel driving circuit 19 .

[0110] For example, when the first color resist unit 50a and the second color resist unit 50b have the same color, the thickness of the first color resist unit 50a corresponding to the first type of sub-pixel 22 is smaller than the thickness of the second color resist unit 50b corresponding to the second type of sub-pixel 21.

[0111] It can be understood that the embodiment of the present application adopts a color filter layer 48 to replace the existing polarizer, that is, the display panel 10 provided in the embodiment of the present application is a PLP type display panel 10. This design can significantly improve the light output efficiency of the display panel 10, thereby improving the display brightness of the display panel 10, and can reduce the power consumption of the display panel 10.

[0112] In some embodiments, the material of the pixel defining layer 42 in the light emitting layer 16 is a light shielding material. In this case, the pixel defining layer 42 can be called a black pixel defining layer (BPDL). The pixel defining layer 42 in the light emitting layer 16 and the light shielding layer 49 in the color filter layer 48 cooperate with each other to shield the first pixel driving circuit 18 and the second pixel driving circuit 19, and only light is emitted from the pixel opening and light is transmitted from the light transmission opening. This design can reduce the reflectivity and increase the local transmittance while improving the light extraction efficiency of the display panel 10.

[0113] In some embodiments, the encapsulation layer 17 is disposed between the light emitting layer 16 and the color filter layer 48 to protect the light emitting layer 16 .

[0114] In some embodiments, Fig. 9 As shown, in the first display area 11 and the second display area 12, a plurality of pixel units 26 are arranged in multiple rows and columns in the row direction and the column direction, and the row direction and the column direction are perpendicular to each other. Each pixel unit 26 includes a first sub-pixel 26a, a second sub-pixel 26b and a third sub-pixel 26c of different colors; the light-transmitting area 13 is located between two adjacent pixel units 26.

[0115] In the first display area 11 and the second display area 12, a plurality of first sub-pixels 26a are arranged in multiple rows and columns in the row direction and the column direction, a plurality of second sub-pixels 26b are arranged in multiple rows and columns in the row direction and the column direction, and a plurality of third sub-pixels 26c are arranged in multiple rows and columns in the row direction and the column direction. A row of second sub-pixels 26b and a row of third sub-pixels 26c are arranged between any two adjacent rows of first sub-pixels 26a; any row of first sub-pixels 26a and an adjacent row of second sub-pixels 26b are arranged alternately, and any row of second sub-pixels 26b and an adjacent row of third sub-pixels 26c are arranged in a one-to-one correspondence.

[0116] In the first display area 11 , in the column direction or the row direction, at least two sub-pixels of at least one same color are electrically connected to the same first pixel driving circuit 18 .

[0117] It can be understood that the sub-pixels of any color located in the first display area 11 can adopt the "one drives many" design. Of course, only the sub-pixels of some colors can adopt the "one drives many" design.

[0118] In some embodiments, the first sub-pixel 26a includes any one of a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), the second sub-pixel 26b includes any one of the red sub-pixel (R), the green sub-pixel (G), and the blue sub-pixel (B) that is different from the first sub-pixel 26a, and the third sub-pixel 26c includes any one of the red sub-pixel (R), the green sub-pixel (G), and the blue sub-pixel (B) that is different from the first sub-pixel 26a and the second sub-pixel 26b.

[0119] In a specific embodiment, the first sub-pixel 26a is a blue sub-pixel (B), the second sub-pixel 26b is a red sub-pixel (R), and the third sub-pixel 26c is a green sub-pixel (G). Below each row of blue sub-pixels (B) is a row of red sub-pixels (R) and a row of green sub-pixels (G). In the column direction, each row of red sub-pixels (R) is arranged in a one-to-one correspondence with an adjacent row of green sub-pixels (G), and each row of red sub-pixels (R) is arranged alternately with an adjacent row of blue sub-pixels (B). Each row of blue sub-pixels (B) and the row of red sub-pixels (R) and a row of green sub-pixels (G) below constitute a row of pixel units 26, and each pixel unit 26 includes blue sub-pixels (B), red sub-pixels (R) and green sub-pixels (G) arranged in a triangle.

[0120] In a specific embodiment, any two adjacent red sub-pixels (R) in a row manner are symmetrically arranged about a symmetry axis L extending along a column direction, and a blue sub-pixel (B) adjacent to the two red sub-pixels (R) is located on the symmetry axis L.

[0121] The following description will be made by taking the “one-drive-many” design of the first sub-pixel 26 a in the first display area 11 as an example.

[0122] In some embodiments, in the first display area 11, in the column direction, at least two adjacent first sub-pixels 26a are electrically connected to the same first pixel driving circuit 18. The second pixel driving circuit 19 is also located in the first display area 11 and is arranged away from the light-transmitting area 13. In the first display area 11, a plurality of second sub-pixels 26b and a plurality of third sub-pixels 26c are respectively electrically connected to a plurality of second pixel driving circuits 19 in a one-to-one correspondence. In this embodiment, only the first sub-pixel 26a adopts a "one-drive-many" design.

[0123] In a specific embodiment, in the first display area 11 , in any column of first sub-pixels 26 a , at least two adjacent first sub-pixels 26 a constitute a first sub-pixel group 20 , and the multiple first sub-pixels 26 a in each first sub-pixel group 20 are electrically connected to the same first pixel driving circuit 18 .

[0124] Specifically, each column of first sub-pixels 26 a constitutes a plurality of first sub-pixel groups 20 , and the plurality of first sub-pixel groups 20 located in two adjacent columns are arranged corresponding to each other or staggered with each other.

[0125] In the column direction, a light-transmitting region 13 is provided between every two adjacent first sub-pixel groups 20. Of course, a light-transmitting region 13 may be provided only between some of the two adjacent first sub-pixel groups 20.

[0126] In the embodiment of the present application, in order to improve the transmittance, a light-transmitting area 13 is provided between each two adjacent first sub-pixel groups 20, and the plurality of light-transmitting areas 13 are arranged in multiple columns. The plurality of light-transmitting areas 13 in two adjacent columns are arranged corresponding to each other or staggered with each other.

[0127] It can be understood that, since the sub-pixels in the same first sub-pixel group 20 are driven by the same first pixel driving circuit 18, the number of pixel driving circuits in the first display area 11 is greatly reduced, thereby greatly reducing the coverage area of ​​the driving circuit, so that the pixel driving circuit in the first display area 11 can be easily set away from the light-transmitting area 13, so the light-transmitting area 13 can be set in the area between two adjacent first sub-pixel groups 20, and there is enough space to set the pixel driving circuit while achieving local high transmittance. At this time, the first light-transmitting opening 44 on the pixel defining layer 42 and the second light-transmitting opening 51 on the light-shielding layer 49 can be aligned and set between the two adjacent first sub-pixel groups 20, so as to form a light-transmitting area 13.

[0128] In some embodiments, the first sub-pixel 26a located in the first display area 11 and the second display area 12 includes a first anode block 59a, and the display panel 10 further includes a plurality of first connection electrodes 52a and a plurality of first connection holes 53a located in the first display area 11, and a plurality of second connection electrodes 52b and a plurality of second connection holes 53b located in the second display area 12. The first connection electrodes 52a and the second connection electrodes 52b are disposed in the same layer as the first anode block 59a, and the first connection electrodes 52a and the second connection electrodes 52b both extend along the column direction.

[0129] The first connecting electrode 52a is located between any two adjacent first anode blocks 59a in the same first sub-pixel group 20, and the two ends of the first connecting electrode 52a are respectively connected to the two adjacent first anode blocks 59a; multiple first connecting holes 53a are arranged in a one-to-one correspondence with multiple first sub-pixel groups, and the first connecting hole 53a is connected to one of the first connecting electrodes 52a in the corresponding first sub-pixel group, and the first pixel driving circuit 18 is connected to the corresponding first connecting electrode 52a through the first connecting hole 53a, thereby realizing electrical connection with the corresponding first anode block 59a.

[0130] A second connecting electrode 52b and a second connecting hole 53b are provided on the periphery of each first anode block 59a located in the second display area 12, one end of the second connecting electrode 52b is connected to the corresponding first anode block 59a, and the other end is connected to the corresponding second connecting hole 53b, and a second pixel driving circuit 19 is electrically connected to the corresponding second connecting electrode 52b through the second connecting hole 53b, thereby achieving electrical connection with the corresponding first anode block 59a.

[0131] In a specific embodiment, the first sub-pixel group 20 includes two first sub-pixels 26a arranged adjacent to each other in the column direction, the first connection electrode 52a is located between the two first sub-pixels 26a in the same first sub-pixel group 20, and the first connection hole 53a is located between the two first sub-pixels 26a in the same first sub-pixel group 20 and is connected to the first connection electrode 52a. In the first display area 11, a plurality of first connection holes 53a are arranged in an array in the row direction and the column direction, and any two adjacent rows of first connection holes 53a are arranged one-to-one in the column direction, or any two adjacent rows of first connection holes 53a are arranged staggered in the column direction. In the second display area 12, a plurality of second connection holes 53b are arranged in an array in the row direction and the column direction, and any two adjacent rows of second connection holes 53b are arranged one-to-one in the column direction; each row of first connection holes 53a and a row of second connection holes 53b are arranged in the same row direction.

[0132] In some embodiments, the second sub-pixel 26b located in the first display area 11 and the second display area 12 includes a second anode block 59b, and the third sub-pixel 26c located in the first display area 11 and the second display area 12 includes a third anode block 59c. The display panel 10 also includes a plurality of third connection electrodes 52c, a plurality of fourth connection electrodes 52d, a plurality of third connection holes 53c, and a plurality of fourth connection holes 53d. A third connection electrode 52c and a third connection hole 53c are provided at the periphery of each second anode block 59b, and a fourth connection electrode 52d and a fourth connection hole 53d are provided at the periphery of each third anode block 59c.

[0133] One end of the third connection electrode 52c is connected to the corresponding second anode block 59b, and the other end is connected to the corresponding third connection hole 53c, and a second pixel driving circuit 19 is electrically connected to the corresponding third connection electrode 52c through the third connection hole 53c, thereby achieving electrical connection with the corresponding second anode block 59b. One end of the fourth connection electrode 52d is connected to the corresponding third anode block 59c, and the other end is connected to the corresponding fourth connection hole 53d, and a second pixel driving circuit 19 is electrically connected to the corresponding fourth connection electrode 52d through the fourth connection hole 53d, thereby achieving electrical connection with the corresponding third anode block 59c.

[0134] In a specific embodiment, the third connection electrode 52c and the fourth connection electrode 52d are arranged in parallel, and the angle between the third connection electrode 52c and the column direction is greater than 0 and less than 90°; the third connection hole 53c and the fourth connection hole 53d respectively corresponding to the second sub-pixel 26b and the third sub-pixel 26c in the same pixel unit 26 are arranged in the same row direction.

[0135] In some embodiments, in the first display area 11, each row of first connection holes 53a is arranged in the same row direction with a row of third connection holes 53c and fourth connection holes 53d. In the second display area 12, the second connection holes 53b, the third connection holes 53c and the fourth connection holes 53d respectively arranged corresponding to the first sub-pixel 26a, the second sub-pixel 26b and the third sub-pixel 26c in the same pixel unit 26 are arranged in the same row direction.

[0136] In some embodiments, the first display area 11 can be divided into a routing area 11a and a non-routing area 11b according to the distribution of the driving circuit layer, and the orthographic projection of the light-transmitting area 13 in the thickness direction of the display panel 10 is located in the orthographic projection of the non-routing area 11b in the thickness direction of the display panel 10; the first pixel driving circuit 18 and the second pixel driving circuit 19 located in the first display area 11 are both located in the routing area 11a.

[0137] It can be understood that the second display area 12 is a wiring area.

[0138] In some embodiments, the orthographic projections of the second sub-pixel 26b and the third sub-pixel 26c located in the first display area 11 in the thickness direction of the display panel 10 are located in the orthographic projection of the wiring area 11a in the thickness direction of the display panel 10, the orthographic projection of a portion of the first sub-pixel 26a located in the first display area 11 in the thickness direction of the display panel 10 is located in the orthographic projection of the wiring area 11a in the thickness direction of the display panel 10, and the orthographic projection of another portion of the first sub-pixel 26a located in the first display area 11 in the thickness direction of the display panel 10 is located in the orthographic projection of the non-wiring area 11b in the thickness direction of the display panel 10.

[0139] In a specific embodiment, the orthographic projection of one of the first sub-pixels 26 a disposed near the light-transmitting area 13 in the first sub-pixel group 20 in the thickness direction of the display panel 10 is located in the orthographic projection of the non-wiring area 11 b in the thickness direction of the display panel 10 .

[0140] In some embodiments, the display panel 10 also includes a touch layer 54 located between the encapsulation layer 17 and the color filter layer 48. The touch layer 54 includes a touch electrode layer 55 and a touch insulation layer 56. The touch electrode is arranged corresponding to the light shielding layer 49. The touch insulation layer 56 is located between the touch electrode and the color filter layer 48.

[0141] In the embodiment of the present application, a light-transmitting area 13 is provided in the first display area 11. By performing a "one-drive-many" design on at least part of the pixel driving circuits located in the first display area 11, a first pixel driving circuit 18 in the first display area 11 can simultaneously drive multiple sub-pixels of the same color to emit light, thereby effectively reducing the number of pixel driving circuits in the first display area 11, thereby reducing the coverage area of ​​the pixel driving circuits in the first display area 11, and further increasing the area of ​​the light-transmitting area 13 in the first display area 11, which is beneficial to improving the local light transmittance of the first display area 11. At the same time, in order to avoid the "one drive multiple" design causing the sub-pixels in the first display area 11 to fail to meet the requirements, thereby causing uneven display brightness in the first display area 11 and the second display area 12, the embodiment of the present application makes a differentiated design for the current amount flowing through the first driving transistor of the first pixel driving circuit 18 and the second driving transistor of the second pixel driving circuit 19 per unit time, so that the current amount flowing through the first driving transistor per unit time is larger, thereby improving the current output capacity of the first pixel driving circuit 18, which is conducive to improving the display brightness of the sub-pixels in the first display area 11 that are electrically connected to the first pixel driving circuit, so that the display brightness of the first display area 11 and the second display area 12 remain consistent, thereby improving the overall display effect of the display panel 10. Therefore, the embodiment of the present application can effectively improve the local light transmittance of the display panel 10 without affecting the overall display effect of the display panel 10.

[0142] like Fig.16 As shown, the embodiment of the present application further provides a display device 60 , which includes at least one optical element 61 and the display panel 10 described in the above embodiment, wherein the optical element 61 is arranged corresponding to the light-transmitting area 13 .

[0143] In some embodiments, the optical element 61 is disposed inside the display panel 10; in other embodiments, the optical element 61 is disposed on the back of the display panel 10 and is disposed corresponding to the first display area 11. The embodiments of the present application do not limit this. As long as the optical element 61 is disposed corresponding to the light-transmitting area 13, it is within the protection scope of the present application.

[0144] In some embodiments, when the optical element is disposed inside the display panel 10 , the number of the optical element may be one, which is disposed corresponding to the first display area 11 ; the number of the optical element may also be multiple, which are disposed one-to-one corresponding to the light-transmitting areas 13 .

[0145] In some embodiments, the optical element 61 includes a camera, an infrared sensor, an ambient light sensor, or a fingerprint reader, but is not limited thereto.

[0146] In the embodiment of the present application, since the light transmittance of the first display area 11 of the display panel 10 is improved, the sensitivity of the optical element 61 is improved, and at the same time, the display effects of different areas of the display device 60 are kept consistent.

[0147] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0148] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0149] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0150] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: It comprises a first display area and a second display area, wherein at least one light-transmitting area is provided in the first display area; The display panel comprises: a driving circuit layer, comprising a plurality of first pixel driving circuits located in the first display area and avoiding the light-transmitting area, and a plurality of second pixel driving circuits located at least in the second display area; and a light-emitting layer, located on one side of the driving circuit layer, and comprising a plurality of pixel units located in the first display area and the second display area, wherein the pixel unit comprises at least three sub-pixels of different colors; in the first display area, at least two of the pixel units, at least two of the sub-pixels of at least one same color are electrically connected to the same first pixel driving circuit; in the second display area, each of the second pixel driving circuits is electrically connected to only one sub-pixel; Among them, the first pixel driving circuit includes a first driving transistor, and the second pixel driving circuit includes a second driving transistor; when the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode ends of the corresponding multiple sub-pixels, and the second driving transistor is electrically connected to the anode end of a corresponding one of the sub-pixels, and the current flowing through the first driving transistor per unit time is greater than the current flowing through the second driving transistor.

2. The display panel according to claim 1, characterized in that: The first driving transistor includes a first active portion, the second driving transistor includes a second active portion, and a ratio of a channel width to a channel length of the first active portion is greater than a ratio of a channel width to a channel length of the second active portion.

3. The display panel according to claim 2, characterized in that: The channel of the first active part is arranged in a straight line, and the channel of the second active part is arranged in a bent shape or a curved shape.

4. The display panel according to claim 1, characterized in that: The first pixel driving circuit further includes a first switch transistor, a first electrode of the first switch transistor is connected to the first data signal terminal, and a second electrode of the first switch transistor is connected to the first electrode of the first driving transistor; The second pixel driving circuit further includes a second switch transistor, a first electrode of the second switch transistor is connected to the second data signal terminal, and a second electrode of the second switch transistor is connected to the first electrode of the second driving transistor; When the display panel is in a light emitting stage, the second electrode of the first driving transistor is electrically connected to the anode terminals of the corresponding plurality of sub-pixels, and the second electrode of the second driving transistor is electrically connected to the anode terminal of a corresponding one of the sub-pixels; Among them, the first driving transistor and the second driving transistor are P-type transistors, the first switching transistor includes a third active portion, the second switching transistor includes a fourth active portion, and the ratio of the channel width to the channel length of the third active portion is smaller than the ratio of the channel width to the channel length of the fourth active portion.

5. The display panel according to any one of claims 1 to 4, characterized in that: The first pixel driving circuit further includes a first switching transistor, a first storage capacitor and a first boosting capacitor; a first electrode of the first switching transistor is connected to a first data signal terminal, and a second electrode of the first switching transistor is connected to a first electrode of the first driving transistor; one end of the first storage capacitor is connected to a first high potential signal terminal, and the other end is connected to a gate of the first driving transistor; a first end of the first boosting capacitor is connected to a gate of the first switching transistor, and the other end is connected to a gate of the first driving transistor; The second pixel driving circuit further includes a second switch transistor, a second storage capacitor and a second boost capacitor; a first electrode of the second switch transistor is connected to the second data signal terminal, and a second electrode of the second switch transistor is connected to the first electrode of the second driving transistor; one end of the second storage capacitor is connected to the second high potential signal terminal, and the other end is connected to the gate of the second driving transistor; a first end of the second boost capacitor is connected to the gate of the second switch transistor, and the other end is connected to the gate of the second driving transistor; When the display panel is in a light-emitting stage, the first electrode of the first driving transistor is electrically connected to the first high-potential signal terminal, the second electrode of the first driving transistor is electrically connected to the anode terminals of the corresponding plurality of sub-pixels, the first electrode of the second driving transistor is electrically connected to the second high-potential signal terminal, and the second electrode of the second driving transistor is electrically connected to the anode terminal of a corresponding sub-pixel; The first switch transistor and the second switch transistor are both P-type thin film transistors, the capacitance value of the first storage capacitor is greater than the capacitance value of the second storage capacitor, and the capacitance value of the first boost capacitor is less than the capacitance value of the second boost capacitor.

6. The display panel according to claim 5, characterized in that: The first pixel driving circuit further includes a first compensation transistor and a first adjustment capacitor; a first electrode of the first compensation transistor is connected to a second electrode of the first driving transistor, and the second electrode of the first compensation transistor is connected to a gate of the first driving transistor; one end of the first adjustment capacitor is connected to the gate of the first driving transistor, and the other end is connected to the gate of the first compensation transistor; The second pixel driving circuit further includes a second compensation transistor and a second adjustment capacitor; a first electrode of the second compensation transistor is connected to a second electrode of the second driving transistor, and a second electrode of the second compensation transistor is connected to a gate of the second driving transistor; one end of the second adjustment capacitor is connected to the gate of the second driving transistor, and the other end is connected to the gate of the second compensation transistor; Wherein, both the first compensation transistor and the second compensation transistor are N-type thin film transistors, and the capacitance value of the first adjustment capacitor is greater than the capacitance value of the second adjustment capacitor.

7. The display panel according to claim 1, characterized in that: When the display panel is in the light-emitting stage, the first electrode of the first driving transistor is electrically connected to the first high-potential signal terminal, the second electrode of the first driving transistor is electrically connected to the anode terminals of the corresponding multiple sub-pixels, the first electrode of the second driving transistor is electrically connected to the second high-potential signal terminal, the second electrode of the second driving transistor is electrically connected to the anode terminal of a corresponding sub-pixel, the power supply voltage value connected to the first high-potential signal terminal is greater than the power supply voltage value connected to the second high-potential signal terminal, and the power supply voltage value connected to the second high-potential signal terminal is greater than 0.

8. The display panel according to claim 7, characterized in that: The driving circuit layer further includes a first high potential signal line and a second high potential signal line spaced apart from each other, wherein the first high potential signal line is connected to the first high potential signal terminal, and the second high potential signal line is connected to the second high potential signal terminal.

9. The display panel according to claim 7, characterized in that: The first pixel driving circuit layer further includes a first reset transistor, the second pixel driving circuit layer further includes a second reset transistor, and the driving circuit layer further includes a second high potential signal line, a first reset signal line, and a second reset signal line; A first electrode of the first reset transistor is connected to the first reset signal line, and a second electrode of the first reset transistor is connected to the first electrode of the first drive transistor; a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to the first electrode of the second drive transistor; The first reset signal line is also connected to the first high potential signal terminal, and the second high potential signal line is connected to the second high potential signal terminal.

10. The display panel according to claim 1, characterized in that: The light-emitting layer includes a pixel defining layer located in the first display area and the second display area, and the pixel defining layer is provided with a plurality of pixel openings located in the first display area and the second display area, and a plurality of first light-transmitting openings located in the first display area; The sub-pixel is located in the pixel opening, and the first light-transmitting opening is arranged in alignment with the light-transmitting area; The sub-pixel comprises an anode block at least partially exposed in the pixel opening, the anode blocks of a plurality of the sub-pixels electrically connected to the same first pixel driving circuit are arranged in the same layer and connected to each other; the anode blocks of a plurality of the sub-pixels electrically connected to different second pixel driving circuits are arranged at intervals from each other; When the display panel is in a light emitting stage, the first driving transistor is electrically connected to the anode blocks of the corresponding plurality of sub-pixels, and the second driving transistor is electrically connected to the anode block of a corresponding one sub-pixel.

11. The display panel according to claim 10, characterized in that: The display panel further comprises a color filter layer located on a side of the light-emitting layer away from the driving circuit layer; the color filter layer comprises a light shielding layer and a color color resist layer; the light shielding layer is provided with a light outlet opening aligned with the pixel opening and a second light-transmitting opening aligned with the first light-transmitting opening; the color color resist layer comprises a color resist unit located in the light outlet opening, and the color of the color resist unit is the same as the color of the sub-pixel in the corresponding pixel opening; Among the plurality of color resist units of the same color, the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the first pixel driving circuit is smaller than the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the second pixel driving circuit.

12. The display panel according to claim 1, characterized in that: In the first display area and the second display area, the plurality of pixel units are arranged in a plurality of rows and columns in a row direction and a column direction, and the row direction and the column direction are perpendicular to each other; each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel of different colors; and the light-transmitting area is located between two adjacent pixel units; In the first display area and the second display area, a plurality of the first sub-pixels are arranged in a plurality of rows and columns in the row direction and the column direction, a plurality of the second sub-pixels are arranged in a plurality of rows and columns in the row direction and the column direction, and a plurality of the third sub-pixels are arranged in a plurality of rows and columns in the row direction and the column direction; a row of the second sub-pixels and a row of the third sub-pixels are arranged between any two adjacent rows of the first sub-pixels; any row of the first sub-pixels and an adjacent row of the second sub-pixels are arranged alternately, and any row of the second sub-pixels and an adjacent row of the third sub-pixels are arranged in a one-to-one correspondence; In the first display area, in the column direction or the row direction, at least two sub-pixels of at least one same color are electrically connected to the same first pixel driving circuit.

13. The display panel according to claim 12, characterized in that: In the first display area, in the column direction, at least two adjacent first sub-pixels are electrically connected to the same first pixel driving circuit; The second pixel driving circuit is also located in the first display area and is arranged away from the light-transmitting area; in the first display area, a plurality of the second sub-pixels and a plurality of the third sub-pixels are electrically connected to a plurality of the second pixel driving circuits in a one-to-one correspondence.

14. The display panel according to claim 13, characterized in that: In the first display area, in any column of the first sub-pixels, at least two adjacent first sub-pixels constitute a first sub-pixel group, and a plurality of the first sub-pixels in each first sub-pixel group are electrically connected to the same first pixel driving circuit; Each column of the first sub-pixels constitutes a plurality of the first sub-pixel groups, and the plurality of the first sub-pixel groups located in two adjacent columns are arranged corresponding to each other or staggered with each other; in the column direction, one light-transmitting area is provided between each two adjacent first sub-pixel groups.

15. The display panel according to claim 14, characterized in that: The first sub-pixel located in the first display area and the second display area includes a first anode block, and the display panel further includes a plurality of first connection electrodes and a plurality of first connection holes located in the first display area, and a plurality of second connection electrodes and a plurality of second connection holes located in the second display area; the first connection electrode and the second connection electrode are arranged in the same layer as the first anode block, and the first connection electrode and the second connection electrode both extend along the column direction; The first connection electrode is located between any two adjacent first anode blocks in the same first sub-pixel group, and both ends of the first connection electrode are respectively connected to the two adjacent first anode blocks; a plurality of first connection holes are arranged in one-to-one correspondence with a plurality of first sub-pixel groups, the first connection hole is connected to one of the first connection electrodes in the corresponding first sub-pixel group, and the first pixel driving circuit is connected to the corresponding first connection electrode through the first connection hole; A second connecting electrode and a second connecting hole are provided on the periphery of each first anode block located in the second display area, one end of the second connecting electrode is connected to the corresponding first anode block, and the other end is connected to the corresponding second connecting hole, and a second pixel driving circuit is electrically connected to the corresponding second connecting electrode through the second connecting hole.

16. The display panel according to claim 15, characterized in that: The first sub-pixel group includes two first sub-pixels arranged adjacent to each other in the column direction, the first connecting electrode is located between the two first sub-pixels in the same first sub-pixel group, and the first connecting hole is located between the two first sub-pixels in the same first sub-pixel group and connected to the first connecting electrode; In the first display area, a plurality of the first connection holes are distributed in an array in the row direction and the column direction, and any two adjacent rows of the first connection holes are arranged in a one-to-one correspondence in the column direction, or any two adjacent rows of the first connection holes are arranged staggered in the column direction; In the second display area, a plurality of the second connection holes are distributed in an array in the row direction and the column direction, and any two adjacent rows of the second connection holes are arranged in a one-to-one correspondence in the column direction; each row of the first connection holes and a row of the second connection holes are arranged in the same row direction.

17. The display panel according to claim 16, characterized in that: The second sub-pixels located in the first display area and the second display area include second anode blocks, and the third sub-pixels located in the first display area and the second display area include third anode blocks; the display panel further includes a plurality of third connection electrodes, a plurality of fourth connection electrodes, a plurality of third connection holes, and a plurality of fourth connection holes; a third connection electrode and a third connection hole are disposed on the periphery of each of the second anode blocks, and a fourth connection electrode and a fourth connection hole are disposed on the periphery of each of the third anode blocks; One end of the third connection electrode is connected to the corresponding second anode block, and the other end is connected to the corresponding third connection hole, and the second pixel driving circuit is electrically connected to the corresponding third connection electrode through the third connection hole; one end of the fourth connection electrode is connected to the corresponding third anode block, and the other end is connected to the corresponding fourth connection hole, and the second pixel driving circuit is electrically connected to the corresponding fourth connection electrode through the fourth connection hole; The third connecting electrode and the fourth connecting electrode are arranged in parallel, and the angle between the third connecting electrode and the column direction is greater than 0 and less than 90°; the third connecting hole and the fourth connecting hole respectively corresponding to the second sub-pixel and the third sub-pixel in the same pixel unit are arranged in the same row direction.

18. The display panel according to claim 17, characterized in that: In the first display area, each row of the first connection holes is arranged in the same row as a row of the third connection holes and a row of the fourth connection holes in the row direction; In the second display area, the second connection hole, the third connection hole and the fourth connection hole respectively corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel in the same pixel unit are arranged in the same row in the row direction.

19. A display device, characterized in that: The device comprises an optical element and a display panel as claimed in any one of claims 1 to 18, wherein the optical element is arranged corresponding to the light-transmitting area.

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