Chip test piece and preparation method thereof, and method for measuring coverage rate of heat-conducting filling layer

Abstract

The embodiment of the invention discloses a chip test piece, a preparation method and a method for measuring the coverage rate of a heat conduction filling layer, the chip test piece comprises a substrate, a chip module and a first heat conduction filling layer, the chip module comprises a cover sheet, a first bonding layer, a sensor film layer and a chip which are sequentially arranged from top to bottom, and the chip is welded and fixed on the surface of the substrate. And the sensor film layer comprises a plurality of capacitive sensors which are uniformly arranged in the flexible dielectric layer in an array mode. According to the embodiment of the invention, the TIM coverage rate can be obtained by converting the pressure distribution at the first heat-conducting filling layer into the change of the capacitance values of the plurality of capacitive sensor arrays and measuring and counting the proportion of the number of the capacitive sensors with the capacitance values within the preset range to the total number. According to the embodiment of the invention, the problem of measuring the coverage rate of the thermal interface material inside or on the surface of the chip package can be solved, so that a more accurate reference index is provided for the design and application of the TIM material.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and more specifically to a chip test piece and a preparation method thereof, and a method for measuring the coverage of a thermal conductive filling layer. Background Art

[0002] In recent years, in order to meet the demand for chip computing power, the computing power density and power consumption density of the new generation of chips have continuously exceeded previous specifications. Correspondingly, the heat dissipation challenges of chips have also increased rapidly. Due to the different thermal expansion characteristics and stiffness characteristics of various components in the chip package, temperature loads and mechanical loads during manufacturing, assembly, and application will cause the chip package to exhibit different modes and degrees of warping deformation, thereby affecting the coverage effect of the thermal interface material (TIM) inside or on the surface of the chip package. Since the thermal interface material (TIM) is a key link in the chip heat dissipation path, the selection of its material and the adaptability of the structural warping and the coverage detection method are issues that need to be focused on when formulating chip heat dissipation solutions. Summary of the invention

[0003] In view of this, the embodiments of the present invention provide a chip test piece and a preparation method, and a method for measuring the coverage of a thermal conductive filling layer, which can solve the problem of measuring the coverage of thermal interface materials inside or on the surface of a chip package, thereby providing a more accurate reference indicator for the design and application of TIM materials.

[0004] In a first aspect, an embodiment of the present invention provides a chip test piece, wherein the chip test piece comprises:

[0005] substrate;

[0006] A chip module, comprising a cover sheet, a first adhesive layer, a sensor film layer and a chip arranged in sequence from top to bottom, wherein the chip is welded and fixed on the surface of the substrate, the sensor film layer is integrated on the chip, and the cover sheet is bonded to the sensor film layer through the first adhesive layer;

[0007] A first heat-conducting filling layer is arranged on the surface of the cover sheet;

[0008] Among them, the sensor film layer includes multiple capacitive sensors and a flexible dielectric layer, the multiple capacitive sensors are evenly arranged in the flexible dielectric layer in an array manner, and the proportion of capacitive sensors with capacitance values ​​within a predetermined range among the multiple capacitive sensors represents the coverage rate of the first thermal conductive filling layer.

[0009] Optionally, the capacitive sensor is a variable-pole-distance capacitive sensor, and the upper electrode plate and the lower electrode plate of each capacitive sensor are arranged vertically and overlapped in position.

[0010] Optionally, the upper plate and the lower plate of each capacitive sensor have the same shape, which are rectangular or circular.

[0011] Optionally, the upper plates and the lower plates of the plurality of capacitive sensors are respectively arranged in an array and are evenly arranged on the upper surface and the lower surface of the flexible dielectric layer; or,

[0012] The upper plates and the lower plates of the plurality of capacitive sensors are respectively and evenly arranged in an array inside the flexible dielectric layer; or,

[0013] An array of upper plates of the plurality of capacitive sensors is disposed on the cover sheet, and an array of lower plates of the plurality of capacitive sensors is disposed on the flexible dielectric layer; or,

[0014] An array of upper plates of the plurality of capacitive sensors is arranged on the flexible dielectric layer, and an array of lower plates of the plurality of capacitive sensors is arranged on the chip; or,

[0015] An array of upper plates of the plurality of capacitive sensors is arranged on the cover plate, and an array of lower plates of the plurality of capacitive sensors is arranged on the chip.

[0016] Optionally, the chip test piece further comprises a metal cover, the inner top surface of the metal cover is in contact with and connected to the first thermal conductive filling layer, and the bottom surface of the metal cover is sealed and connected to the substrate via a second adhesive layer.

[0017] Optionally, the chip test piece further includes a circuit board, the substrate is disposed on the circuit board, and the substrate is interconnected with the circuit board.

[0018] Optionally, the chip test piece further comprises a heat sink disposed above the metal cover, a second heat-conducting filling layer is disposed between the heat sink and the metal cover, and the heat sink is connected to the circuit board via a locking member.

[0019] Optionally, the chip test piece further comprises a heat sink, and the heat sink is arranged above the first thermal conductive filling layer;

[0020] The chip test piece also includes a metal ring and a circuit board. The bottom surface of the metal ring is sealed and connected to the substrate through a second adhesive layer. The chip module is located in the metal ring. The substrate is arranged on the circuit board, and the substrate and the circuit board are interconnected.

[0021] Optionally, the chip test piece further includes a bottom filling layer filled between the chip and the substrate.

[0022] Optionally, the material of the first thermally conductive filling layer is one of gel, silicone grease, graphite, and solid / liquid metal, and the material of the cover sheet is silicon or an organic material.

[0023] In a second aspect, an embodiment of the present invention provides a method for preparing a chip test piece, the method comprising:

[0024] Fabricate metal routing circuits, pads, and through-silicon vias on the top surface of the first wafer;

[0025] Grinding the back side of the first wafer to a predetermined thickness and exposing the end of the through silicon via;

[0026] Manufacturing the sensor film layer on the back side of the first wafer by semiconductor process;

[0027] cutting the first wafer having the sensor thin film layer into dies;

[0028] grinding the second wafer to a predetermined thickness;

[0029] bonding the die to the polished second wafer using the first bonding layer;

[0030] Cutting the bonded dies into chip modules;

[0031] The chip module is welded and fixed on a substrate, on which a metal wiring circuit is made;

[0032] Filling the bottom filling material into the gap between the chip module and the substrate and curing it to form a bottom filling layer;

[0033] Arranging a first thermally conductive filling layer on the upper surface of the chip module or the lower surface of the metal cover;

[0034] A second adhesive layer is applied on the edge of the substrate, and the metal cover is bonded to the substrate. The metal cover is connected to the chip module through the first heat-conducting filling layer.

[0035] Optionally, the preparation method further comprises:

[0036] A substrate is disposed on a circuit board, the substrate being interconnected with the circuit board.

[0037] Optionally, the preparation method further comprises:

[0038] Arranging a second thermally conductive filling layer on the upper surface of the metal cover or the lower surface of the heat sink;

[0039] The heat sink is arranged above the metal cover, and the heat sink is locked with the circuit board.

[0040] In a third aspect, an embodiment of the present invention provides a method for measuring the coverage of a thermally conductive filling layer, the method comprising:

[0041] Connecting a capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip test piece;

[0042] Recording the capacitance value of each capacitive sensor in the chip test piece;

[0043] Connecting a capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip control test piece;

[0044] Recording the capacitance value of each capacitive sensor in the chip control test piece;

[0045] Calculating the difference in capacitance values ​​of the capacitive sensors at the same position in the chip test piece and the control test piece;

[0046] When the difference is within a predetermined range, it is determined that the first thermally conductive filling layer above the capacitive sensor is in a good coverage state;

[0047] The ratio of the number of capacitance sensors whose difference values ​​are within a predetermined range to the total number of capacitance sensors is calculated, and the ratio represents the coverage rate of the first thermally conductive filling layer.

[0048] The chip test piece of the embodiment of the present invention includes a substrate, a chip module, and a first thermal conductive filling layer. The chip module includes a cover sheet, a first adhesive layer, a sensor film layer and a chip arranged in sequence from top to bottom, and the chip is welded and fixed on the surface of the substrate. The sensor film layer includes a plurality of capacitive sensors uniformly arranged in an array in a flexible dielectric layer. In this embodiment, the TIM coverage can be obtained by converting the pressure distribution at the first thermal conductive filling layer into a change in the capacitance value of a plurality of capacitive sensor arrays, and measuring the ratio of the number of capacitive sensors with capacitance values ​​within a predetermined range to the total number. This embodiment can solve the problem of measuring the coverage of thermal interface materials inside or on the surface of a chip package, thereby providing a more accurate reference indicator for the design and application of TIM materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0050] Figure 1 It is a cross-sectional view of a metal cover chip package single product;

[0051] Figure 2 This is a cross-sectional view of a metal cover chip package unit after warping and deformation;

[0052] Figure 3 is a cross-sectional view of a chip test piece according to an embodiment of the present invention;

[0053] Figure 4is a cross-sectional view of a chip control test piece according to an embodiment of the present invention;

[0054] Figure 5 is a top view of a sensor film layer of a chip test piece according to an embodiment of the present invention;

[0055] Figure 6 is a cross-sectional view of a chip test piece according to an embodiment of the present invention mounted on a circuit board;

[0056] Figure 7 is a cross-sectional view of a chip test piece according to an embodiment of the present invention after being mounted on a circuit board and having a heat sink assembled;

[0057] Figure 8 is a cross-sectional view of a bare chip type chip test piece according to an embodiment of the present invention after being mounted on a circuit board and having a heat sink assembled;

[0058] Fig. 9 is a flow chart of a method for preparing a chip test piece according to an embodiment of the present invention;

[0059] Fig.10 It is a structural schematic diagram of each step in the process of preparing a chip test piece according to an embodiment of the present invention;

[0060] Fig.11 It is a flow chart of a method for measuring TIM coverage according to an embodiment of the present invention.

[0061] Reference numerals:

[0062] 1-substrate; 2-chip module; 21-cover; 22-first adhesive layer; 23-sensor film layer; 231-capacitive sensor; 232-flexible dielectric layer; 233-upper electrode; 234-lower electrode; 24-chip; 3-first thermal conductive filling layer; 4-metal cover; 5-second adhesive layer; 6-circuit board; 7-second thermal conductive filling layer; 8-bottom filling layer; 9-heat sink; 10-metal ring. DETAILED DESCRIPTION

[0063] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0064] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0065] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0066] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0067] Figure 1 This is a cross-sectional view of a metal lid chip package unit. Figure 2 for Figure 1 The cross-sectional view of the metal cover chip package monomer product after warping. Figure 1 As shown, in the metal-lid chip package monomer product, the chip 24 and the substrate 1 are formed into a whole through metal welding and the curing of the bottom filler (the solder joints are omitted in the figure). It should be noted that the bottom filler plays a role in protecting the solder joints, but in some embodiments there may be only solder joints without bottom filler. A thermal interface material (TIM) is provided between the upper surface of the chip 24 and the lower surface of the metal cover for heat conduction, and the metal cover and the substrate are fixed by an adhesive. The thermal expansion characteristics and stiffness characteristics of each component in the metal-lid chip package monomer product are different, and during the manufacturing process of the package monomer, it will experience a variety of temperature loads and mechanical loads. In a high-temperature environment, the package monomer product is close to a flat state, which is different from the Figure 1 In the process of the ambient temperature dropping from high temperature to room temperature, since the shrinkage of the substrate 1 exceeds that of the chip 24 and the metal cover has a large rigidity and is not prone to bending and deformation, the packaged single product may show the following Figure 2 The warping situation in Figure 2 As shown in FIG. 1 , after the warping deformation occurs, the center portion of the thermal conductive filling layer (i.e., TIM formation) inside the package unit product is fully pressed, and a gap or separation occurs between the edge portion and the chip 24. It should be noted that due to the diversity of internal material selection and structural design solutions of the package, in addition to Figure 2 In addition to the warping deformation states shown, there may be other warping states, such as a downward bulge at the center of the chip or non-negligible deformation on the metal cover. Warping deformation affects the coverage of the TIM inside or on the surface of the product, and has a significant impact on the heat dissipation efficiency, stability and service life of the product. Therefore, during the production process, it is necessary to measure the TIM coverage of the product to ensure that it meets the requirements.

[0068] For measurement Figure 1The TIM coverage of the product part shown in the figure can be measured by designing a chip test piece with an internal pressure sensor, and its structure should be as identical or equivalent to the product part as possible to ensure the accuracy of the TIM coverage measurement.

[0069] Figure 3 , Figure 6 , Figure 7 , Figure 8 It is a cross-sectional view of the chip test piece of the embodiment of the present application. Among them, the TIM coverage can be specifically expressed as the ratio of the area actually covered by the TIM to the surface area of ​​the component (i.e., chip) that the TIM is intended to cover. Therefore, the measurement principle of the chip test piece of the embodiment of the present application is to first divide the TIM area into multiple small areas, and then convert the pressure condition of the TIM on the small area into the output of the sensor under the area, and then determine whether the TIM is well pressed on the small area, and finally count the number of small areas with good pressing, calculate its ratio to the total number of small areas, and obtain the TIM coverage.

[0070] Figure 3 Figure 1 is a cross-sectional view of a metal-covered chip test piece. Figure 3 As shown, the chip test piece includes a substrate 1, a chip module 2, a first thermal conductive filling layer 3 and a metal cover 4. In this embodiment, the metal cover 4 is bonded to the edge of the substrate 1 through a second adhesive layer 5, and an accommodation space is formed therebetween. The chip module 2 and the first thermal conductive filling layer 3 are arranged in the accommodation space, thereby forming a metal cover type chip test piece.

[0071] Figure 3 The chip test piece shown is Figure 1 The difference of the product part shown is that the chip in the product part is replaced by a chip module 2 consisting of a cover sheet 21, a first adhesive layer 22, a sensor film layer 23 and a chip 24. Specifically, the cover sheet 21, the first adhesive layer 22, the sensor film layer 23 and the chip 24 are arranged in sequence from top to bottom. Among them, the chip 24 is welded and fixed on the surface of the substrate 1, the sensor film layer 23 is formed on the chip 24, and the cover sheet 21 is bonded to the sensor film layer 23 through the first adhesive layer 22. The first thermal conductive filling layer 3 is arranged on the surface of the cover sheet 21 or the inner top surface of the metal cover, and then the second adhesive layer 5 is applied on the edge of the substrate 1, and the metal cover is bonded to the substrate 1 through the second adhesive layer 5. At this time, the metal cover 4 and the cover sheet 21 are connected through the first thermal conductive filling layer 3, that is, the first thermal conductive filling layer 3 is in contact with the metal cover 4 and the cover sheet 21 respectively.

[0072] The first heat-conducting filling layer 3 is formed of a thermal interface material, which can be a thin sheet with a fixed shape or a soft material with no fixed shape, and the material can be one of gel, silicone grease, graphite, solid / liquid metal. Figure 3It is a chip test piece corresponding to the metal lid package monomer product. In the chip field, the first thermal conductive filling layer 3 can be referred to as TIM1.

[0073] The sensor film layer 23 is formed on the chip 24 by deposition, etching, electroplating, etc. The sensor film layer 23 includes a plurality of capacitive sensors 231 and a flexible dielectric layer 232. The plurality of capacitive sensors 231 are evenly arranged in an array in the flexible dielectric layer 232. Figure 5 Each capacitive sensor 231 is used to measure whether deformation such as warping or separation occurs between its coverage area and the first thermal conductive filling layer 3 .

[0074] In this embodiment, the capacitive sensor 231 is a pressure sensor. Under the action of pressure, the sensor film layer 23 is deformed, so that the capacitance of the capacitive sensor 231 changes, thereby obtaining the TIM coverage. Preferably, the capacitive sensor 231 is a variable-pole-distance capacitive sensor 231. Under the action of pressure, the distance between the upper plate and the lower plate is changed, so that the capacitance value changes. Therefore, the coverage of the area TIM1 where the capacitive sensor 231 is located is determined by the change in the capacitance value.

[0075] Specifically, when the capacitive sensor 231 covers the area and the first thermally conductive filling layer 3 and is fully pressed without warping and separation, the capacitance value measured by the capacitive sensor 231 is larger than that in the pressure-free state, and the capacitance value continues to increase with the increase of pressure, and it is judged that the area TIM1 is well covered; when the capacitive sensor 231 covers the area and the first thermally conductive filling layer 3 and warps and separates, the capacitance value measured by the capacitive sensor 231 does not change significantly (when the TIM is non-viscous) or becomes smaller (when the TIM is viscous) compared to the pressure-free state, and the capacitance value continues to decrease with the increase of the separation degree, and it is judged that the area TIM1 is poorly covered. Therefore, by counting the ratio of the number of capacitive sensors 231 with capacitance values ​​within a predetermined range to the total number of capacitive sensors 231, the coverage rate of the first thermally conductive filling layer 3 can be obtained.

[0076] In this embodiment, the upper plate 233 and the lower plate 234 of each capacitive sensor 231 are arranged in the flexible dielectric layer 232 in the thickness direction, and the upper plate 233 and the lower plate 234 are overlapped in the top view. The arrangement of the upper plate 233 and the lower plate 234 of the capacitive sensor 231 in the thickness direction overlaps allows the capacitive sensor 231 to more accurately measure the capacitance value of its coverage area. In this embodiment, the upper plate 233 and the lower plate 234 are evenly distributed in the array, which can avoid the interference caused by the uneven plate array during the pressure distribution at the first thermal conductive filling layer 3 from top to bottom, thereby improving the accuracy of the TIM coverage measurement.

[0077] Furthermore, the upper plate 233 and the lower plate 234 of each capacitive sensor 231 have the same shape, which are any shape such as rectangle, circle, etc. The upper plate 233 and the lower plate 234 have the same shape, so that their array positions overlap, thereby improving the accuracy of TIM1 coverage measurement. In addition, the upper plate 233 and the lower plate 234 can also adopt different shapes.

[0078] In this embodiment, the upper plate 233 and the lower plate 234 of the capacitive sensor 231 are respectively arranged in an array and uniformly arranged on the upper surface and the lower surface of the flexible dielectric layer 232, so that the capacitive sensor 231 can be located close to the first thermal conductive filling layer 3 to reduce the influence of the gradual uniformization of the pressure during the downward conduction. The flexible dielectric layer 232 can be replaced by a thin film insert or a silicon wafer with a high dielectric constant. In other embodiments, the upper plate 233 and the lower plate 234 of the capacitive sensor 231 can be respectively arranged in an array and uniformly arranged inside the flexible dielectric layer 232.

[0079] In addition, the upper electrode plate 233 array of the capacitive sensor 231 is arranged in the cover 21, and the lower electrode plate 234 array is arranged on the flexible dielectric layer 232; or, the upper electrode plate 233 array of the capacitive sensor 231 is arranged on the flexible dielectric layer 232, and the lower electrode plate 234 array is arranged on the chip 24; or, the upper electrode plate 233 array of the capacitive sensor 231 is arranged on the cover 21, and the lower electrode plate 234 array is arranged on the chip 24. The cover 21 and the sensor film layer 23 can be fixed by reflow soldering instead of the first adhesive layer 22; when the sensor film layer is a silicon wafer with a built-in electrode array, it can also be fixed by hybrid bonding. The above-mentioned manufacturing method of transferring the electrode array to the chip 24 or the cover 21 using a semiconductor process can improve the output capacitance and sensitivity of the sensor in some cases.

[0080] It should be noted that, in order to ensure that the contact state (such as bonding / separation) between the first thermal conductive filling layer 3 and other components (metal cover, cover sheet) is the same as that of the original product, the total thickness of the cover sheet 21, the first adhesive layer 22 and the sensor film layer 23 should be as thin as possible, and the thickness of the chip module 2 should be consistent with the thickness of the chip of the product, so that the size of other components in the chip test piece is consistent with that of other components in the product, thereby making the warping performance of the chip test piece approximately consistent with that of the original product, and enabling the position of the capacitive sensor 231 to be close to the first thermal conductive filling layer 3 to reduce the influence of the gradual uniformization of pressure during the downward conduction process. Among them, the total thickness of the cover sheet 21, the first adhesive layer 22 and the sensor film layer 23 can be between tens and hundreds of microns according to the current process design.

[0081] Furthermore, since the cover sheet 21 is used to directly contact the first heat-conducting filling layer 3, the material of the cover sheet 21 should be consistent with the material of the contact portion between the chip and the first heat-conducting filling layer 3 in the product part, so as to simulate the contact state between the chip and the first heat-conducting filling layer in the original product part. In this embodiment, the material of the cover sheet 21 is the same as the material of the contact portion between the chip and the first heat-conducting filling layer in the product part, for example, both are silicon or organic materials.

[0082] Optionally, the chip test piece further includes a bottom filling layer 8, which is formed between the chip 24 and the substrate 1 by filling and curing the bottom filling material. The bottom filling layer 8 is used to protect the solder joints between the chip 24 and the substrate 1. Considering the thermal conductivity, fluidity, curing characteristics, thermal expansion coefficient matching and other characteristics, the bottom filling layer 8 can be formed by filling and curing epoxy phenol material containing silicon dioxide particles, epoxy amine material or other insulating materials.

[0083] In this embodiment, the first adhesive layer 22 is a thermosetting film used for chip mounting in semiconductor technology. The second adhesive layer 5 can be a packaging adhesive such as a silicon-based compound containing particles, epoxy resin glue, etc., which has good bonding strength, thermal stability and other characteristics. The flexible dielectric layer 232 can be formed of an organic polymer, such as polyimide, or an inorganic material, such as a thin silicon wafer. The material of the metal cover 4 can be a metal (such as copper, aluminum or alloy), etc.

[0084] In one embodiment, the upper plate 233 and the lower plate 234 of the capacitive sensor are respectively connected to the metallized through-silicon via (TSV) filled in the chip 24 through metal wiring, and then connected to the substrate 1 through TSV, and then the substrate 1 is connected to the capacitance measuring instrument. The capacitance measuring instrument can measure the capacitance value of the capacitance sensor 231 at each position in the chip test piece. In addition, the leads of the upper plate 233 and the lower plate 234 of the capacitive sensor can be led out to the capacitance measuring instrument from different levels such as the flexible dielectric layer 232 or the chip 24 or the substrate 1, which can avoid designing and manufacturing TSV or wiring on the chip 24 or the substrate 1, reducing costs. When the TSV depth exceeds the process capability, a plurality of stacked thin chips can be used instead of the chip 24, and the stacked chips are fixed by reflow soldering or hybrid bonding.

[0085] Figure 4 is a cross-sectional view of a chip control test piece of this embodiment. Figure 3 The difference between the chip test piece is that, Figure 4 The chip control test piece in the experiment does not include the first thermal conductive filling layer 3, that is, there is a gap between the cover sheet 21 and the inner top surface of the metal cover. The purpose of setting up the chip control test piece (i.e., the control group) is to Figure 3The output data of the capacitance sensor provides a reference value (comparison), which is calculated by Figure 3 The output capacitance is relatively Figure 4 The difference between the output reference values ​​is used to infer the influence of the pressure at the first thermal conductive filling layer 3. Figure 3 In some possible embodiments, there is no need to set up a chip control test piece. Instead, it is necessary to record the capacitance value of each capacitive sensor after the sensor film layer 23 and the cover sheet 21 of the chip test piece are prepared and before the first thermal conductive filling layer 3 is applied, as a reference value for subsequent measurements.

[0086] Figure 6 : is a cross-sectional view of the metal cover chip test piece of this embodiment installed on a circuit board. Figure 3 Based on the metal cover chip test piece, Figure 6 A ball grid array (BGA) and a circuit board 6 are added. That is, the chip test piece also includes a circuit board 6, Figure 3 The substrate 1 of the metal cap chip shown is arranged on the circuit board 6, and the substrate 1 and the circuit board 6 are interconnected through BGA. It should be noted that the lower surface of the substrate 1 can also be interconnected with the circuit board 6 in the form of a contact array package (Land Grid Array, LGA) or the like. Figure 6 For the chip test piece corresponding to the metal cover package monomer product, in the chip field, the first thermal conductive filling layer 3 can be referred to as TIM1. Figure 6 The measurement of TIM1 coverage in the structure can also set up a control group, that is, Figure 4 The structure is fixed on the circuit board 6 in a similar manner. Figure 6 The output data of the capacitance sensor provides the reference value.

[0087] Figure 7 This is a cross-sectional view of the metal cover chip test piece after it is mounted on the circuit board and the heat sink is assembled. Figure 6 On the basis of Figure 7 A heat sink and a second heat-conducting filling layer 7 are added. The heat sink 9 is arranged above the metal cover 4, and the second heat-conducting filling layer 7 is arranged between the heat sink 9 and the metal cover 4. The material of the second heat-conducting filling layer 7 is consistent with the material of the first heat-conducting filling layer 3. The heat sink 9 can be fixedly connected to the circuit board 6 by fastening members such as screws. In one embodiment, the heat sink 9 is an air-cooled heat sink with fins. In other embodiments, the air-cooled heat sink can adopt other structures, or it can be a liquid-cooled heat sink. Figure 7 In the measurement of the coverage rate of the first thermal conductive filling layer 3, a control group can also be set up. Figure 6 The structure is assembled with a heat sink in a similar manner. Figure 7 The output data of the capacitance sensor provides the reference value. Figure 7 It is a corresponding chip test piece after the metal lid package monomer product is mounted on a board and a heat sink is assembled. In the chip field, the first thermal conductive filling layer 3 can be referred to as TIM1, and the second thermal conductive filling layer 7 can be referred to as TIM2.

[0088] Figure 8 This is a cross-sectional view of the bare chip chip test piece of this embodiment after it is installed on a circuit board and the heat sink is assembled. The bare chip chip test piece refers to the chip module 2 being exposed to the outside in a packaged single body state. Figure 8 and Figure 7 The difference is that the metal cover is replaced by a metal ring 10, the chip module 2 is located in the metal ring 10, the bottom surface of the metal ring 10 is connected to the substrate 1 through the second adhesive layer 5, and the heat sink 9 is directly arranged above the first thermal conductive filling layer 3. That is, the first thermal conductive filling layer 3 is used to fill the gap between the cover sheet 21 and the heat sink 9. Among them, the substrate 1 is interconnected with the circuit board 6 in the form of BGA or LGA. Figure 8 The measurement of the coverage of the first thermal conductive filling layer 3 requires recording the capacitance value of each capacitive sensor after the sensor film layer 23 and the cover sheet 21 of the chip test piece are prepared and before the first thermal conductive filling layer 3 is applied, as a reference value for subsequent measurements. Figure 8 It is a chip test piece corresponding to a bare chip packaged single product after being mounted on a board and equipped with a heat sink. In the chip field, the first thermal conductive filling layer 3 can be referred to as TIM1.5.

[0089] exist Figure 6 , Figure 7 , Figure 8 In the chip test piece shown, the leads of the upper electrode plate 233 and the lower electrode plate 234 of the capacitive sensor can be led out to the capacitance measuring instrument from different levels such as the flexible dielectric layer 232 or the chip 24 or the substrate 1 or the circuit board 6, thereby avoiding the design and manufacture of TSV or routing on the chip 24 or the substrate 1 or the circuit board 6, thereby reducing costs.

[0090] Fig. 9 The invention discloses a method for preparing a metal cover chip test piece. Fig.10 The figure is a schematic diagram of the various steps in the preparation process of the metal cover chip test piece. Fig. 9 As shown, the preparation method comprises:

[0091] Step S105 , fabricating metal routing circuits, pads and through silicon vias on the top surface of the first wafer.

[0092] First, metal wiring circuits, pads, TSVs, etc. are fabricated on the back side of the first wafer as required, so as to be interconnected with the capacitive sensors in the formed sensor film layer and / or with the substrate 1 in the subsequent process.

[0093] Step S110 , grinding the back side of the first wafer to a predetermined thickness and exposing the ends of the through silicon vias.

[0094] Step S115 , manufacturing a sensor thin film layer on the back side of the first wafer by using a semiconductor process.

[0095] The structure of the sensor film layer 23 is consistent with that in the above embodiment, and will not be described in detail. The semiconductor process includes spin coating, curing, deposition, etching, electroplating, and the like.

[0096] Step S120 , cutting the first wafer having the sensor thin film layer into dies.

[0097] Step S125 , grinding the second wafer to a predetermined thickness.

[0098] According to the current process, the second wafer is polished to a predetermined thickness, as thin as possible.

[0099] Step S130: Use the first adhesive layer to bond the die to the polished second wafer.

[0100] Step S135 , cutting the bonded dies into chip modules.

[0101] Step S140, welding and fixing the chip module on a substrate. A metal wiring circuit is made on the substrate so that the capacitive sensor and the substrate are interconnected.

[0102] Step S145 , filling the gap between the chip module and the substrate with bottom filling material and curing the bottom filling material to form a bottom filling layer.

[0103] Since the bottom filler is used to protect the solder joint, the bottom filler can be set or not. That is, this step can be set or not according to the needs.

[0104] Step S150: arranging a first thermally conductive filling layer on the upper surface of the chip module or the lower surface of the metal cover.

[0105] Step S155 , applying a second adhesive layer on the edge of the substrate to bond the metal cover to the substrate.

[0106] After the metal cover is bonded to the substrate, the metal cover contacts the first thermal conductive filling layer, and the cover sheet contacts the first thermal conductive filling layer. Thus, the metal cover chip test piece packaged in this way is completed. The structure of the chip test piece after each step of the above process is completed is as follows: Fig.10 shown.

[0107] When the metal cover chip test piece needs to be mounted on a board, the following steps can be added: the substrate is connected and arranged on the circuit board, and the substrate and the circuit board are interconnected. The substrate and the circuit board can be interconnected in a BGA form or an LGA form.

[0108] When the metal cover type chip test piece needs to be mounted on a board and a heat sink, the following steps can be added: a second heat conductive filling layer is arranged on the upper surface of the metal cover or the lower surface of the heat sink. The heat sink is arranged above the metal cover and the heat sink is locked to the circuit board. At this time, the second heat conductive filling layer is filled between the heat sink and the metal cover.

[0109] The difference between the preparation method of the bare chip test piece and the preparation method of the metal cover chip test piece is that the second adhesive layer is applied to the edge of the substrate, the metal ring is bonded to the substrate, the substrate is connected and set on the circuit board, and the substrate and the circuit board are interconnected. Then, the first thermal conductive filling layer is arranged on the upper surface of the chip module or the lower surface of the heat sink, the heat sink is directly arranged above the chip module and the heat sink is locked to the circuit board. At this time, the first thermal conductive filling layer is filled between the heat sink and the metal cover.

[0110] Meanwhile, the preparation method of the control group of the corresponding test piece is similar and will not be described in detail.

[0111] Fig.11 FIG. 1 is a flow chart of the method for measuring TIM coverage in this embodiment. Fig.11 As shown, the measurement methods include:

[0112] Step S210: Connect a capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip test piece.

[0113] The chip test piece can be in one of the following states: a metal-covered chip test piece, a metal-covered chip test piece mounted on a circuit board, a metal-covered chip test piece mounted on a circuit board and equipped with a heat sink, or a bare chip chip test piece mounted on a circuit board and equipped with a heat sink.

[0114] Step S220 , recording the capacitance value of each capacitive sensor in the chip test piece.

[0115] Each capacitive sensor has a different number, so as to analyze and obtain the TIM coverage of the corresponding position.

[0116] Step S230: Connect the capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip control test piece.

[0117] The chip control test piece is set accordingly according to the different chip test pieces to improve the reference accuracy.

[0118] Step S240: Record the capacitance value of each capacitive sensor in the chip control test piece.

[0119] Step S250: Calculate the difference in capacitance between the capacitance sensor at the same position in the chip test piece and the control test piece.

[0120] Step S260: When the difference is within a predetermined range, it is determined that the first thermally conductive filling layer above the capacitive sensor is in a good coverage state.

[0121] When the difference in capacitance value between the capacitive sensor at the same position in the chip test piece and the control test piece is within a predetermined range, it indicates that the position is in a good coverage state; when the difference in capacitance value between the capacitive sensor at the same position in the chip test piece and the control test piece exceeds the predetermined range, it indicates that the position is in a gap, separation, etc. The predetermined range can be determined by the baseline value of the control group, or can be calibrated by other measurement methods of the TIM coverage of the package monomer, such as acoustic scanning method, cutting measurement method, or can be derived theoretically.

[0122] Step S270: Calculate the ratio of the number of capacitance sensors whose differences are within a predetermined range to the total number of capacitance sensors, where the ratio represents the coverage of the first thermally conductive filling layer.

[0123] This embodiment can measure TIM coverage by setting up a chip test piece to replace the product piece, so as to achieve in-situ measurement and better deal with the problem of measuring TIM coverage inside or on the surface of the chip package. By using a built-in pressure sensor on the chip test piece, the pressure distribution at the TIM can be measured in four states: metal cover chip test piece, upper plate, upper plate and heat sink assembly, and bare chip chip test piece upper plate and heat sink assembly. The contact state of the original product piece is retained to the maximum extent, thereby avoiding the introduction of errors caused by different contact states, and the built-in pressure sensor has stronger adaptability and a finer resolution of pressure distribution measurement.

[0124] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip test piece, characterized in that: The chip test piece comprises: base(1); A chip module (2), comprising a cover sheet (21), a first adhesive layer (22), a sensor film layer (23) and a chip (24) arranged in sequence from top to bottom, the chip (24) being welded and fixed on the surface of the substrate (1), the sensor film layer (23) being integrated on the chip (24), and the cover sheet (21) being bonded to the sensor film layer (23) via the first adhesive layer (22); A first heat-conducting filling layer (3) is arranged on the surface of the cover sheet (21); The sensor film layer (23) comprises a plurality of capacitive sensors (231) and a flexible dielectric layer (232); the plurality of capacitive sensors (231) are evenly arranged in an array in the flexible dielectric layer (232); and the proportion of the capacitive sensors (231) having capacitance values ​​within a predetermined range among the plurality of capacitive sensors (231) represents the coverage of the first thermally conductive filling layer (3).

2. The chip test piece according to claim 1, characterized in that: The capacitive sensor (231) is a variable-pole-distance type capacitive sensor (231), and the upper electrode plate (233) and the lower electrode plate (234) of each capacitive sensor (231) are arranged up and down and their positions overlap.

3. The chip test piece according to claim 2, characterized in that: The upper electrode plate (233) and the lower electrode plate (234) of each capacitive sensor (231) have the same shape, and are both rectangular or circular.

4. The chip test piece according to claim 2, characterized in that: The upper plates (233) and the lower plates (234) of the plurality of capacitive sensors (231) are respectively and evenly arranged in an array on the upper surface and the lower surface of the flexible dielectric layer (232); or, The upper plates (233) and the lower plates (234) of the plurality of capacitive sensors (231) are respectively and evenly arranged in an array inside the flexible dielectric layer (232); or, An array of upper plates (233) of the plurality of capacitive sensors (231) is arranged on the cover sheet (21), and an array of lower plates (234) of the plurality of capacitive sensors (231) is arranged on the flexible dielectric layer (232); or, An array of upper plates (233) of the plurality of capacitive sensors (231) is arranged on the flexible dielectric layer (232), and an array of lower plates (234) of the plurality of capacitive sensors (231) is arranged on the chip (24); or, An array of upper plates (233) of the plurality of capacitive sensors (231) is arranged on the cover sheet (21), and an array of lower plates (234) of the plurality of capacitive sensors (231) is arranged on the chip (24).

5. The chip test piece according to claim 1, characterized in that: The chip test piece further comprises a metal cover (4), the inner top surface of the metal cover (4) being in contact with and connected to the first heat-conducting filling layer (3), and the bottom surface of the metal cover (4) being sealed and connected to the substrate (1) via a second adhesive layer (5).

6. The chip test piece according to claim 5, characterized in that: The chip test piece further comprises a circuit board (6), the substrate (1) is arranged on the circuit board (6), and the substrate (1) and the circuit board (6) are interconnected.

7. The chip test piece according to claim 6, characterized in that: The chip test piece also includes a heat sink (9) arranged above the metal cover (4), a second heat-conducting filling layer (7) is arranged between the heat sink (9) and the metal cover (4), and the heat sink (9) is connected to the circuit board (6) via a locking member.

8. The chip test piece according to claim 1, characterized in that: The chip test piece further comprises a heat sink (9), wherein the heat sink (9) is arranged above the first heat-conducting filling layer (3); The chip test piece further comprises a metal ring (10) and a circuit board (6); the bottom surface of the metal ring (10) is sealedly connected to the substrate (1) via a second adhesive layer (5); the chip module (2) is located inside the metal ring (10); the substrate (1) is arranged on the circuit board (6); and the substrate (1) and the circuit board (6) are interconnected.

9. The chip test piece according to claim 1, characterized in that: The chip test piece further comprises a bottom filling layer (8) filled between the chip (24) and the substrate (1).

10. The chip test piece according to claim 1, characterized in that: The material of the first heat-conducting filling layer (3) is one of gel, silicone grease, graphite, and solid / liquid metal, and the material of the cover sheet (21) is silicon or an organic material.

11. A method for preparing a chip test piece, characterized in that: The preparation method comprises: Fabricate metal routing circuits, pads, and through-silicon vias on the top surface of the first wafer; Grinding the back side of the first wafer to a predetermined thickness and exposing the end of the through silicon via; Manufacturing the sensor film layer on the back side of the first wafer by semiconductor process; cutting the first wafer having the sensor thin film layer into dies; grinding the second wafer to a predetermined thickness; bonding the die to the polished second wafer using the first bonding layer; Cutting the bonded dies into chip modules; The chip module is welded and fixed on a substrate, on which a metal wiring circuit is made; Filling the bottom filling material into the gap between the chip module and the substrate and curing it to form a bottom filling layer; Arranging a first thermally conductive filling layer on the upper surface of the chip module or the lower surface of the metal cover; A second adhesive layer is applied on the edge of the substrate, and the metal cover is bonded to the substrate. The metal cover is connected to the chip module through the first heat-conducting filling layer.

12. The preparation method according to claim 11, characterized in that: The preparation method further comprises: A substrate is disposed on a circuit board, the substrate being interconnected with the circuit board.

13. The preparation method according to claim 12, characterized in that: The preparation method further comprises: Arranging a second thermally conductive filling layer on the upper surface of the metal cover or the lower surface of the heat sink; The heat sink is arranged above the metal cover, and the heat sink is locked with the circuit board.

14. A method for measuring the coverage of a thermal conductive filling layer, characterized in that: The measuring method comprises: Connecting a capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip test piece; Recording the capacitance value of each capacitive sensor in the chip test piece; Connecting a capacitance measuring instrument to the upper electrode and the lower electrode of each capacitance sensor in the chip control test piece; Recording the capacitance value of each capacitive sensor in the chip control test piece; Calculating the difference in capacitance values ​​of the capacitive sensors at the same position in the chip test piece and the control test piece; When the difference is within a predetermined range, it is determined that the first thermally conductive filling layer above the capacitive sensor is in a good coverage state; The ratio of the number of capacitance sensors whose difference values ​​are within a predetermined range to the total number of capacitance sensors is calculated, and the ratio represents the coverage rate of the first thermally conductive filling layer.

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