On-chip network construction method, device, equipment and readable storage medium

Abstract

The embodiment of the present invention provides a method, device, equipment and readable storage medium for constructing a network on chip, the method comprising: determining the component type of the component to be connected according to the number of levels of the preset routing components included in the component to be connected; the number of levels of the preset routing components corresponding to the first type is greater than the number of levels of the preset routing components corresponding to the second type; determining a first component belonging to the first type in the component to be connected, connecting the first component to the downstream port of the preset root routing component; in the case where the first component is connected, connecting the remaining downstream port in the root routing component to the upstream port of the tree routing component, so that the downstream port of the tree routing component is in a connectable state; determining a second component belonging to the second type in the component to be connected, connecting the second component to the downstream port of the tree routing component, so as to construct a tree-like network on chip. The present invention can improve the resource utilization of the network on chip.

Description

Technical Field

[0001] The present invention relates to the field of network-on-chip technology, and in particular to a method, device, electronic device and computer-readable storage medium for constructing a network-on-chip. Background Art

[0002] As the size and complexity of System on Chip (SOC) continue to increase, the data transmission rate of bus-type data exchange is relatively low, and data exchange between components within SOC based on Network-on-Chip (NoC) has become common.

[0003] In the related art, the structure of the on-chip network is fixed, and the data flow, operation sequence and logical relationship between various parts (such as processor core and cache) are also fixed.

[0004] However, in the related art, since a fixed-structured on-chip network is constructed, the fixed on-chip network structure may be inconsistent with actual needs, resulting in low resource utilization of the on-chip network. Summary of the invention

[0005] The embodiments of the present invention provide a method, device, electronic device and readable storage medium for constructing a network on a chip, which can solve the problem in the related art that the applicability of an instruction set cannot be determined.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a method for constructing an on-chip network, the method comprising:

[0007] Determine the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type;

[0008] Determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component;

[0009] In the case where the first component is connected, connecting the remaining downstream port in the root routing component to the upstream port of the tree-shaped routing component so that the downstream port of the tree-shaped routing component is in a connectable state;

[0010] A second component belonging to the second type is determined among the components to be connected, and the second component is connected to a downstream port of the tree-shaped routing component to construct a tree-shaped network on chip.

[0011] On the other hand, an embodiment of the present invention discloses a device for constructing a network on chip, the device comprising:

[0012] A component type module, used to determine the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type;

[0013] A first connecting module, configured to determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component;

[0014] A tree-shaped routing module, used for connecting the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component when the first component is connected, so that the downstream ports of the tree-shaped routing component are in a connectable state;

[0015] The second connection module is used to determine a second component belonging to the second type among the components to be connected, and connect the second component to the downstream port of the tree-shaped routing component to build a tree-shaped on-chip network.

[0016] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned on-chip network construction method.

[0017] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned on-chip network construction method.

[0018] The embodiment of the present invention includes the following advantages: the component type of the component to be connected is determined by the number of levels of the preset routing component, and for the first component of the first type in the components to be connected, the first component is connected to the downstream port of the root routing component, and when the first component is connected, the upstream port of the tree-like routing component is connected to the downstream port of the root routing component, so that the downstream port of the tree-like routing component is in a connectable state, and for the second component of the second type in the components to be connected, the second component is connected to the downstream port of the tree-like routing component, thereby constructing a tree-like on-chip network. The internal preset routing component with a larger number of levels is directly connected to the root routing component, and the internal preset routing component with a smaller number of levels is indirectly connected to the root routing component through the tree-like routing component. Components of different component types can be connected to routing components of different levels respectively, and the ports of routing components of different levels are fully utilized. Through the classification of the components to be connected and the grading of the routing components, a network on chip that meets the component connection requirements can be flexibly constructed, thereby improving the resource utilization of the network on chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 is a flowchart of the steps of a method for constructing a network on chip according to the present invention;

[0021] Figure 2 is a schematic diagram of a network-on-chip architecture of the present invention;

[0022] Figure 3 is a flowchart of another method for constructing a network on a chip according to the present invention;

[0023] Figure 4 is a schematic diagram of tree-like routing component connections of the present invention;

[0024] Figure 5 is a schematic diagram of the connection of the extended access components of the present invention;

[0025] Figure 6 is a schematic diagram of the addressing process of the present invention;

[0026] Figure 7 is a structural block diagram of the on-chip network construction device of the present invention;

[0027] Figure 8 It is a structural block diagram of an electronic device for constructing an on-chip network according to the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0030] Method Embodiment

[0031] Reference Figure 1 , shows a flowchart of a method for constructing a network on chip according to an embodiment of the present invention, the method may specifically include the following steps:

[0032] Step 101, determining the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type.

[0033] In the embodiment of the present invention, the components to be connected may include a preset routing component, and one or more of a processor core, a core cluster, a cache, a snoop filter, and other components. The specific configurations of different components to be connected may be different.

[0034] The component type of the component to be connected may be determined according to the number of levels of the preset routing components included therein, and the preset routing component may refer to a tree routing component (TRT, Tree Router). The number of levels of the preset routing component may represent the connection status of the preset routing components inside the component to be connected.

[0035] For example, if there is only one preset routing component inside the component to be connected and there is no additional connected preset routing component, the number of levels is 1. If there are two preset routing components A and B inside the component to be connected and B is connected to A, the number of levels is 2. Similarly, the different numbers of levels of preset routing components inside different components to be connected can be determined.

[0036] The components to be connected can include home nodes (HN), request nodes (RN), and further subdivided into fully consistent request nodes (RNF), I / O consistent request nodes (RNI), HND with distributed virtual memory support, fully consistent home nodes (HNF), and others. The home node can manage and store data within a specific address range and process requests from other nodes.

[0037] Among the components to be connected listed above, the number of levels of preset routing components included in HND can be 2, which can be used as the first type; the number of levels of preset routing components included in RHF, HNF, and RNI can be 1, which can be used as the second type. It can be understood that the component type can include more, such as the third type and the fourth type, and the number of levels of preset routing components corresponding to more component types is also different, which is not specifically limited here.

[0038] Components to be connected of different component types can be connected to routing components of different levels. Routing components of different levels can be connected to each other, for example, a tree-like routing component is connected to a root routing component.

[0039] Among them, the routing component of the on-chip network is used to select a suitable path for the transmission of data from the source node to the destination node in the on-chip network. When the data reaches the routing component, the routing component directs the data packet to the next appropriate node or link based on the address information or other relevant identifiers in the data, thereby realizing communication between different components in the on-chip network.

[0040] Step 102: determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component.

[0041] In the embodiment of the present invention, the relevant content of determining the first component of the first type in the components to be connected is not repeated. The number of root routing components can be one, the downstream ports of the root routing component can be at least two or more, and the upstream port of the root routing component can be connected to the interconnect network routing component (Interconnect Router) of the on-chip network.

[0042] The first components of the first type may be connected to different downstream ports in the root routing component respectively, that is, different first components are connected to their respective corresponding downstream ports of the root routing component.

[0043] Step 103: When the first component is connected, connect the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component, so that the downstream ports of the tree-shaped routing component are in a connectable state.

[0044] In the embodiment of the present invention, the second type of second component may be connected after all first components have been connected, that is, each first component has been connected to the downstream port of the root routing component.

[0045] For the second component of the second type, the upstream port of the tree-shaped routing component may be first connected to the downstream port of the root routing component, so that the downstream port of the tree-shaped routing component is in a connectable state or a valid state.

[0046] It can be understood that the upstream port of the tree-like routing component is connected to the downstream port of the root routing component, which is actually an expansion of the connectable ports, based on which a tree-like structure of the on-chip network can be formed. Among them, since the first component of the first type is also connected to the downstream port of the root routing component, the more ports the first component occupies, the fewer remaining downstream ports in the root routing component that can be used to connect to the tree-like routing component.

[0047] Step 104: determine a second component belonging to the second type among the components to be connected, and connect the second component to the downstream port of the tree-shaped routing component to construct a tree-shaped network on chip.

[0048] In the embodiment of the present invention, similarly, the number of levels of the preset routing components in the second component of the second type in the components to be connected is 1. For example, the second type may include RNF, HNF, and RNI, which are not specifically limited here.

[0049] The second components of the second type are respectively connected to different downstream ports in the tree-shaped routing component, and different second components and different downstream ports in the tree-shaped routing component may correspond one to one.

[0050] The first component is directly connected to the root routing component, and the second component is connected to the tree routing component, thereby finally constructing a tree-like on-chip network.

[0051] Figure 2 is a schematic diagram of a network-on-chip architecture provided by an embodiment of the present invention; Figure 2 It represents the top level of routing components in the on-chip network (MXP, Main cross point), Figure 2The interconnection network routing component 201 is connected to the intermediate component 202, and is connected to the root routing component 203 through the intermediate component 202. The root routing component 203 may have 4 downstream ports. The first component 204 may be connected to port 0 of the root routing component 203 through the intermediate component 205.

[0052] For the second type, tree routing component 206 is connected to port 1 of root routing component 203 , second component 207 is connected to port 0 of tree routing component 206 through intermediate component 208 , and second component 209 is connected to port 1 of tree routing component 206 through intermediate component 210 .

[0053] Understandably, Figure 2 The first component, the second component, the tree-shaped routing component and the number of each port are only for illustration and can be adjusted according to actual needs.

[0054] In summary, the embodiment of the present invention is implemented to determine the component type of the component to be connected by the number of levels of the preset routing component. For the first component of the first type in the component to be connected, the first component is connected to the downstream port of the root routing component. When the first component is connected, the upstream port of the tree-like routing component is connected to the downstream port of the root routing component, so that the downstream port of the tree-like routing component is in a connectable state. For the second component of the second type in the component to be connected, the second component is connected to the downstream port of the tree-like routing component, thereby constructing a tree-like on-chip network. The internal preset routing component with a larger number of levels is directly connected to the root routing component, and the internal preset routing component with a smaller number of levels is indirectly connected to the root routing component through the tree-like routing component. Components of different component types can be connected to routing components of different levels respectively, and the ports of routing components of different levels are fully utilized. Through the classification of the components to be connected and the grading of the routing components, the on-chip network structure that meets the component connection requirements can be flexibly constructed, thereby improving the resource utilization of the on-chip network.

[0055] Figure 3 A flowchart of another method for constructing a network on chip according to the present invention is shown. The method may specifically include the following steps:

[0056] Step 301, determining the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type;

[0057] Step 302, determining a first component belonging to the first type among the components to be connected, and connecting the first component to a downstream port of a preset root routing component;

[0058] Step 303: When the first component is connected, connect the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component, so that the downstream ports of the tree-shaped routing component are in a connectable state;

[0059] Step 304: determine a second component belonging to the second type among the components to be connected, and connect the second component to the downstream port of the tree-shaped routing component to construct a tree-shaped network on chip.

[0060] The contents of steps 301-304 can refer to the above Figure 1 The embodiments are not described in detail here.

[0061] Optionally, the step 303 of connecting the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component includes:

[0062] Sub-step 3031, determining a first quantity of the second components and a second quantity of downstream ports of the tree-shaped routing component;

[0063] Sub-step 3032: determining a third number of tree-shaped routing components according to the first number and the second number; the first number and the third number are positively correlated; the second number and the third number are negatively correlated;

[0064] Sub-step 3033, connecting the third number of tree-like routing components to the downstream port of the root routing component.

[0065] In the embodiment of the present invention, since the number of downstream ports of the tree-shaped routing component is limited, it is necessary to determine the first number of the second components and the second number of the downstream ports of the tree-shaped routing component respectively. The first number of the second components represents the connection requirement of the second components, and the second number of the downstream ports of the tree-shaped routing component represents the connection capacity of each tree-shaped routing component.

[0066] When the first number is larger and the second number of downstream ports of each tree-like routing component is fixed, more tree-like routing components are needed. When the second number is larger and the first number is fixed, fewer tree-like routing components are needed. In the case where a second component is connected to a downstream port of a tree-like routing component, the third number of required tree-like routing components can be determined based on the first number and the second number.

[0067] The third number of tree-shaped routing components are connected to the downstream ports of the root routing component, and then the first number of second components can be connected to the on-chip network based on the third number of tree-shaped routing components.

[0068] In the implementation of the embodiment of the present invention, by determining the first number of second components and the second number of downstream ports of the tree-like routing component, the third number of tree-like routing components is determined according to the first number and the second number, and the third number of tree-like routing components are connected to the downstream ports of the root routing component. The number of required tree-like routing components can be determined according to the number of second components, and the access requirements of different numbers of second components can be met, thereby improving the flexibility of on-chip network construction and improving the resource utilization of the on-chip network.

[0069] Optionally, the step of connecting the third number of tree-shaped routing components to downstream ports of the root routing component includes:

[0070] Determining a preset routing level of the tree-like network on chip; the preset routing level represents a maximum stacking level of tree-like routing components to which each downstream port in the root routing component can be connected;

[0071] Stacking and connecting the upstream ports of the third number of tree-shaped routing components to the same downstream port of the root routing component;

[0072] When the downstream port has reached the preset routing level and the third number of tree-like routing components are still not fully connected, continue to stack the tree-like routing components with the next downstream port of the root routing component until the third number of tree-like routing components are all connected.

[0073] In the embodiment of the present invention, the routing level of the tree-like network on chip may have certain restrictions, namely, the preset routing level. For example, the preset routing level may be two. The first component may include two layers of preset routing components. Then, when the root routing component is connected to the first component, the preset routing level has been reached. If the first component is connected to the tree-like routing component, since the tree-like routing component needs to be connected to the root routing component first, the third layer is reached, which exceeds the limit of the preset routing level. The specific preset routing level is not limited here.

[0074] In the case of preset routing level restrictions, it may not be possible to directly or indirectly connect all the third number of tree-like routing components to the same downstream port of the root routing component. For example, the preset routing level is two, and one tree-like routing component can be connected to port A of the root routing component. Since the preset routing level is two, at most one level of tree-like routing components can be connected to the tree-like routing component; if the preset routing level is larger, multiple layers of tree-like routing components can be stacked and connected. If the preset routing level is smaller, such as one, after port A of the root routing component is connected to one layer of tree-like routing components, it cannot continue to connect to the next layer of tree-like routing components.

[0075] If the downstream port of the current root routing component has been fully connected to the tree-shaped routing components at the maximum stacking level, the connection is continued for the next downstream port until the third number of tree-shaped routing components have been connected.

[0076] Figure 4 is a schematic diagram of tree-like routing component connections provided by an embodiment of the present invention; Figure 4 Port 0 of the root routing component 401 is connected to the tree routing component 402, and the four downstream ports of the tree routing component 402 can be connected to four second components (only one is shown in the figure). When the preset routing level is one, the other port of the root routing component 401, i.e., port 1, continues to be connected to the tree routing component 403, and the four downstream ports of the tree routing component 403 can be connected to four second components (only one is shown in the figure).

[0077] Understandably, Figure 4 The middle root routing component can also be connected to the interconnection network routing component, the intermediate component and other components. In order to highlight the key points, the repeated content is not shown. For details, please refer to Figure 2 .

[0078] By implementing the embodiments of the present invention, the connection process of the tree-like routing components is limited based on the preset routing hierarchy, which can prevent the on-chip network from becoming more complicated, thereby reducing delays and resource consumption, and improving the communication efficiency and resource utilization of the constructed on-chip network.

[0079] Optionally, the component to be connected includes a third component; and the method further includes:

[0080] In the case where there is a processor core to be connected, connecting the downstream port of the root routing component to the upstream port of the extended access component so that the downstream port of the extended access component is in a connectable state;

[0081] The downstream port of the extended access component is connected to the third component; the third component is used to connect the processor core to the tree-like on-chip network.

[0082] In the embodiment of the present invention, the on-chip network can also be connected to processor cores of more different manufacturers. The processor core can be connected to the on-chip network through a third component. The third component can be an external sampler (external sampler) or other components for accessing the processor core.

[0083] In order to connect the third component to further access the processor core, the idle downstream port in the root routing component can be connected to the upstream port of the extended access component. The extended access component can also be called a control component or a miscellaneous component (misc). The extended access component can access a variety of different types of components, such as a configuration component (CFG, Configuration), a performance monitor (PMU, Performance Monitor), the third component for accessing the processor core, and other components, which are not specifically limited here.

[0084] After the idle downstream port of the root routing component is connected to the upstream port of the extended access component, the downstream port of the extended access component is in a connectable state, and a third component can be connected to the downstream port of the extended access component, and more processor cores can be connected to the tree-like on-chip network through the third component.

[0085] Figure 5 is a schematic diagram of the connection of the extended access component provided by an embodiment of the present invention; Figure 5 In the example, the upstream port of the extended access component 501 is connected to the downstream port of the root routing component, and the downstream port of the extended access component 501 can be connected to the configuration component, the performance monitor and at least one third component 502 respectively.

[0086] When implementing an embodiment of the present invention, when there are processor cores to be connected, the downstream port of the root routing component is connected to the upstream port of the extended access component, and the third component is connected to the downstream port of the extended access component. Further, more processor cores can be connected to the tree-like on-chip network through the extended access component and the third component, thereby improving the flexibility of on-chip network construction.

[0087] Optionally, the step of connecting the downstream port of the extended access component to the third component includes:

[0088] Determine a fourth number of the processor cores and a fifth number of downstream ports of the extended access component; the processor cores to be accessed correspond one-to-one to the third component;

[0089] When the fourth number is less than or equal to the fifth number, connecting the fourth number of third components to different downstream ports of the extended access component respectively;

[0090] When the fourth number is greater than the fifth number, the upstream port of the tree-like routing component is connected to the downstream port of the extended access component, and the fourth number of third components are respectively connected to different downstream ports of the tree-like routing component.

[0091] In the embodiment of the present invention, the number of processor cores that need to be additionally connected is indefinite. When these processor cores need to be connected, the number of processor cores, i.e., the fourth number, can be determined first, and the fifth number of downstream ports of the extended access component needs to be determined. Each processor core can access the on-chip network through a different third component, so the number of third components can be determined based on the fourth number of processor cores. For example, when the third components correspond to the processor cores one by one, the number of third components is the fourth number.

[0092] When the fourth number of processor cores is less than or equal to the fifth number, it means that the number of downstream ports of the current extended access component can meet the access requirements of these processor cores. Therefore, the fourth number of third components can be directly connected to the fifth number of different downstream ports of the extended access component.

[0093] When the fourth number of processor cores is greater than the fifth number, it means that the number of downstream ports of the current extended access component cannot meet the access requirements of these processor cores, and the fourth number of third components cannot be directly connected to different downstream ports of the extended access component. Therefore, the upstream port of another tree-shaped routing component can be connected to the downstream port of the extended access component.

[0094] It is understandable that when the fourth number of processor cores is greater than the fifth number, the other connected tree-like routing components may be functionally the same as the tree-like routing component used to connect the second component in step 103 above, but are not the same tree-like routing component.

[0095] Among them, when the fourth number of processor cores is greater than the fifth number, determining the required number of tree-like routing components and the connection process of the tree-like routing components may also be similar to the above-mentioned "stacking connection for different downstream ports of the root routing component based on the preset routing hierarchy" related process, and will not be repeated here.

[0096] The problem of insufficient number of downstream ports of the current extended access component can be solved by using another tree-like routing component. The fourth number of third components can be connected to different downstream ports of the tree-like routing component respectively, thereby completing the access of the fourth number of processor cores.

[0097] By implementing the embodiments of the present invention, it is possible to determine whether to directly access the extended access component or to perform further port expansion through the tree-like routing component according to the specific number of processor cores to adapt to the access requirements of the processor cores, thereby improving the flexibility of on-chip network construction and improving the resource utilization of the on-chip network.

[0098] Optionally, the method further includes:

[0099] Determining communication characteristic parameters of each processor core and a third component corresponding to each processor core;

[0100] According to the communication characteristic parameters of each processor core, the communication configuration of the third component corresponding to each processor core is adjusted to establish communication between each processor core and the corresponding third component.

[0101] In the embodiment of the present invention, since the processor cores to be connected may be from different manufacturers, different processor cores have differences, for example, differences in design, function, interface, etc.

[0102] In order to access and implement communication of processor cores in the on-chip network through the third component, the communication characteristic parameters of each processor core can be determined. Since different processor cores can access the on-chip network through different third components, the third component corresponding to each processor core also needs to be determined.

[0103] The communication characteristic parameters may be parameters such as connection protocol, data transmission rate, signal format, etc. Based on the configurable characteristics of the third component, such as External sam, the third component is allowed to adjust according to these different communication characteristic parameters. For example, the connection protocol, data transmission rate, signal format, etc. parameters may be adjusted so that different third components can establish connections with cores of different manufacturers and perform data exchange.

[0104] By implementing an embodiment of the present invention, by determining the communication characteristic parameters of each processor core and the third component corresponding to each processor core; adjusting the communication configuration of the third component corresponding to each processor core according to the communication characteristic parameters of each processor core, so that communication is established between each processor core and the corresponding third component, the compatibility and scalability of the on-chip network can be improved, making it more convenient and efficient to build a complex chip system containing cores from multiple sources, and ultimately improving the flexibility of the on-chip network.

[0105] In addition, the upstream port of the tree-like routing component is connected to the downstream port of the root routing component. Since the first component of the first type is also connected to the downstream port of the root routing component, the more first components there are, the fewer downstream ports in the root routing component that can be used for expansion of the tree-like routing component. In the case where the number of first components is greater than or equal to the number of downstream ports of the root routing component, if each first component is continuously connected to the downstream port of the root routing component, the second component, the third component or other components will be unable to access.

[0106] Therefore, in the process of connecting the first component to different downstream ports of the root routing component one by one, the downstream port (root routing component) to which the first component is not currently connected can be used as the target port, and the number of the target ports can be determined in real time.

[0107] When the number of target ports that have not yet been connected to the first component is a specific number, such as 1, 2 or others, the target ports can be connected to the upstream port of the tree routing component so that the second component of the second type can also be added to the construction of the on-chip network. The target ports can also be connected to the extended access component so that the CFG component, PMU component, third component, etc. can be connected, thereby improving the flexibility of the on-chip network construction.

[0108] Optionally, the method further includes:

[0109] Step A1, determining a topological structure of a tree-like network-on-chip composed of a target component set, the root routing component and the tree-like routing component; the target component set includes the first component and the second component;

[0110] Step A2: determining identification information of each target component according to the position of each target component in the topological structure; the identification information is used to implement addressing operations for the target component.

[0111] In an embodiment of the present invention, the target component may include a first component and a second component. The number of first components and the number of second components are not limited. After the on-chip network is constructed based on the target component set, the root routing component and the tree routing component, the topological structure of the tree-like on-chip network can be determined.

[0112] Based on the position of each target component in the topological structure, identification information of each target component is determined respectively, and each component may correspond to a target identifier (DESTID).

[0113] DESTID can be 16 bits and can be split into two parts: high 8 bits and low 8 bits. The high 8 bits can store xid (the identifier of the x direction in the tree-like on-chip network) and yid (the identifier of the y direction in the tree-like on-chip network).

[0114] The lower 8 bits may contain the device identification information (device id). Among the lower 8 bits, only the lower 6 bits may be used for addressing operations, that is, these lower 6 bits of information can be used for positioning, communicating, and other operations on the device in the on-chip network. Due to network structure design, address allocation rules or compatibility and other reasons, the upper 2 bits of the lower 8 bits may be set to 0 by default, and these 2 bits do not participate in the device addressing operation. If necessary, these 2 bits can also be used to store other information.

[0115] According to the position of the target component in the topology structure, the lower 6 bits of the above lower 8 bits may be determined.

[0116] Figure 6is a schematic diagram of an addressing process provided by an embodiment of the present invention; the lower 6 bits of the lower 8 bits of DESTID may be 000110;

[0117] 1. According to the 10 in the first and second positions, the tree routing component 601 to which the port 2 is connected can be determined in the root routing component;

[0118] 2. According to the 01 in the 3rd and 4th bits, the next level tree-shaped routing component 602 to which port 2 is connected can be determined in the tree-shaped routing component;

[0119] 3. According to the 00 in the 5th and 6th bits, the target component 604 to which port 0 is connected can be determined in the next-level tree-shaped routing component 603.

[0120] In the SoC of the Noc engine, the physical location and the SoC address space are completely bound, and the 14 bits in the above DESTID are directly equal to bits 14-27 of the SoC address space. In theory, the maximum number of components that can be connected to a single port (PORT) of the root routing component is 16, and the maximum addressing space of the registers of the configuration components on a single PORT is 8 kilobytes (KB).

[0121] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0122] Device Embodiment

[0123] Figure 7 is a structural block diagram of a network-on-chip construction device of the present invention, wherein the device 70 comprises:

[0124] The component type module 701 is used to determine the component type of the component to be connected according to the number of levels of the preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of the preset routing components corresponding to the first type is greater than the number of levels of the preset routing components corresponding to the second type;

[0125] A first connecting module 702, configured to determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component;

[0126] The tree-shaped routing module 703 is used to connect the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component when the first component is connected, so that the downstream ports of the tree-shaped routing component are in a connectable state;

[0127] The second connecting module 704 is used to determine a second component belonging to the second type among the components to be connected, and connect the second component to the downstream port of the tree-shaped routing component to construct a tree-shaped network on chip.

[0128] Optionally, the first connection module includes:

[0129] A quantity acquisition submodule, used to determine a first quantity of the second components and a second quantity of downstream ports of the tree-shaped routing component;

[0130] a quantity determination submodule, configured to determine a third quantity of tree-shaped routing components according to the first quantity and the second quantity; the first quantity and the third quantity are positively correlated; and the second quantity and the third quantity are negatively correlated;

[0131] The tree connection submodule is used to connect the third number of tree-like routing components to the downstream port of the root routing component.

[0132] Optional, tree-connected submodules, including:

[0133] A stacking level unit, used to determine a preset routing level of the tree-like network on chip; the preset routing level represents a maximum stacking level of the tree-like routing components to which each downstream port in the root routing component can be connected;

[0134] A tree stacking unit, used to stack and connect the upstream ports of the third number of tree routing components with the same downstream port of the root routing component;

[0135] The stacking cycle unit is used to continue to stack the tree-like routing component with the next downstream port of the root routing component when the downstream port has reached the preset routing level and the third number of tree-like routing components are still not fully connected, until the third number of tree-like routing components are all connected.

[0136] Optionally, the component to be connected includes a third component; and the device further includes:

[0137] A core access module, used to connect the downstream port of the root routing component to the upstream port of the extended access component when there is a processor core to be accessed, so that the downstream port of the extended access component is in a connectable state;

[0138] The extended access module is used to connect the downstream port of the extended access component with the third component; the third component is used to connect the processor core to the tree-like on-chip network.

[0139] Optional, extended access modules, including:

[0140] A quantity collection submodule, used to determine a fourth quantity of the processor cores and a fifth quantity of downstream ports of the extended access component; the processor cores to be accessed correspond one-to-one to the third component;

[0141] A port sufficiency submodule, used for connecting the fourth number of third components to different downstream ports of the extended access component respectively when the fourth number is less than or equal to the fifth number;

[0142] The port extension submodule is used to connect the upstream port of the tree-like routing component with the downstream port of the extended access component when the fourth number is greater than the fifth number, and to connect the third components of the fourth number to different downstream ports of the tree-like routing component respectively.

[0143] Optionally, the device further comprises:

[0144] A core feature module, used to determine the communication feature parameters of each processor core and the third component corresponding to each processor core;

[0145] The component configuration module is used to adjust the communication configuration of the third component corresponding to each processor core according to the communication characteristic parameters of each processor core, so as to establish communication between each processor core and the corresponding third component.

[0146] Optionally, the device further comprises:

[0147] A topology structure module, used to determine a topology structure of a tree-like network-on-chip composed of a target component set, the root routing component and the tree-like routing component; the target component set includes the first component and the second component;

[0148] The identification information module is used to determine the identification information of each target component according to the position of each target component in the topological structure; the identification information is used to implement the addressing operation for the target component.

[0149] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0151] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0152] Reference Figure 8 , is a structural block diagram of an electronic device for building an on-chip network provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the on-chip network construction method of the aforementioned embodiment.

[0153] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor.

[0154] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, and a control bus. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0155] The memory can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be an EEPROM (Electrically ErasableProgrammable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, and an optical data storage device.

[0156] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 2 The on-chip network construction method shown.

[0157] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0158] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (which may include disk storage, CD-ROM, optical storage) containing computer-usable program code.

[0159] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0160] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0161] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 Functional steps of one or more boxes.

[0162] Although the preferred embodiments of the present invention are described, those skilled in the art will recognize the basic creative concept and may make other changes and modifications to these embodiments. The appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0163] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0164] The above is a detailed introduction to a network-on-chip construction method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for constructing a network on chip, characterized in that: The method comprises: Determine the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type; Determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component; In the case where the first component is connected, connecting the remaining downstream port in the root routing component to the upstream port of the tree-shaped routing component so that the downstream port of the tree-shaped routing component is in a connectable state; A second component belonging to the second type is determined among the components to be connected, and the second component is connected to a downstream port of the tree-shaped routing component to construct a tree-shaped network on chip.

2. The method according to claim 1, characterized in that The step of connecting the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component comprises: determining a first number of the second components and a second number of downstream ports of the tree routing component; Determine a third number of tree-like routing components according to the first number and the second number; there is a positive correlation between the first number and the third number; there is a negative correlation between the second number and the third number; The third number of tree-like routing components are connected to the downstream ports of the root routing component.

3. The method according to claim 2, characterized in that The step of connecting the third number of tree-shaped routing components to the downstream ports of the root routing component comprises: Determining a preset routing level of the tree-like network on chip; the preset routing level represents a maximum stacking level of tree-like routing components to which each downstream port in the root routing component can be connected; Stacking and connecting the upstream ports of the third number of tree-shaped routing components to the same downstream port of the root routing component; When the downstream port has reached the preset routing level and the third number of tree-like routing components are still not fully connected, continue to stack the tree-like routing components with the next downstream port of the root routing component until the third number of tree-like routing components are all connected.

4. The method according to claim 1, characterized in that: The component to be connected includes a third component; and the method further includes: In the case where there is a processor core to be connected, connecting the downstream port of the root routing component to the upstream port of the extended access component so that the downstream port of the extended access component is in a connectable state; The downstream port of the extended access component is connected to the third component; the third component is used to connect the processor core to the tree-like on-chip network.

5. The method according to claim 4, characterized in that The step of connecting the downstream port of the extended access component to the third component comprises: Determine a fourth number of the processor cores and a fifth number of downstream ports of the extended access component; the processor cores to be accessed correspond one-to-one to the third component; When the fourth number is less than or equal to the fifth number, connecting the fourth number of third components to different downstream ports of the extended access component respectively; When the fourth number is greater than the fifth number, the upstream port of the tree-like routing component is connected to the downstream port of the extended access component, and the fourth number of third components are respectively connected to different downstream ports of the tree-like routing component.

6. The method according to claim 4, characterized in that The method further comprises: Determining communication characteristic parameters of each processor core and a third component corresponding to each processor core; According to the communication characteristic parameters of each processor core, the communication configuration of the third component corresponding to each processor core is adjusted to establish communication between each processor core and the corresponding third component.

7. The method according to claim 1, characterized in that The method further comprises: Determine a topological structure of a tree-like network-on-chip composed of a target component set, the root routing component, and the tree-like routing component; the target component set includes the first component and the second component; According to the position of each target component in the topological structure, identification information of each target component is determined respectively; the identification information is used to implement addressing operations for the target component.

8. A network-on-chip construction device, characterized in that: The device comprises: A component type module, used to determine the component type of the component to be connected according to the number of levels of preset routing components included in the component to be connected; the component type includes a first type and a second type; the number of levels of preset routing components corresponding to the first type is greater than the number of levels of preset routing components corresponding to the second type; A first connecting module, configured to determine a first component of the first type among the components to be connected, and connect the first component to a downstream port of a preset root routing component; A tree-shaped routing module, used for connecting the remaining downstream ports in the root routing component to the upstream ports of the tree-shaped routing component when the first component is connected, so that the downstream ports of the tree-shaped routing component are in a connectable state; The second connection module is used to determine a second component belonging to the second type among the components to be connected, and connect the second component to the downstream port of the tree-shaped routing component to build a tree-shaped on-chip network.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the on-chip network construction method as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the on-chip network construction method according to any one of claims 1 to 7.

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