Repair circuit, repair locking method and memory

Abstract

The embodiment of the invention provides a repair circuit, a repair locking method and a memory, and the repair circuit comprises a clock circuit which is used for generating a target clock signal according to a reset signal, a repair locking signal and a preset clock signal; wherein when the repair locking signal is in an enabling state, the target clock signal is in an invalid state; the latch circuit is used for carrying out sampling processing on a preset address signal according to the target clock signal under the condition that the target clock signal is in an effective state, so that the latch circuit outputs a first address signal; under the condition that the target clock signal is in the invalid state, the sampling processing is not executed, so that the output of the latch circuit is in a latch state; wherein in the invalid state, the target clock signal does not have level flipping; in the effective state, the target clock signal has level flipping. According to the embodiment of the invention, the function of repairing and locking can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a repair circuit, a repair locking method and a memory. Background Art

[0002] During normal use of the memory, some storage rows and / or columns may fail. In order to extend the life of the memory in the event of a failure of the storage rows and / or columns, a post package repair (PPR) method is used to repair the storage rows and / or columns of the memory. Specifically, redundant storage rows and / or columns may be used to replace the failed storage rows and / or columns. The PPR method includes soft post package repair (Soft PPR, SPPR) and hard post package repair (Hard PPR, HPPR), wherein SPPR is a temporary repair and HPPR is a permanent repair. Summary of the invention

[0003] Embodiments of the present disclosure provide a repair circuit, a repair locking method, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a repair circuit, including:

[0005] A clock circuit, used for receiving a reset signal, a repair lock signal and a preset clock signal, and generating a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is in an invalid state;

[0006] a latch circuit, configured to receive the target clock signal, and when the target clock signal is in a valid state, perform sampling processing on a preset address signal according to the target clock signal, so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, not perform the sampling processing, so that the output of the latch circuit is in a latched state;

[0007] Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

[0008] In some embodiments, the clock circuit includes a clock control circuit and a first logic circuit, wherein:

[0009] The clock control circuit is used to receive the reset signal and the repair lock signal, and generate the clock control signal according to the reset signal and the repair lock signal;

[0010] The first logic circuit is used to receive the clock control signal and the preset clock signal, and generate the target clock signal according to the clock control signal and the preset clock signal; wherein: when the clock control signal is in a disabled state, the preset clock signal is output as the target clock signal; when the clock control signal is in an enabled state, the target clock signal is fixed in an invalid state.

[0011] In some embodiments, the clock control circuit includes a first NOT gate and a latch, and the first logic circuit includes a second NOT gate and a first NOR gate; wherein:

[0012] The input end of the first NOT gate is used to receive the repair lock signal, and the output end of the first NOT gate is connected to the first input end of the latch;

[0013] The second input end of the latch is used to receive the reset signal; the output end of the latch is connected to the first input end of the first NOR gate, and is used to output the clock control signal;

[0014] The input end of the second NOT gate is used to receive the preset clock signal, and the output end of the second NOT gate is connected to the second input end of the first NOR gate;

[0015] The output end of the first NOR gate is used to output the target clock signal.

[0016] In some embodiments, the latch includes a first NAND gate and a second NAND gate, wherein:

[0017] The first input end of the first NAND gate is connected to the output end of the first NAND gate, and the first input end of the first NAND gate serves as the first input end of the latch; the second input end of the first NAND gate is connected to the output end of the second NAND gate; the output end of the first NAND gate serves as the output end of the latch, and is used to output the clock control signal;

[0018] The first input end of the second NAND gate is connected to the output end of the first NAND gate; the second input end of the second NAND gate serves as the second input end of the latch, for receiving the reset signal.

[0019] In some embodiments, the repair circuit further includes an input circuit, an enabling circuit and a matching circuit, wherein:

[0020] The input circuit is used to receive an activation signal and a current address signal, and to sample and process the current address signal according to the activation signal to obtain a target address signal;

[0021] The enabling circuit is used to receive the current address signal, the activation signal, the repair signal and the target clock signal, sample the current address signal according to the activation signal and the repair signal to obtain an initial enabling signal, and sample and latch the initial enabling signal according to the target clock signal to obtain a target enabling signal;

[0022] The matching circuit is used to receive the target address signal, the first address signal and the target enable signal, compare the target address signal with the first address signal to generate a comparison signal, and perform logic processing on the target enable signal and the comparison signal to generate a matching signal.

[0023] In some embodiments, the input circuit includes a first sampling circuit, the input end of the first sampling circuit is used to receive the current address signal, and the clock end of the first sampling circuit is used to receive the activation signal; wherein:

[0024] The first sampling circuit is used for sampling the current address signal according to the activation signal to generate the target address signal when the activation signal is in an enabled state;

[0025] The target address signal includes an n-bit target address, where n is an integer greater than 0.

[0026] In some embodiments, the enabling circuit includes a second logic circuit, a second sampling circuit, and a third sampling circuit; wherein:

[0027] The second logic circuit is used to receive the activation signal and the repair signal, perform logic processing on the activation signal and the repair signal, and generate a trigger signal; wherein, when the activation signal and the repair signal are both in an enabled state, the trigger signal is in an enabled state;

[0028] The second sampling circuit is used to receive the trigger signal and the current address signal, sample the current address signal according to the trigger signal, and generate the initial enable signal;

[0029] The third sampling circuit is used to receive the target clock signal and the initial enable signal, and when the target clock signal is in a repair state, perform sampling and latching processing on the initial enable signal to generate the target enable signal.

[0030] In some embodiments, the second logic circuit includes a first AND gate; wherein:

[0031] The first input terminal of the first AND gate is used to receive the activation signal;

[0032] The second input terminal of the first AND gate is used to receive the repair signal;

[0033] The output terminal of the first AND gate is connected to the clock terminal of the second sampling circuit for outputting the trigger signal.

[0034] In some embodiments, the matching circuit includes a comparison circuit and a third logic circuit; wherein:

[0035] The comparison circuit is used to receive the target address signal and the first address signal, compare the target address signal with the first address signal, and generate the comparison signal;

[0036] The third logic circuit is used to receive the target enable signal and the comparison signal, and generate the matching signal according to the comparison signal when the target enable signal is in an enabled state; and fix the matching signal in a disabled state when the target enable signal is in a disabled state.

[0037] In some embodiments, the preset address signal includes an n-bit preset address, the first address signal includes an n-bit first address, the comparison signal includes an n-bit comparison sub-signal, the latch circuit includes n sampling sub-circuits, and the comparison circuit includes n comparison sub-circuits; wherein:

[0038] The i-th sampling subcircuit is used to receive the target clock signal and the i-th preset address, sample and latch the i-th preset address according to the target clock signal, and generate the i-th first address;

[0039] The i-th comparison sub-circuit is used to receive the i-th target address and the i-th first address, compare the i-th target address with the i-th first address, and generate an i-th comparison sub-signal, where i is an integer greater than 0 and less than or equal to n.

[0040] In some embodiments, the i-th comparison subcircuit comprises an i-th XNOR gate; wherein:

[0041] The first input terminal of the i-th XNOR gate is connected to the output terminal of the input circuit, and is used for receiving the i-th target address;

[0042] The second input terminal of the i-th XNOR gate is connected to the output terminal of the i-th sampling subcircuit, and is used to receive the i-th first address;

[0043] The output terminal of the i-th XNOR gate is used to output the i-th comparison sub-signal.

[0044] In some embodiments, the third logic circuit includes a second AND gate, wherein the second AND gate includes a first input terminal and n second input terminals; wherein:

[0045] The first input terminal of the second AND gate is used to receive the target enable signal;

[0046] The i-th second input terminal of the second AND gate is used to receive the i-th comparison sub-signal;

[0047] The output terminal of the second AND gate is used to output the matching signal.

[0048] In some embodiments, the repair signal includes a soft-packaged repair signal; and the preset clock signal is generated according to the repair signal and an initial clock signal.

[0049] In a second aspect, an embodiment of the present disclosure provides a method for repairing a lock, comprising:

[0050] Receiving a reset signal, a repair lock signal and a preset clock signal through a clock circuit, and generating a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is in an invalid state;

[0051] receiving the target clock signal through a latch circuit, and sampling a preset address signal according to the target clock signal when the target clock signal is in a valid state, so that the latch circuit outputs a first address signal; and not performing the sampling process when the target clock signal is in an invalid state, so that the output of the latch circuit is in a latched state;

[0052] Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

[0053] In a third aspect, an embodiment of the present disclosure provides a memory, comprising a repair circuit as described in any one of the first aspects.

[0054] The embodiment of the present disclosure provides a repair circuit, a repair locking method and a memory, wherein the repair circuit includes: a clock circuit, which is used to receive a reset signal, a repair locking signal and a preset clock signal, and generate a target clock signal according to the reset signal, the repair locking signal and the preset clock signal; wherein, when the repair locking signal is in an enabled state, the target clock signal is in an invalid state; a latch circuit, which is used to receive the target clock signal, and when the target clock signal is in a valid state, the preset address signal is sampled and processed according to the target clock signal, so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, the sampling process is not performed, so that the output of the latch circuit is in a latched state; wherein, when it is in an invalid state, the target clock signal does not have a level flip; when it is in a valid state, the target clock signal has a level flip. In this way, the clock circuit is controlled to generate a target clock signal by using the repair locking signal, and when it is necessary to repair the lock, the target clock signal is in an invalid state, so that the latch circuit cannot perform sampling and is maintained in a latched state, and finally the function of repairing the lock is realized without making too many changes to the circuit, which meets the requirements of the standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the structure of an SPPR circuit provided in an embodiment of the present disclosure;

[0056] Figure 2 A schematic diagram of the structure of a repair circuit provided by an embodiment of the present disclosure;

[0057] Figure 3 A schematic diagram of the structure of another repair circuit provided by an embodiment of the present disclosure;

[0058] Figure 4 A detailed structural diagram of a repair circuit provided in an embodiment of the present disclosure;

[0059] Figure 5 A signal timing diagram provided for an embodiment of the present disclosure;

[0060] Figure 6 A flowchart of a repair and undo method provided in an embodiment of the present disclosure;

[0061] Figure 7 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0064] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0065] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0066] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0067] Post Package Repair (PPR)

[0068] Soft Post Package Repair (SPPR);

[0069] Hard Post Package Repair (HPPR);

[0070] Dynamic Random Access Memory (DRAM);

[0071] D flip-flop (DFF);

[0072] Standard (SPEC);

[0073] Activation (ACT);

[0074] Row Address (RA);

[0075] Double Data Rate (DDR).

[0076] See also Figure 1 , which shows a schematic diagram of the composition structure of an SPPR circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the SPPR circuit 10 includes: an AND gate A1, a trigger DFF_1, a trigger DFF_2, a fuse latch X, n fuse latches (fuse latch 0 to fuse latch n-1), n ​​XNOR gates (XNOR gate X0 to XN-1), and an AND gate A2. Where n is an integer greater than 0.

[0077] It should be noted that the memory (such as DRAM) includes a storage array and a redundant storage array. When a row in the storage array fails, the redundant row in the redundant storage array can be used to replace the failed row to work. This replacement can be non-permanent (SPPR), or this replacement can also be permanent (HPPR). In the embodiments of the present disclosure, SPPR is mainly targeted.

[0078] like Figure 1 As shown, fuse latch 0 to fuse latch n-1 are used to latch the address FzRA 0 to FzRAn-1 of the disabled row (combined and recorded as FzRA<0:n-1>). Here, the address FzRA<0:n-1> can be sent to fuse latch 0 to fuse latch n-1 by other circuits or devices. Or, Figure 1 As shown, the input terminal D of each fuse latch is connected to the output terminal of the trigger DFF_2. The trigger DFF_2 samples the address signal corresponding to the failed row to obtain the address FzRA<0:n-1>, and sends it to the fuse latch 0 to the fuse latch n-1 for latching.

[0079] The flip-flop DFF_1 is used to sample the address RA of the access row according to the activation signal ACT to obtain n-bit address sampling signals RA0-RAn-1 (combined as RA<0:n-1>). The address RA comes from the activation signal ACT, that is, the address RA is the address information carried by the activation signal ACT.

[0080] AND gate A1 performs AND logic processing on activation signal ACT and post-soft packaging repair signal SPPR, and the signal output by AND gate A1 is used as the clock signal of trigger DFF_2. Only when activation signal ACT and post-soft packaging repair signal SPPR are both in the enabled state, DFF_2 will sample address RA to obtain enable signal EN.

[0081] like Figure 1 As shown, the input end of each fuse latch is represented by D, and the output end is represented by Q. Among them, the fuse latch X samples the enable signal EN according to the latch clock signal LatClk, obtains the repair enable signal FzEN, and sends it to the AND gate A2. The fuse latch i-1 samples the address FzRA i-1 according to the latch clock signal LatClk, and outputs the sampled signal from the output end Q and sends it to the XOR gate Xi-1. Among them, i is an integer greater than 0 and less than or equal to n. Among them, the latch clock signal LatClk is generated according to the soft package repair signal SPPR, that is, when the soft package repair signal SPPR is in the enabled state, the latch clock signal LatClk is valid, so that the fuse latch X, fuse latch 0~fuse latch n-1 can sample the signal received at the input end D according to the latch clock signal LatClk.

[0082] The XNOR gate Xi-1 compares the address RAi-1 output by the trigger DFF_1 with the signal obtained by sampling and latching the address FzRAi-1 by the fuse latch i-1. If the two are the same, the XNOR gate Xi-1 outputs a logic 1; if the two are different, the XNOR gate Xi-1 outputs a logic 0; the output signal of each XNOR gate Xi-1 is transmitted to the AND gate A2, and the AND gate A2 also receives the address enable signal FzEN output by the fuse latch X.

[0083] Thus, if each FzRA i-1 and RA i-1 can match (i.e., the two signals received by each XNOR gate Xi i-1 are the same), then the outputs of the n XNOR gates are all logic 1, indicating that the row corresponding to the address RA is the failed row. At the same time, if the signal output by the fuse latch X is also logic 1, it means that a repair operation needs to be performed, so that the matching signal Ma output by the AND gate A2 is logic 1, indicating that the redundant row is used to replace the failed row to ensure the normal operation of the memory.

[0084] It should also be noted that the address FzRA<0:n-1> of the failed row latched by fuse latch 0 to fuse latch n-1 is not fixed, but variable. For example, fuse latch 0 to fuse latch n-1 latch the address FzRA<0:n-1> corresponding to the first failed row. After the first failed row is repaired, fuse latch 0 to fuse latch n-1 can also latch the address FzRA<0:n-1> corresponding to the second failed row.

[0085] That is to say, Figure 1In the SPPR circuit 10 shown, a latch clock signal LatClk can be generated by using the SPPR command, and the latch clock signal LatClk can be sent to the fuse latch of the corresponding storage body (Bank) to retain the repaired failed row address FzRA 0~FzRA n-1. Afterwards, when the chip activates the row address, it will be compared with the retained failed row address FzRA 0~FzRA n-1. If the match is successful, the row decoder will access the redundant row instead of the failed row. In addition, the fuse latch X retains the fuse enable information (EN). Therefore, only when EN=logic 1, the retained address is valid and address matching is performed when activated, otherwise the Ma signal will always remain at a low level (logic 0).

[0086] The SPPR Lock SPEC standard was released later than SPPR. How to integrate SPPR Lock into SPPR circuit while meeting the standard is a problem that needs to be solved.

[0087] Based on this, the embodiment of the present disclosure provides a repair circuit, including: a clock circuit, which is used to receive a reset signal, a repair lock signal and a preset clock signal, and generate a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein, when the repair lock signal is in an enabled state, the target clock signal is in an invalid state; a latch circuit, which is used to receive the target clock signal, and when the target clock signal is in a valid state, the preset address signal is sampled and processed according to the target clock signal, so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, the sampling process is not performed, so that the output of the latch circuit is in a latched state; wherein, when it is in an invalid state, the target clock signal does not have a level flip; when it is in a valid state, the target clock signal has a level flip. In this way, the clock circuit is controlled to generate a target clock signal by using the repair lock signal, and when it is necessary to repair and lock, the target clock signal is in an invalid state, so that the latch circuit cannot perform sampling and maintains in a latched state, and finally the function of repairing and locking is realized without making too many changes to the circuit, which meets the requirements of the standard.

[0088] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0089] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a repair circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the repair circuit 20 includes:

[0090] The clock circuit 21 is used to receive a reset signal, a repair lock signal and a preset clock signal, and generate a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein, when the repair lock signal is in an enabled state, the target clock signal is in an invalid state;

[0091] The latch circuit 22 is used to receive the target clock signal, and when the target clock signal is in a valid state, the preset address signal is sampled according to the target clock signal, so that the latch circuit 22 outputs the first address signal; and when the target clock signal is in an invalid state, no sampling is performed, so that the output of the latch circuit 22 is in a latched state;

[0092] When the target clock signal is in an invalid state, there is no level flip in the target clock signal; when the target clock signal is in a valid state, there is a level flip in the target clock signal.

[0093] It should be noted that the repair circuit 20 may be an SPPR circuit, and correspondingly, the repair lock signal is a signal indicating that the SPPR resource is locked (which may be recorded as SPPR Lock CMD). Figure 1 On the basis of the SPPR circuit 10 shown, it is improved by adding the SPPR locking function without changing the SPPR circuit 10 too much to meet the requirements of the standard.

[0094] In this embodiment, SPPR is a method of quickly but temporarily repairing the row address of each bank group (storage structure such as bank group or bank) on a memory device (such as DDR5 DRAM), compared to HPPR, which takes longer but can permanently repair the row address.

[0095] SPPR lock allows SPPR resources to be locked in place. Lock operations can be performed on SPPR resources separately. In this way, the SPPR lock function can lock a specific SPPR resource in its current location and not allow another SPPR operation or SPPR undo operation to be performed on the resource. More specifically, if Figure 2As shown, the latch circuit 22 can latch the preset address signal, sample and latch the preset address signal, and generate a first address signal. Among them, the preset address signal is the address of the failed row, that is, in the SPPR, the latch circuit 22 is used to latch the address of the failed row; and the preset address signal is not fixed, but variable. For example, the latch circuit 22 latches the preset address signal corresponding to the first failed row and outputs the corresponding first address signal. After repairing the first failed row, the latch circuit 22 can also latch the preset address signal corresponding to the second failed row and output the corresponding first address signal. The repair lock (in the embodiment disclosed in the present invention, mainly refers to the SPPR lock) function is: during the period when the SPPR latch is effective, the latch circuit 22 only latches a specific preset address signal and outputs the corresponding first address signal, and does not latch other subsequent address signals.

[0096] In order to realize the SPPR locking function, such as Figure 2 As shown, the embodiment of the present disclosure adds a clock circuit 21 to the repair circuit 20, and the clock circuit 21 is connected to the latch circuit 22. The repair lock signal is used to indicate whether the repair circuit 20 enters the repair lock state. If the repair lock signal is in the enabled state, it indicates that the repair circuit 20 enters the repair lock state. If the repair lock signal is in the disabled state, it indicates that the repair circuit 20 does not enter the repair lock state and works normally; the preset clock signal is a clock signal that controls the latch circuit 22 to perform sampling when there is no repair lock function, for example: Figure 1 The latch clock signal LatClk in the SPPR circuit 10 is shown. The reset signal is used to reset the clock circuit 21 when the repair lock is not required.

[0097] It should also be noted that the repair lock signal controls the repair circuit 20 in the following manner: when the repair lock signal is in a non-enabled state, there is no need to perform repair lock, and the preset clock signal is output as the target clock signal; at this time, the level state of the target clock signal will change, and there will be a level flip, so that the latch circuit 22 can sample the preset address signal according to the target clock signal to obtain a first address signal; when the preset address signal changes, the latch circuit 22 can sample the changed preset address signal according to the target clock signal to generate a new first address signal.

[0098] When the repair lock signal is in the enabled state, the repair lock needs to be performed, and the new preset address signal is not latched. The preset clock signal has no effect on the target clock signal, and the target clock signal is always in an invalid state; at this time, the level state of the target clock signal is fixed, the level state does not change, and the level flip does not occur, so that the latch circuit 22 cannot sample the preset address signal, and the first address signal it outputs is the state it latched before. Even if the preset address signal changes, since the target clock signal is in a fixed level state, the latch circuit 22 cannot sample and will not generate a new first address signal, thereby realizing the repair lock function.

[0099] In this way, the embodiment of the present disclosure adds a clock circuit 21 in the SPPR circuit. When the repair lock signal is in an enabled state, the clock circuit 21 controls the target clock signal to be in an invalid state, so that the latch circuit 22 cannot sample the preset address signal according to the target clock signal, thereby realizing the function of repair locking without making too many changes to the circuit.

[0100] exist Figure 2 Based on Figure 3 , which shows a schematic diagram of the composition structure of another repair circuit provided by the embodiment of the present disclosure. Figure 3 As shown, in some embodiments, the repair circuit 20 further includes an input circuit 23, an enabling circuit 24 and a matching circuit 25, wherein:

[0101] The input circuit 23 is used to receive the activation signal and the current address signal, and to sample and process the current address signal according to the activation signal to obtain the target address signal;

[0102] The enabling circuit 24 is used to receive the current address signal, the activation signal, the repair signal and the target clock signal, sample the current address signal according to the activation signal and the repair signal to obtain the initial enabling signal, sample and latch the initial enabling signal according to the target clock signal to obtain the target enabling signal;

[0103] The matching circuit 25 is used to receive the target address signal, the first address signal and the target enable signal, compare the target address signal with the first address signal to generate a comparison signal, and perform logic processing on the target enable signal and the comparison signal to generate a matching signal.

[0104] It should be noted that the activation signal is used to activate the corresponding storage address in the memory (such as storage unit, row, column, storage body, etc., this embodiment takes row as an example), and the current address signal is used to locate the storage address. In other words, the activation signal and the current address signal are corresponding.

[0105] The input circuit 23 is a circuit with sampling and latching functions. When receiving the activation signal and the current address signal, if the activation signal and the current address signal are valid signals, that is, the activation signal and the current address signal can successfully locate the row (or storage row) in the storage array, then the input circuit 23 will sample the current address signal according to the activation signal to obtain the target address signal.

[0106] The activation signal and the current address signal are also transmitted to the enable circuit 24, and the enable circuit 24 also receives the repair signal. In this embodiment, the repair signal can be an SPPR signal. The enable circuit 24 is also a circuit with sampling and latching functions. In this way, when the repair signal is in the enabled state, the repair circuit 20 enters the repair working state. If the activation signal and the current address signal are valid signals, the enable circuit 24 samples the current address signal according to the activation signal to generate an initial enable signal, and the initial enable signal is in the enabled state; further, if the repair lock signal is in the non-enabled state, the target clock signal is in the valid state, and the enable circuit 24 samples and latches the initial enable signal according to the target clock signal to generate a target enable signal in the enabled state, and sends it to the matching circuit 25; if the repair lock signal is in the enabled state, the target clock signal is in the invalid state. At this time, the enable circuit 24 cannot sample the initial enable signal, so that the target enable signal will maintain its previous state.

[0107] In this way, on the one hand, the target clock signal is sent to the latch circuit 22 to control whether the preset address signal is sampled and latched. When the target clock signal is in an invalid state, the latch circuit 22 can be in a latched state. Even if the preset address signal changes, the first address signal will not change, thereby realizing the repair latch function. On the other hand, the target clock signal is also sent to the enable circuit 24 to control whether the initial enable signal is sampled and latched. When the target clock signal is in an invalid state, the initial enable signal will not be sampled, so that the target enable signal is fixed in the previous state.

[0108] For the matching circuit 25, when the target clock signal is in the effective state, it compares the first address signal with the target address signal. If the first address signal and the target address signal are the same, the generated comparison signal is in one level state, indicating that the row corresponding to the current address signal is the invalid row corresponding to the preset address signal; if the first address signal and the target address signal are different, the generated comparison signal is in another level state, indicating that the row corresponding to the current address signal is not the invalid row; and then the target enable signal performs logic control, and only when the target enable signal is in the enabled state, the matching signal is output according to the comparison result, otherwise, the matching signal will maintain a fixed level state (non-enabled state). If the current address signal corresponds to the invalid row, the redundant row is used to replace the invalid row for operation, otherwise, the row corresponding to the current address signal works normally.

[0109] It should also be noted that in the embodiment of the present disclosure, a high level of logic 1 is used as an enabled state and a low level of logic 0 is used as a disabled state. However, a high level of logic 1 may be used as a disabled state and a low level of logic 0 may be used as an enabled state. This is not limited to this and is specifically set in combination with the circuit.

[0110] In a specific circuit implementation, see Figure 4 , which shows a detailed structural diagram of a repair circuit provided by an embodiment of the present disclosure. For the input circuit 23, as Figure 4 As shown, the input circuit 23 includes a first sampling circuit 231, the input end of the first sampling circuit 231 is used to receive the current address signal RA, and the clock end of the first sampling circuit 231 is used to receive the activation signal ACT; wherein:

[0111] The first sampling circuit 231 is used for sampling the current address signal RA according to the activation signal ACT to generate the target address signal RA<0:n-1> when the activation signal ACT is in an enabled state;

[0112] The target address signal RA<0:n-1> includes an n-bit target address RA i-1, where n is an integer greater than 0, and i is an integer greater than 0 and less than or equal to n.

[0113] It should be noted that, in the embodiment of the present disclosure, the first sampling circuit 231 can be implemented by a DFF (or other devices having sampling latch and other functions). Figure 4 As shown, the first sampling circuit 231 is represented by DFF_1. The input terminal and the clock terminal of the first sampling circuit 231 are respectively used as two input terminals of the input circuit 23, and the output terminal of the first sampling circuit 231 is used as the output terminal of the input circuit 23.

[0114] Wherein, RA represents the current address signal, and ACT represents the activation signal. When the activation signal ACT is in the enabled state, it indicates that it carries valid address information, that is, the current address signal RA is valid and can indicate a row in the storage array (here, the row address is taken as an example. In other embodiments, it can also be a specific storage unit, a column address, or even a storage body, etc.). When the activation signal ACT is converted from the disabled state to the enabled state, a rising edge can be formed to trigger the first sampling circuit 231, so that the first sampling circuit 231 samples the current address signal RA according to the activation signal ACT to obtain the target address signal RA<0:n-1>, and the target address signal RA<0:n-1> includes an n-bit target address: RA 0~RA n-1.

[0115] Correspondingly, the current address signal may include an n-bit current address, and the first sampling circuit 231 may include n DFFs, each DFF receives an activation signal ACT and a current address, performs sampling according to the activation signal ACT and the current address, and generates a corresponding target address.

[0116] For the clock circuit 21, if Figure 4 As shown, the clock circuit 21 includes a clock control circuit 211 and a first logic circuit 212, wherein:

[0117] The clock control circuit 211 is used for receiving a reset signal Reset_n and a repair lock signal SPPR Lock, and generating a clock control signal Clk Lock according to the reset signal Reset_n and the repair lock signal SPPR Lock;

[0118] The first logic circuit 212 is used to receive the clock control signal Clk Lock and the preset clock signal Clk1, and generate the target clock signal Clk2 according to the clock control signal Clk Lock and the preset clock signal Clk1; wherein: when the clock control signal Clk Lock is in a disabled state, the preset clock signal Clk1 is output as the target clock signal Clk2; when the clock control signal Clk Lock is in an enabled state, the target clock signal Clk2 is in an invalid state.

[0119] It should be noted that if Figure 4 As shown, since this embodiment is mainly for SPPR, the repair lock signal can be recorded as SPPR Lock, Reset_n represents the reset signal, Clk Lock represents the clock control signal, Clk1 represents the preset clock signal, and Clk2 represents the target clock signal.

[0120] When the repair lock signal SPPR Lock is in the enabled state, the clock control circuit 211 latches the state of the repair lock signal SPPR Lock, so that the clock control signal Clk Lock output by the clock control circuit 211 is in the enabled state until the reset signal Reset_n resets the clock control signal Clk Lock to the initial state.

[0121] One input end of the first logic circuit 212 is connected to the output end of the clock control circuit 211 for receiving the clock control signal Clk Lock, and the other input end of the first logic circuit 212 receives the preset clock signal Clk1. When the clock control signal Clk Lock is in a disabled state, the state of the latch circuit 22 will not be locked, and the first logic circuit 212 will output the preset clock signal Clk1 as the target clock signal Clk2. At this time, if the preset clock signal Clk1 is in a valid state, the target clock signal Clk2 is also in a valid state, so that the latch circuit 22 can normally perform the sampling function according to the target clock signal Clk2; when the clock control signal Clk Lock is in an enabled state, the state of the latch circuit 22 will be locked, and the first logic circuit 212 will shield the preset clock signal Clk1. At this time, no matter what state the preset clock signal Clk1 is in, the target clock signal Clk2 is always in an invalid state, and then the latch circuit 22 cannot perform the sampling function according to the target clock signal Clk2, and the state is locked.

[0122] Specifically, Figure 4 As shown, the clock control circuit 211 includes a first NOT gate N1 and a latch LAT, and the first logic circuit 212 includes a second NOT gate N2 and a first NOR gate XO; wherein:

[0123] An input end of the first NOT gate N1 is used to receive a repair lock signal SPPR Lock, and an output end of the first NOT gate N1 is connected to a first input end of the latch LAT;

[0124] The second input terminal of the latch LAT is used to receive the reset signal Reset_n; the output terminal of the latch LAT is connected to the first input terminal of the first NOR gate XO, and is used to output the clock control signal Clk Lock;

[0125] The input end of the second NOT gate N2 is used to receive the preset clock signal Clk1, and the output end of the second NOT gate N2 is connected to the second input end of the first NOR gate XO;

[0126] The output terminal of the first NOR gate XO is used to output the target clock signal Clk2.

[0127] Take the latch LAT composed of NAND gates as an example. Figure 4As shown, the latch LAT includes a first NAND gate NA1 and a second NAND gate NA2, wherein:

[0128] The first input end of the first NAND gate NA1 is connected to the output end of the first NAND gate N1, and the first input end of the first NAND gate NA1 serves as the first input end of the latch LAT; the second input end of the first NAND gate NA1 is connected to the output end of the second NAND gate NA2; the output end of the first NAND gate NA1 serves as the output end of the latch LAT, and is used to output the clock control signal ClkLock;

[0129] The first input terminal of the second NAND gate NA2 is connected to the output terminal of the first NAND gate NA1 ; the second input terminal of the second NAND gate NA2 serves as the second input terminal of the latch LAT, and is used to receive the reset signal Reset_n.

[0130] It should be noted that in Figure 4 In the example shown, the reset signal Reset_n is a signal that is effective at a low level (logic 0). When Reset_n is at a low level, the output of the latch LAT is reset to an initial state. During normal operation of the circuit, Reset_n is at a high level (logic 1).

[0131] During the period when Reset_n is at a high level, if the repair lock signal SPPR Lock is in an enabled state (logic 1), the signal output by the first NOT gate N1 is logic 0, and the signal received by the first input terminal of the latch NA1 is logic 0, then the clock control signal Clk Lock output by the latch LAT is in an enabled state (logic 1). At this time, for the NOR gate XO, one of its input terminals is connected to the output terminal of the latch LAT to receive the clock control signal Clk Lock in an enabled state, and the other input terminal is connected to the output terminal of the second NOT gate N2 to receive the inverted signal of the preset clock signal Clk1; since the clock control signal Clk Lock is logic 1, no matter what state the preset clock signal Clk1 is in, the target clock signal Clk2 output by the NOR gate XO is always logic 0 and is in an invalid state.

[0132] During the period when Reset_n is at a high level, if the repair lock signal SPPR Lock is in a disabled state (logic 0), the signal output by the first NOT gate N1 is logic 1, and the signal received at the first input terminal of the latch NA1 is logic 1, then the clock control signal output by the latch LAT maintains the previous state until Reset_n becomes a low level, and the clock control signal ClkLock is reset. In this case, if the clock control signal Clk Lock is maintained at logic 1, the output of the NOR gate XO is consistent with the description in the previous paragraph; if the clock control signal Clk Lock is maintained at logic 0, the target clock signal Clk2 output by the NOR gate XO is opposite to the level state of the signal received at its second input terminal, that is, the same as the level state of the preset clock signal Clk1.

[0133] In this embodiment, the preset clock signal Clk1 can be generated by performing a logical operation on the repair signal SPPR and the initial clock signal. Here, the initial clock signal can be a system clock or other signals, and the preset clock signal Clk1 can be generated by performing a logical operation on the repair signal SPPR and the initial clock signal. Therefore, the preset clock signal Clk1 can also be recorded as SPPR Clk. For the preset clock signal Clk1, when the repair signal SPPR is in the enabled state, it generates a short pulse, which is used as a sampling clock for the latch circuit 22 and the enable circuit 24.

[0134] It should also be noted that, for the first logic circuit 212, it can also be implemented by a third NOT gate and a third AND gate. In this case, the third NOT gate is connected to the output end of the clock control circuit 211, and the output end of the third NOT gate is connected to the first input end of the third AND gate. The second input end of the third AND gate is used to receive the preset clock signal Clk1, and the output end of the third AND gate is used to output the target clock signal Clk2. Figure 4 The same functions as those of the first logic circuit 212 are not described in detail here.

[0135] In this way, when the repair circuit 20 is performing a repair operation, if it is necessary to enter a repair locked state, it is only necessary to enable the repair lock signal SPPR Lock, and the clock control circuit 211 will latch the enable state, so that the clock control signal Clk Lock is in an enabled state, thereby controlling the target clock signal Clk2 to be in an invalid state, so that the enabling circuit 24 and the latch circuit 22 cannot perform a sampling operation, thereby achieving SPPR locking, until the reset signal Reset_n resets the clock control signal Clk Lock.

[0136] For the enabling circuit 24, if Figure 4As shown, the enabling circuit 24 includes a second logic circuit 241, a second sampling circuit 242 and a third sampling circuit 243; wherein:

[0137] The second logic circuit 241 is used to receive the activation signal ACT and the repair signal SPPR, perform logic processing on the activation signal ACT and the repair signal SPPR, and generate a trigger signal; wherein, when the activation signal ACT and the repair signal SPPR are both in an enabled state, the trigger signal is in an enabled state;

[0138] The second sampling circuit 242 is used to receive the trigger signal and the current address signal RA, sample the current address signal RA according to the trigger signal, and generate an initial enable signal EN;

[0139] The third sampling circuit 243 is used for receiving the target clock signal Clk2 and the initial enable signal EN, and when the target clock signal Clk2 is in a valid state, sampling and latching the initial enable signal EN to generate a target enable signal Fz EN.

[0140] It should be noted that if Figure 4 As shown, in the embodiment of the present disclosure, the second sampling circuit 242 can be implemented by a DFF (or other devices with sampling and latching functions), the third sampling circuit 243 is a circuit with sampling and latching functions, the third sampling circuit 243 samples and latches the initial enable signal EN according to the target clock signal Clk2 to obtain the target enable signal FzEN, the third sampling circuit 243 can be implemented by a fuse latch, etc., and the repair signal can be a repair signal after soft packaging. Therefore, Figure 4 As shown, the second sampling circuit 242 is represented by DFF_2, the third sampling circuit 243 is represented by the fuse latch X, the repair signal is represented by SPPR, EN represents the initial enable signal, and FzEN represents the target enable signal.

[0141] Specifically, Figure 4 As shown, the second logic circuit 241 includes a first AND gate A1; wherein:

[0142] The first input terminal of the first AND gate A1 is used to receive the activation signal ACT;

[0143] The second input terminal of the first AND gate A1 is used to receive the repair signal SPPR;

[0144] The output terminal of the first AND gate A1 is connected to the clock terminal of the second sampling circuit 242 for outputting a trigger signal.

[0145] It should be noted that if Figure 4As shown, the first input terminal and the second input terminal of the first AND gate A1 and the clock terminal of the third sampling circuit 243 are respectively used as the three input terminals of the enabling circuit 24 , and the output terminal of the third sampling circuit 243 is used as the output terminal of the enabling circuit 24 .

[0146] The second logic circuit 241 is used to perform an AND logic operation on the activation signal ACT and the repair signal SPPR, and the second logic circuit 241 can be implemented by an AND gate A1. In this way, when the activation signal ACT and the repair signal SPPR are both in the enabled state (logic 1), the trigger signal output by the first AND gate A1 is also in the enabled state, otherwise, the trigger signal is in the disabled state.

[0147] When the trigger signal is converted from the non-enabled state to the enabled state, a rising edge is formed to trigger the second sampling circuit 242, so that the second sampling circuit 242 can sample and latch the current address signal RA according to the trigger signal, obtain the initial enable signal EN, and send it to the third sampling circuit 243. Here, when the second sampling circuit 242 performs sampling, if the current address signal RA can effectively indicate a row in the storage array, the second sampling circuit 242 can output the initial enable signal EN in the enabled state; otherwise, the initial enable signal EN is in the non-enabled state.

[0148] The input terminal D of the fuse latch X is connected to the output terminal of DFF_2 to receive the initial enable signal EN, and the clock terminal of the fuse latch X is connected to the output terminal of the clock circuit 21 (i.e., the output terminal of the first NOR gate XO) to receive the target clock signal Clk2. In this way, during the SPPR locking period, the target clock signal Clk2 is in an invalid state, so that the fuse latch X cannot sample the initial enable signal EN, and the target enable signal FzEN will maintain the state before the target clock signal Clk2 becomes invalid.

[0149] For the matching circuit 25, Figure 4 As shown, the matching circuit 25 includes a comparison circuit 251 and a third logic circuit 252; wherein:

[0150] The comparison circuit 251 is used for receiving the target address signal RA<0:n-1> and the first address signal FA<0:n-1>, comparing the target address signal RA<0:n-1> with the first address signal FA<0:n-1>, and generating a comparison signal Com<0:n-1>;

[0151] The third logic circuit 252 is used to receive the target enable signal Fz EN and the comparison signal Com<0:n-1>, and generate a match signal Ma according to the comparison signal Com<0:n-1> when the target enable signal FzEN is in an enabled state; when the target enable signal FzEN is in a disabled state, the match signal Ma is fixed in a disabled state.

[0152] It should be noted that the target enable signal FzEN is used to control whether to generate the match signal Ma according to the comparison signal Com<0:n-1>. That is, when the target enable signal FzEN is in the enabled state, the repair circuit 20 performs the repair operation normally. If the target address signal RA<0:n-1> is the same as the first address signal FA<0:n-1>, it means that the row corresponding to the current address signal RA is the failed row corresponding to the preset address signal FzRA<0:n-1>, then the match signal Ma is in the enabled state, indicating that the redundant row is used to replace the failed row; if the target address signal RA<0:n-1> is different from the first address signal FA<0:n-1>, it means that the row corresponding to the current address signal RA is not the failed row corresponding to the preset address signal FzRA<0:n-1>, then the match signal Ma is in the disabled state, indicating that the row corresponding to the current address signal RA works normally.

[0153] When the target enable signal FzEN is in a disabled state, no matter what the comparison result between the target address signal RA<0:n-1> and the first address signal FA<0:n-1> is, the match signal Ma is in a disabled state, and the repair circuit 20 does not perform a repair operation.

[0154] For the latch circuit 22 and the comparison circuit 251, if Figure 4 As shown, the preset address signal FzRA<0:n-1> includes an n-bit preset address FzRA i-1, the first address signal FA<0:n-1> includes an n-bit first address FA i-1, the comparison signal Com<0:n-1> includes an n-bit comparison sub-signal Com i-1, the latch circuit 22 includes n sampling sub-circuits 221, and the comparison circuit 251 includes n comparison sub-circuits 2511; wherein:

[0155] The i-th sampling sub-circuit 221 is used to receive the target clock signal Clk2 and the i-th preset address FzRA i-1, sample and latch the i-th preset address FzRA i-1 according to the target clock signal Clk2, and generate the i-th first address FA i-1;

[0156] The i-th comparison sub-circuit 2511 is used to receive the i-th target address RA i-1 and the i-th first address FA i-1, compare the i-th target address RA i-1 with the i-th first address FA i-1, and generate the i-th comparison sub-signal Com i-1, where i is an integer greater than 0 and less than or equal to n.

[0157] It should be noted that if Figure 4 As shown, the sampling sub-circuit 221 is a circuit with sampling and latching functions. The input terminal D of the i-th sampling sub-circuit 221 receives the i-th preset address FzRA i-1, the clock terminal of each sampling sub-circuit 221 receives the target clock signal Clk2, and the output terminal Q of the i-th sampling sub-circuit 221 outputs the i-th first address FA i-1.

[0158] The i-th sampling subcircuit 221 samples and latches the corresponding i-th preset address FzRA i-1 according to the target clock signal Clk2 to obtain the corresponding i-th first address RA1 i-1. The sampling subcircuit 221 can be a fuse latch. Figure 4 In FIG. 1 , the fuse latch in the i-th sampling sub-circuit 221 is recorded as fuse latch i-1, and the n fuse latches in the latch circuit 22 are recorded as fuse latch 0 to fuse latch n-1, respectively.

[0159] The comparison sub-circuit 2511 is a circuit with a comparison function. The i-th comparison sub-circuit 2511 receives the i-th target address RA i-1 and the i-th first address FA i-1. When the i-th target address RA i-1 and the i-th first address FA i-1 are the same, the comparison sub-signal Com i-1 output by the i-th comparison sub-circuit 2511 is a first value. When the i-th target address RAi-1 and the i-th first address FA i-1 are different, the comparison sub-signal Comi-1 output by the i-th comparison sub-circuit 2511 is a second value.

[0160] The first value may be a high-level logic 1, and the second value may be a low-level logic 0; or, the first value may be a low-level logic 0, and the second value may be a high-level logic 1, and there is no specific limitation on this.

[0161] like Figure 4 As shown, for the comparison circuit 251 and the third logic circuit 252, in one implementation, the i-th comparison sub-circuit 2511 includes the i-th XNOR gate Xi-1; wherein:

[0162] The first input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal of the input circuit 23 for receiving the i-th target address RA i-1;

[0163] The second input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal of the i-th sampling sub-circuit 221, and is used to receive the i-th first address FA i-1;

[0164] The output terminal of the i-th XNOR gate Xi-1 is used for outputting the i-th comparison sub-signal Com i-1.

[0165] The third logic circuit 252 includes a second AND gate A2, and the second AND gate A2 includes a first input terminal and n second input terminals; wherein:

[0166] The first input terminal of the second AND gate A2 is used to receive the target enable signal FzEN;

[0167] The i-th second input terminal of the second AND gate A2 is used for receiving the i-th comparison sub-signal Com i-1;

[0168] The output terminal of the second AND gate A2 is used to output a matching signal Ma.

[0169] It should be noted that if Figure 4 As shown, taking the first sampling sub-circuit 221 and the first comparison sub-circuit 2511 as an example, the output terminal Q of the fuse latch 0 is connected to the second input terminal of the X-OR gate X0, and the first input terminal of the X-OR gate X0 is connected to the output terminal of the input circuit 23. In this way, the first input terminal and the second input terminal of the X-OR gate X0 receive the first target address RA 0 and the first first address FA 0 respectively; if the first first address FA 0 and the first target address RA 0 are the same, the first comparison sub-signal Com 0 output by the X-OR gate X0 is logic 1; if the first first address RA1 0 and the first target address RA 0 are different, the first comparison sub-signal Com 0 output by the X-OR gate X0 is logic 0.

[0170] The same is true for the remaining sampling sub-circuit 221 and the comparison sub-circuit 2511 , which will not be described in detail here.

[0171] It should also be noted that, for the comparison circuit 251 and the third logic circuit 252, in another implementation, the i-th comparison sub-circuit includes the i-th XOR gate; wherein:

[0172] A first input terminal of the i-th XOR gate is connected to the output terminal of the input circuit for receiving the i-th target address;

[0173] The second input terminal of the i-th XOR gate is connected to the output terminal of the i-th sampling subcircuit for receiving the i-th first address;

[0174] The output terminal of the i-th XOR gate is used to output the i-th comparison sub-signal.

[0175] The third logic circuit includes a third NAND gate, and the third NAND gate includes a first input terminal and n second input terminals; wherein:

[0176] The first input terminal of the third NAND gate is used to receive the target enable signal;

[0177] The i-th second input terminal of the third NAND gate is used to receive the i-th comparison sub-signal;

[0178] The output terminal of the third NAND gate is used to output a matching signal.

[0179] It should be noted that the comparison subcircuit can also be implemented by an XOR gate. In this case, the third logic circuit is implemented by a NAND gate, which can also implement Figure 4 The same functions are not repeated here.

[0180] exist Figure 4 Based on the circuit shown, see Figure 5 , which shows a signal timing diagram provided by an embodiment of the present disclosure. Figure 5 As shown, a high-level logic 1 represents an enabled state, and a low-level logic 2 represents a disabled state. During the period when the repair signal SPPR is in the enabled state, after the repair lock signal SPPR Lock becomes the enabled state, the enabled state of the repair lock signal SPPR Lock is latched, so that after the repair lock signal SPPR Lock becomes the enabled state and before the reset signal Reset_n becomes the low-level state to reset the circuit (due to the influence of the device, there is a certain delay), the clock control signal Clk Lock is in the enabled state, and the initial enable signal Clk1 during this period is in an invalid state, and the target enable signal Clk2 is also in an invalid state (it can be understood that since the clock control signal Clk Lock is in the enabled state, even if the initial enable signal Clk1 is in a valid state, the target enable signal Clk2 is still in an invalid state), so that the address signal latched by the latch circuit 22 is the first address signal Pre FA<0:n-1> obtained by sampling and latching the last preset address signal; after the circuit is reset, and the repair lock signal SPPR Lock is in the disabled state, and the circuit performs the repair operation normally. After the rising edge of the initial enable signal Clk1 arrives, the target clock signal Clk2 is correspondingly in the valid state, and the latch circuit 22 samples and latches the new preset address signal to obtain a new first address signal FA<0:n-1> (due to the influence of the device, there is a certain delay).

[0181] In addition, from Figure 5 It can be seen from FIG. 1 that when the clock control signal Clk Lock becomes enabled and the rising edge of the preset clock signal Clk1 arrives, the target enable signal FzEN is in a disabled state, so that the matching signal Ma is fixed in a disabled state.

[0182] The simulation results show that the repair circuit 20 can realize the repair operation and the repair locking function.

[0183] In short, the disclosed embodiments relate to DRAM, and more particularly to SPPR design, and by using this solution, SPPR locking can be applied to existing DDR5 products. Since the SPPR Lock SPEC was released later than SPPR, this new function needs to be added to the existing SPPR function, but at the same time, too much structural and logical changes are not wanted to affect the existing SPPR. This solution introduces a method for implementing the SPPR locking function and adapting to the current SPPR design.

[0184] The disclosed embodiment combines SPPR with SPPR lock to achieve the "lock" function without changing the current design too much, thereby reducing the risk of change and resource consumption. Specifically: on the one hand, the target clock signal Clk2 is generated by combining the repair signal SPPR and the repair lock signal SPPR Lock; on the other hand, when performing SPPR lock, "Clk Lock" is latched to a high level to block the subsequent target clock signal Clk2 until it is reset by the reset signal Reset_n. This solution introduces a simple but efficient design to implement the SPPR lock function of DDR5, which can achieve SPEC requirements with limited circuit implementation, thereby reducing design time and size costs.

[0185] In another embodiment of the present disclosure, see Figure 6 , which shows a flowchart of a method for repairing a lock provided by an embodiment of the present disclosure. Figure 6 As shown, the method may include:

[0186] S601: receiving a reset signal, a repair lock signal and a preset clock signal through a clock circuit, and generating a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein, when the repair lock signal is in an enabled state, the target clock signal is in an invalid state.

[0187] S602: Receive a target clock signal through a latch circuit, and when the target clock signal is in a valid state, sample a preset address signal according to the target clock signal so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, do not perform sampling so that the output of the latch circuit is in a latched state.

[0188] When the target clock signal is in an invalid state, there is no level flip in the target clock signal; when the target clock signal is in a valid state, there is a level flip in the target clock signal.

[0189] It should be noted that the repair locking method provided in the embodiment of the present disclosure is applied to the repair circuit 20 in the aforementioned embodiment. For details not disclosed in this embodiment, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0190] In another embodiment of the present disclosure, see Figure 7 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 7 As shown, the memory 70 at least includes the repair circuit 20 in the aforementioned embodiment.

[0191] It should be noted that the memory 70 can be a semiconductor memory such as DRAM. For DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0192] Since the memory 70 includes the repair circuit 20, the repair locking function can be implemented, which meets the standard requirements.

[0193] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0194] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0195] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0196] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0197] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0198] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0199] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A repair circuit, characterized in that: include: A clock circuit, used for receiving a reset signal, a repair lock signal and a preset clock signal, and generating a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is in an invalid state; a latch circuit, configured to receive the target clock signal, and when the target clock signal is in a valid state, perform sampling processing on a preset address signal according to the target clock signal, so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, not perform the sampling processing, so that the output of the latch circuit is in a latched state; Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

2. The repair circuit according to claim 1, characterized in that: The clock circuit comprises a clock control circuit and a first logic circuit, wherein: The clock control circuit is used to receive the reset signal and the repair lock signal, and generate a clock control signal according to the reset signal and the repair lock signal; The first logic circuit is used to receive the clock control signal and the preset clock signal, and generate the target clock signal according to the clock control signal and the preset clock signal; wherein: when the clock control signal is in a disabled state, the preset clock signal is output as the target clock signal; when the clock control signal is in an enabled state, the target clock signal is fixed in an invalid state.

3. The repair circuit according to claim 2, characterized in that: The clock control circuit includes a first NOT gate and a latch, and the first logic circuit includes a second NOT gate and a first NOR gate; wherein: The input end of the first NOT gate is used to receive the repair lock signal, and the output end of the first NOT gate is connected to the first input end of the latch; The second input end of the latch is used to receive the reset signal; the output end of the latch is connected to the first input end of the first NOR gate, and is used to output the clock control signal; The input end of the second NOT gate is used to receive the preset clock signal, and the output end of the second NOT gate is connected to the second input end of the first NOR gate; The output end of the first NOR gate is used to output the target clock signal.

4. The repair circuit according to claim 3, characterized in that: The latch comprises a first NAND gate and a second NAND gate, wherein: The first input end of the first NAND gate is connected to the output end of the first NAND gate, and the first input end of the first NAND gate serves as the first input end of the latch; the second input end of the first NAND gate is connected to the output end of the second NAND gate; the output end of the first NAND gate serves as the output end of the latch, and is used to output the clock control signal; The first input end of the second NAND gate is connected to the output end of the first NAND gate; the second input end of the second NAND gate serves as the second input end of the latch, for receiving the reset signal.

5. The repair circuit according to claim 1, characterized in that: The repair circuit further includes an input circuit, an enabling circuit and a matching circuit, wherein: The input circuit is used to receive an activation signal and a current address signal, and to sample and process the current address signal according to the activation signal to obtain a target address signal; The enabling circuit is used to receive the current address signal, the activation signal, the repair signal and the target clock signal, sample the current address signal according to the activation signal and the repair signal to obtain an initial enabling signal, and sample and latch the initial enabling signal according to the target clock signal to obtain a target enabling signal; The matching circuit is used to receive the target address signal, the first address signal and the target enable signal, compare the target address signal with the first address signal to generate a comparison signal, and perform logic processing on the target enable signal and the comparison signal to generate a matching signal.

6. The repair circuit according to claim 5, characterized in that: The input circuit comprises a first sampling circuit, the input end of the first sampling circuit is used to receive the current address signal, and the clock end of the first sampling circuit is used to receive the activation signal; wherein: The first sampling circuit is used for sampling the current address signal according to the activation signal to generate the target address signal when the activation signal is in an enabled state; The target address signal includes an n-bit target address, where n is an integer greater than 0.

7. The repair circuit according to claim 5, characterized in that: The enabling circuit includes a second logic circuit, a second sampling circuit and a third sampling circuit; wherein: The second logic circuit is used to receive the activation signal and the repair signal, perform logic processing on the activation signal and the repair signal, and generate a trigger signal; wherein, when the activation signal and the repair signal are both in an enabled state, the trigger signal is in an enabled state; The second sampling circuit is used to receive the trigger signal and the current address signal, sample the current address signal according to the trigger signal, and generate the initial enable signal; The third sampling circuit is used to receive the target clock signal and the initial enable signal, and when the target clock signal is in a repair state, perform sampling and latching processing on the initial enable signal to generate the target enable signal.

8. The repair circuit according to claim 7, characterized in that: The second logic circuit comprises a first AND gate; wherein: The first input terminal of the first AND gate is used to receive the activation signal; The second input terminal of the first AND gate is used to receive the repair signal; The output terminal of the first AND gate is connected to the clock terminal of the second sampling circuit for outputting the trigger signal.

9. The repair circuit according to claim 5, characterized in that: The matching circuit includes a comparison circuit and a third logic circuit; wherein: The comparison circuit is used to receive the target address signal and the first address signal, compare the target address signal with the first address signal, and generate the comparison signal; The third logic circuit is used to receive the target enable signal and the comparison signal, and generate the matching signal according to the comparison signal when the target enable signal is in an enabled state; and fix the matching signal in a disabled state when the target enable signal is in a disabled state.

10. The repair circuit according to claim 9, characterized in that: The preset address signal includes an n-bit preset address, the first address signal includes an n-bit first address, the comparison signal includes an n-bit comparison sub-signal, the latch circuit includes n sampling sub-circuits, and the comparison circuit includes n comparison sub-circuits; wherein: The i-th sampling subcircuit is used to receive the target clock signal and the i-th preset address, sample and latch the i-th preset address according to the target clock signal, and generate the i-th first address; The i-th comparison sub-circuit is used to receive the i-th target address and the i-th first address, compare the i-th target address with the i-th first address, and generate an i-th comparison sub-signal, where i is an integer greater than 0 and less than or equal to n.

11. The repair circuit according to claim 10, wherein the i-th comparison subcircuit comprises an i-th XNOR gate; wherein: The first input terminal of the i-th XNOR gate is connected to the output terminal of the input circuit, and is used for receiving the i-th target address; The second input terminal of the i-th XNOR gate is connected to the output terminal of the i-th sampling subcircuit, and is used to receive the i-th first address; The output terminal of the i-th XNOR gate is used to output the i-th comparison sub-signal.

12. The repair circuit according to claim 10, characterized in that: The third logic circuit includes a second AND gate, wherein the second AND gate includes a first input terminal and n second input terminals; wherein: The first input terminal of the second AND gate is used to receive the target enable signal; The i-th second input terminal of the second AND gate is used to receive the i-th comparison sub-signal; The output terminal of the second AND gate is used to output the matching signal.

13. The repair circuit according to any one of claims 5 to 12, characterized in that: The repair signal includes a repair signal after soft packaging; and the preset clock signal is generated according to the repair signal and the initial clock signal.

14. A method for repairing locking, characterized in that: include: Receiving a reset signal, a repair lock signal and a preset clock signal through a clock circuit, and generating a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is in an invalid state; receiving the target clock signal through a latch circuit, and sampling a preset address signal according to the target clock signal when the target clock signal is in a valid state, so that the latch circuit outputs a first address signal; and not performing the sampling process when the target clock signal is in an invalid state, so that the output of the latch circuit is in a latched state; Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

15. A memory, characterized in that: Comprising a repair circuit as claimed in any one of claims 1 to 13.

Images