Fully differential operational amplifier and electronic equipment

Abstract

The invention provides a fully differential operational amplifier and electronic equipment. The fully differential operational amplifier comprises a fully differential ClassAB output stage, a cascode structure, a floating current source, a zero-pole compensation circuit, a compensation zeroing circuit and an error amplifier, the output stage, the cascode structure and the floating current source are connected in pairs; the zero pole compensation circuit is connected with the output stage and the cascode structure; the error amplifier is respectively connected with the cascode structure and the zero pole compensation circuit; the compensation zeroing circuit is connected with the output stage; the error amplifier is connected with a common-mode reference level; two ports of the cascode structure are used as differential signal input ends; and two ports of the output stage are used as differential signal output ends. The common-mode feedback scheme is simple, few in loop, small in power consumption, small in area, easy to implement, free of influence on a differential-mode loop, good in common-mode stability, good in common-mode response speed and precision and good in circuit performance.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a fully differential operational amplifier and electronic equipment. Background Art

[0002] With the advancement of CMOS process technology, reducing the power consumption of circuit systems has become one of the main directions of chip design research. The fully differential class AB amplifier can achieve high dynamic current and output swing at low static current, thus having higher performance, and therefore has attracted the attention of many chip front-end designers.

[0003] Full differential has many advantages, such as suppressing even harmonics and increasing output swing, but for high-gain amplifiers with fully differential structures, the current mismatch between the two differential paths will inevitably cause the output voltage to deviate to the power supply or ground terminal, completely destroying the static operating point of the op amp. Therefore, differential op amps need a common-mode feedback loop to stabilize the common-mode level of their outputs so that the output of the op amp has the best swing range. Therefore, the stability and response speed of the common-mode feedback loop are crucial to fully differential op amps.

[0004] Because of the high gain of high-gain fully differential operational amplifiers, there are usually two ways to achieve the desired common-mode level: the first is to make a common-mode feedback loop at each stage to ensure that its common-mode level is normal, but this method requires multiple common-mode loops and error amplifiers, which consumes a lot of power and has more loops, which can easily affect the stability of other differential-mode loops; the second is to reduce the gain of the common-mode feedback loop, bring the main pole closer to the origin, and make the common-mode loop have a relatively good phase margin, but this method sacrifices the loop gain, gain-bandwidth product GBW, and common-mode level offset (deviation caused by the difference between the two input ends), thereby reducing the speed and accuracy of the common-mode loop. Summary of the invention

[0005] The purpose of the present application is to provide a fully differential operational amplifier and electronic equipment, which have a simple common-mode feedback scheme, fewer loops, low power consumption, small area, easy implementation, and no impact on the differential-mode loop; while maintaining good differential-mode performance, it also has good common-mode stability and good common-mode response speed and accuracy, thereby ensuring that the static operating point of the circuit is normal and the circuit performance is excellent.

[0006] In the first aspect, the present application provides a fully differential operational amplifier, which includes: a fully differential ClassAB output stage composed of first to fourth transistors, a cascode structure composed of fifth to eighth transistors, a floating current source composed of ninth to twelfth transistors and a first current source and a second current source, a zero-pole compensation circuit, a compensation zero adjustment circuit, and an error amplifier composed of thirteenth to sixteenth transistors and a third current source; the fully differential ClassAB output stage, the cascode structure, and the floating current source are connected in pairs; the zero-pole compensation circuit is connected to the fully differential ClassAB output stage and the cascode structure; the error amplifier is respectively connected to the cascode structure and the zero-pole compensation circuit; the compensation zero adjustment circuit is connected to the fully differential ClassAB output stage; the error amplifier is connected to the common mode reference level; the two ports of the cascode structure serve as differential signal input terminals; and the two ports of the fully differential ClassAB output stage serve as differential signal output terminals.

[0007] Furthermore, in the above-mentioned fully differential ClassAB output stage, the sources of the first transistor and the third transistor are both connected to the high level end; the gates of the first transistor and the third transistor are respectively connected to the cascode structure, the floating current source and the compensation zero adjustment circuit; the drain of the first transistor is respectively connected to the drain of the second transistor and the compensation zero adjustment circuit, and serves as the first differential signal output end; the drain of the third transistor is connected to the drain of the fourth transistor and the compensation zero adjustment circuit, and serves as the second differential signal output end; the sources of the second transistor and the fourth transistor are both grounded; and the gates of the second transistor and the fourth transistor are both connected to the floating current source.

[0008] Furthermore, in the above-mentioned cascode structure, the sources of the fifth transistor and the sixth transistor are both connected to the high level end; the gates of the fifth transistor and the sixth transistor are both connected to the zero-pole compensation circuit and the error amplifier; the drain of the sixth transistor is connected to the source of the eighth transistor and serves as the first differential signal input end; the drain of the fifth transistor is connected to the source of the seventh transistor and serves as the second differential signal input end; the gates of the seventh transistor and the eighth transistor are both connected to the first bias voltage; the drain of the seventh transistor is respectively connected to the gate of the first transistor, the compensation zero adjustment circuit and the floating current source; the drain of the eighth transistor is respectively connected to the gate of the third transistor, the compensation zero adjustment circuit and the floating current source.

[0009] Furthermore, the above-mentioned zero-pole compensation circuit includes: a first compensation circuit and a second compensation circuit; the first compensation circuit is connected to the cascode structure; and the second compensation circuit is connected to the fully differential ClassAB output stage and the error amplifier.

[0010] Furthermore, the above-mentioned first compensation circuit includes: a first capacitor, a first resistor, and a sixth resistor; one end of the first capacitor, one end of the first resistor, and one end of the sixth resistor are connected in pairs; the other end of the first capacitor is connected to the gates of the fifth transistor and the sixth transistor in the cascode structure; the other end of the first resistor is connected to the drain of the sixth transistor and the source of the eighth transistor; the other end of the sixth resistor is connected to the drain of the fifth transistor and the source of the seventh transistor.

[0011] Furthermore, the above-mentioned second compensation circuit includes: a second capacitor, a third capacitor, a second resistor and a third resistor; one end of the second capacitor, one end of the third capacitor, one end of the second resistor and one end of the third resistor are all connected to the error amplifier; the other end of the second capacitor and the other end of the second resistor are both connected to the drain of the first transistor in the fully differential ClassAB output stage; the other end of the third capacitor and the other end of the third resistor are both connected to the drain of the third transistor.

[0012] Furthermore, the above-mentioned compensation zero adjustment circuit includes: a fourth resistor, a fifth resistor, a fourth capacitor and a fifth capacitor; one end of the fourth resistor is connected to the gate of the first transistor, and the other end is connected to one end of the fourth capacitor; the other end of the fourth capacitor is connected to the drain of the first transistor; one end of the fifth resistor is connected to the gate of the third transistor, and the other end is connected to one end of the fifth capacitor; the other end of the fifth capacitor is connected to the drain of the third transistor.

[0013] Furthermore, in the above-mentioned floating current source, the gates of the ninth transistor and the tenth transistor are both connected to the second bias voltage; the source of the ninth transistor is respectively connected to the drains of the seventh transistor and the eleventh transistor; the source of the tenth transistor is respectively connected to the drains of the eighth transistor and the twelfth transistor; the drain of the ninth transistor is respectively connected to the source of the eleventh transistor, the negative electrode of the first current source, and the gate of the second transistor; the drain of the tenth transistor is respectively connected to the source of the twelfth transistor, the negative electrode of the second current source, and the gate of the fourth transistor; the positive electrodes of the first current source and the second current source are both grounded; and the gates of the eleventh transistor and the twelfth transistor are both connected to the third bias voltage.

[0014] Furthermore, in the above-mentioned error amplifier, the sources of the thirteenth transistor and the fourteenth transistor are both connected to the high level end; the gates of the thirteenth transistor and the fourteenth transistor are both connected to the drain of the fourteenth transistor; the drain of the thirteenth transistor is connected to the drain of the fifteenth transistor; the drain of the fourteenth transistor is connected to the drain of the sixteenth transistor; the gate of the fifteenth transistor is connected to the common connection point of the second capacitor, the third capacitor, the second resistor and the third resistor in the second compensation circuit; the gate of the sixteenth transistor is connected to the common mode reference level; the sources of the fifteenth transistor and the sixteenth transistor are both connected to the negative electrode of the third current source; and the positive electrode of the third current source is grounded.

[0015] In a second aspect, the present application further provides an electronic device, the electronic device comprising the fully differential operational amplifier as described in the first aspect.

[0016] In the fully differential operational amplifier and electronic device provided by the present application, the fully differential operational amplifier includes: a fully differential ClassAB output stage composed of first to fourth transistors, a cascode structure composed of fifth to eighth transistors, a floating current source composed of ninth to twelfth transistors and a first current source and a second current source, a zero-pole compensation circuit, a compensation zero adjustment circuit, and an error amplifier composed of thirteenth to sixteenth transistors and a third current source; the fully differential ClassAB output stage, the cascode structure, and the floating current source are connected in pairs; the zero-pole compensation circuit is connected to the fully differential ClassAB output stage and the cascode structure; the error amplifier is respectively connected to the cascode structure and the zero-pole compensation circuit; the compensation zero adjustment circuit is connected to the fully differential ClassAB output stage; the error amplifier is connected to the common mode reference level; the two ports of the cascode structure are used as differential signal input terminals; and the two ports of the fully differential ClassAB output stage are used as differential signal output terminals. The common-mode feedback scheme is simple, has few loops, low power consumption, small area, is easy to implement, and does not affect the differential-mode loop; while maintaining good differential-mode performance, it also has good common-mode stability and good common-mode response speed and accuracy, thereby ensuring that the static operating point of the circuit is normal and the circuit performance is excellent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A structural block diagram of a fully differential operational amplifier provided in an embodiment of the present application;

[0019] Figure 2 A circuit diagram of a fully differential operational amplifier provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] In existing fully differential operational amplifiers, either multiple common-mode loops and error amplifiers are required, which consumes large power and has many loops, which easily affects the stability of other differential-mode loops; or the speed and accuracy of the common-mode loop are reduced at the expense of the gain and GBW of the loop and the offset of the common-mode reference level. Based on this, the embodiments of the present application provide a fully differential operational amplifier and electronic device, which has a simple common-mode feedback scheme, few loops, low power consumption, small area, easy implementation, and does not affect the differential-mode loop; while maintaining good differential-mode performance, it also has good common-mode stability and good common-mode response speed and accuracy, thereby ensuring that the static operating point of the circuit is normal and the circuit performance is excellent.

[0023] To facilitate understanding of this embodiment, a fully differential operational amplifier disclosed in the embodiment of the present application is first introduced in detail.

[0024] Figure 1 A fully differential operational amplifier is provided in an embodiment of the present application, and the fully differential operational amplifier includes: a fully differential ClassAB output stage 11 composed of first to fourth transistors, a cascode structure 12 composed of fifth to eighth transistors, a floating current source 13 composed of ninth to twelfth transistors and a first current source and a second current source, a zero-pole compensation circuit 14, a compensation zero adjustment circuit 15, and an error amplifier 16 composed of thirteenth to sixteenth transistors and a third current source.

[0025] Among them, the fully differential ClassAB output stage 11, the cascode structure 12 and the floating current source 13 are connected in pairs; the zero-pole compensation circuit 14 is connected to the fully differential ClassAB output stage 11 and the cascode structure 12; the error amplifier 16 is connected to the cascode structure 12 and the zero-pole compensation circuit 14 respectively; the compensation zero adjustment circuit 15 is connected to the fully differential ClassAB output stage 11; the error amplifier 16 is connected to the common mode reference level; the two ports of the cascode structure 12 are used as differential signal input terminals; and the two ports of the fully differential ClassAB output stage 11 are used as differential signal output terminals.

[0026] The embodiment of the present application provides a fully differential operational amplifier, which uses a common-mode feedback loop to achieve the stability of the common-mode reference level through a new common-mode feedback loop solution and a zero-pole compensation method, and has extremely low power consumption and good common-mode response speed and accuracy. This solution has no effect on the differential-mode loop of the operational amplifier, so that the fully differential operational amplifier has low power consumption and high performance while also having good common-mode response.

[0027] See also Figure 2 As shown, in the above-mentioned fully differential ClassAB output stage 11, the sources of the first transistor M1 and the third transistor M2 are both connected to the high level terminal VDD; the gate of the first transistor M1 (i.e., point B) and the gate of the third transistor M3 (i.e., point C) are respectively connected to the cascode structure 12, the floating current source 13 and the compensation zero adjustment circuit 15; the drain of the first transistor M1 is respectively connected to the drain of the second transistor M2 and the compensation zero adjustment circuit 15, and serves as the first differential signal output terminal VOP; the drain of the third transistor M3 is connected to the drain of the fourth transistor M4, the compensation zero adjustment circuit 15, and serves as the second differential signal output terminal VON; the sources of the second transistor M2 and the fourth transistor M4 are both grounded; and the gates of the second transistor M2 and the fourth transistor M4 are both connected to the floating current source 13.

[0028] Furthermore, in the above-mentioned cascode structure 12, the sources of the fifth transistor M5 and the sixth transistor M6 are both connected to the high level terminal VDD; the gates of the fifth transistor M5 and the sixth transistor M6 (i.e., point A) are both connected to the zero-pole compensation circuit 14 and the error amplifier 16; the drain of the sixth transistor M6 is connected to the source of the eighth transistor M8 and serves as the first differential signal input terminal Iin+; the drain of the fifth transistor M5 is connected to the source of the seventh transistor M7 and serves as the second differential signal input terminal Iin-; the gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the first bias voltage vb1; the drain of the seventh transistor M7 is respectively connected to the gate of the first transistor M1 (i.e., point B), the compensation zero adjustment circuit 15 and the floating current source 13; the drain of the eighth transistor M8 is respectively connected to the gate of the third transistor M3 (i.e., point C), the compensation zero adjustment circuit 15 and the floating current source 13.

[0029] Furthermore, the above-mentioned zero-pole compensation circuit 14 includes: a first compensation circuit 141 and a second compensation circuit 142 ; the first compensation circuit 141 is connected to the cascode structure 12 ; the second compensation circuit 142 is connected to the fully differential ClassAB output stage 11 and the error amplifier 16 .

[0030] Furthermore, the first compensation circuit 141 includes: a first capacitor C1, a first resistor R1, and a sixth resistor R6; one end of the first capacitor C1, one end of the first resistor R1, and one end of the sixth resistor R6 are connected in pairs; the other end of the first capacitor C1 is connected to the gates of the fifth transistor M5 and the sixth transistor M6 in the cascode structure 12; the other end of the first resistor R1 is connected to the drain of the sixth transistor M6 and the source of the eighth transistor M8; the other end of the sixth resistor R6 is connected to the drain of the fifth transistor M5 and the source of the seventh transistor M7.

[0031] Furthermore, the second compensation circuit 142 includes: a second capacitor C2, a third capacitor C3, a second resistor R2 and a third resistor R3; one end of the second capacitor C2, one end of the third capacitor C3, one end of the second resistor R2 and one end of the third resistor R3 are all connected to the error amplifier 16; the other end of the second capacitor C2 and the other end of the second resistor R2 are both connected to the drain of the first transistor M1 in the fully differential ClassAB output stage 11; the other end of the third capacitor C3 and the other end of the third resistor R3 are both connected to the drain of the third transistor M3.

[0032] Furthermore, the above-mentioned compensation zero adjustment circuit 15 includes: a fourth resistor R4, a fifth resistor R5, a fourth capacitor C4 and a fifth capacitor C5; one end of the fourth resistor R4 is connected to the gate of the first transistor M1, and the other end is connected to one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is connected to the drain of the first transistor M1; one end of the fifth resistor R5 is connected to the gate of the third transistor M3, and the other end is connected to one end of the fifth capacitor C5; the other end of the fifth capacitor C5 is connected to the drain of the third transistor M3.

[0033] Further, in the above-mentioned floating current source 13, the gates of the ninth transistor M9 and the tenth transistor M10 are both connected to the second bias voltage vb2; the source of the ninth transistor M9 is respectively connected to the drains of the seventh transistor M7 and the eleventh transistor M11; the source of the tenth transistor M10 is respectively connected to the drains of the eighth transistor M8 and the twelfth transistor M12; the drain of the ninth transistor M9 is respectively connected to the source of the eleventh transistor M11, the negative electrode of the first current source IB1, and the gate of the second transistor IB2; the drain of the tenth transistor M10 is respectively connected to the source of the twelfth transistor M12, the negative electrode of the second current source IB2, and the gate of the fourth transistor M4; the positive electrodes of the first current source IB1 and the second current source IB2 are both grounded; and the gates of the eleventh transistor M11 and the twelfth transistor M12 are both connected to the third bias voltage vb3.

[0034] Further, in the above-mentioned error amplifier 16, the sources of the thirteenth transistor M13 and the fourteenth transistor M14 are both connected to the high level terminal VDD; the gates of the thirteenth transistor M13 and the fourteenth transistor M14 are both connected to the drain of the fourteenth transistor M14; the drain of the thirteenth transistor M13 is connected to the drain of the fifteenth transistor M15; the drain of the fourteenth transistor M14 is connected to the drain of the sixteenth transistor M16; the gate of the fifteenth transistor M15 is connected to the common connection point of the second capacitor C2, the third capacitor C3, the second resistor R2 and the third resistor R3 in the second compensation circuit 142; the gate of the sixteenth transistor M16 is connected to the common mode reference level VREF; the sources of the fifteenth transistor M15 and the sixteenth transistor M16 are both connected to the negative electrode of the third current source IB3; and the positive electrode of the third current source IB3 is grounded.

[0035] In summary, the entire circuit consists of the following parts: a fully differential ClassAB output stage composed of M1-M4, a cascode structure composed of M5-M8 as the load of the first stage of the operational amplifier, a floating current source composed of M9-M12, used to bias the output stage, vb1 is the bias of the cascode tube in the cascode structure, vb2 and vb3 are the bias of the floating current source NMOS and PMOS, vb1, vb2, and vb3 are all provided by external circuits, IB1 and IB2 are the tail current sources of the differential circuit, C1, R0, R1 and C2, C3 , R2, and R3 are zero-pole compensation devices on the common-mode loop, forming a zero-pole compensation circuit; C4, C5 and R4, R5 are Maitreya compensation capacitors and zero adjustment resistors, forming a compensation zero adjustment module, Iin+ and Iin- are differential signal input terminals, generated by the previous stage circuit, and VOP / VON are ClassAB differential signal output terminals; M13-M16 and IB3 form an error amplifier on the common-mode loop, among which M13 and M14 are active load tubes of the error amplifier, M15 and M16 are GM tubes, IB3 is a tail current source, and VREF is a common-mode reference level provided externally.

[0036] Figure 2In the common-mode feedback loop, the common-mode level at the output of the fully differential op amp is obtained through resistors R2 and R3, and then sent to the gate of M15 of the error amplifier. The gate of M16 of the error amplifier is the common-mode reference level VREF (usually VDD / 2) provided externally. The error amplifier sends the error between the common-mode level at the output and the reference level VREF to the gates of M5 and M6 of the cascode structure, and then outputs to the gates of M1 and M3 after a first stage of amplification. After another stage of amplification, it is sent to the output end, and then the common-mode level at the output of the fully differential op amp is detected and returned to the input of the error amplifier (the gate of M15 and M16), forming a common-mode closed loop. This is a negative feedback loop. As long as the gain of the error amplifier is large enough, the common-mode level at the output of the fully differential op amp (the static voltage of node D) will strictly follow VREF. This common-mode loop has a total of three stages of amplification, so it has a higher gain and GBW, but its stability is relatively poor, and an additional zero-pole compensation solution is required.

[0037] Although C4, C5 and R4, R5 can improve the stability of the common-mode loop, they are more sensitive to the differential-mode loop, which will affect the performance of the circuit. Therefore, here, the output node A of the error amplifier and the drain of M5 and M6 of the cascode structure are used C1, R0, R1, and the zero-pole compensation scheme composed of C2 and C3 is used at the output of the fully differential op amp to compensate for the stability of the common-mode loop.

[0038] like Figure 2 As shown, the working principle of the circuit structure of the present invention is as follows: the resistor divider composed of R2 and R3 obtains the common mode level of the differential operational amplifier output, and obtains VCM=(VOP*R2+VON*R3) / (R2+R3). In the design, R2=R3, and is relatively large relative to the output impedance, so VCM=(VOP+VON) / 2. Then VCM and VREF are used as the differential input terminals of the error amplifier, and the output terminal is connected to the cascode structure composed of M5 and M7 and M6 and M8, and then output from the output stage M1 and M3, and the common mode level of the output terminal is returned to the negative input terminal of the error amplifier (the gate of M15).

[0039] The common-mode loop has three stages of amplification, M15 and M16 are the first stage, M5 and M6 are the second stage, and M1 and M3 are the third stage. The larger gain will have a higher GBW and make the output common-mode reference level VCM closer to VREF more accurately, so that the circuit has the best swing range.

[0040] Since its common-mode loop has a high gain, additional zero-pole compensation technology is required to ensure the stability of the common-mode loop. Figure 2Node A is the output terminal of the error amplifier. It is a high-resistance node and will contribute a main pole. Without the first resistor R1 and the first capacitor C1, the pole w p1,A for:

[0041]

[0042] Among them, R A represents the impedance of node A to ground; C A Represents the capacitance of node A to ground; R out,op Represents the output impedance of the error amplifier; C out,op Represents the output capacitance of the error amplifier; C gg5 Represents the gate capacitance of MOS tube M5; Cgg5=Cgs5+Cgd5+Cgb5; C gg6 Represents the gate capacitance of MOS tube M6.

[0043] After adding the first capacitor C1, according to the Maitreya theorem, the capacitance seen from node A increases by (1+A V5 )C1, only a small capacitor needs to be connected in parallel to obtain an amplified (1+A V5 ) times larger capacitor, achieving twice the result with half the effort and avoiding the increase in circuit area caused by large capacitor compensation. V5 is the gain of the second stage amplifier tube M5 (M6) in the common mode loop, A V5 for:

[0044] A V5 =g m5,6 *(g m7,8 r o7,8 *r o5,6 );

[0045] Among them, g m5,6 Indicates the transconductance of MOS tube M5 (or M6); g m7,8 Indicates the transconductance of MOS tube M7 (or M8); r o7,8 Represents the equivalent output resistance of MOS tube M7 (or M8); r o5,6 Indicates the equivalent output resistance of MOS tube M5 (or M6).

[0046] The pole w after adding the first capacitor C1 p1,A ′ becomes:

[0047]

[0048] Among them, p1 represents the first pole, which is the main pole. It can be seen that the frequency of the main pole of the common-mode loop decreases and moves to the low frequency, and the non-main pole will also move to the high frequency, thereby realizing the splitting and separation of the main and secondary poles, effectively improving the phase margin of the common-mode loop and enhancing the stability of the system; since the addition of C1 will produce a zero point in the right half plane, it is also necessary to add resistors R6 and R1 to move the zero point to the left half plane. In addition, there are capacitors C2 and C3 at the output end of the fully differential op amp for compensation. By adjusting the appropriate values ​​of R6, R1, C2, and C3, the secondary pole generated by the output node is offset by the zero point in the circuit, thereby improving the stability of the loop.

[0049] This zero-pole compensation scheme for the fully differential op amp with ClassAB output has almost no effect on the differential mode performance of the circuit, but has a great effect on improving the stability of the common mode loop. This scheme uses fewer devices, and the capacitors C1, C2, and C3 are all small, which will not increase the layout area of ​​the circuit. At the same time, without introducing new zero poles and sacrificing differential mode performance, it achieves good common mode stability and response speed. It is simple, efficient, flexible and practical. Compared with the prior art, the common mode feedback scheme of the fully differential operational amplifier with ClassAB output is simple, with fewer loops, low power consumption, small area, easy to implement, and does not affect the differential mode loop. While maintaining good differential mode performance, it also has good common mode stability and good common mode response speed and accuracy, thereby ensuring that the static operating point of the circuit is normal and the circuit performance is excellent.

[0050] Based on the above amplifier embodiment, the present application embodiment also provides an electronic device, see Figure 3 As shown, the electronic device 32 includes a fully differential operational amplifier 322 as described above.

[0051] The electronic device provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned amplifier embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the electronic device, reference may be made to the corresponding contents in the aforementioned amplifier embodiment.

[0052] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0053] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A fully differential operational amplifier, characterized in that: The fully differential operational amplifier comprises: a fully differential ClassAB output stage composed of first to fourth transistors, a cascode structure composed of fifth to eighth transistors, a floating current source composed of ninth to twelfth transistors and a first current source and a second current source, a zero-pole compensation circuit, a compensation zero adjustment circuit, and an error amplifier composed of thirteenth to sixteenth transistors and a third current source; The fully differential ClassAB output stage, the cascode structure and the floating current source are connected in pairs; the zero-pole compensation circuit is connected to the fully differential ClassAB output stage and the cascode structure; the error amplifier is connected to the cascode structure and the zero-pole compensation circuit respectively; the compensation zero adjustment circuit is connected to the fully differential ClassAB output stage; The error amplifier is connected to a common-mode reference level; the two ports of the cascode structure serve as differential signal input terminals; and the two ports of the fully differential ClassAB output stage serve as differential signal output terminals.

2. The fully differential operational amplifier according to claim 1, wherein: In the fully differential ClassAB output stage, the sources of the first transistor and the third transistor are both connected to the high level end; the gates of the first transistor and the third transistor are respectively connected to the cascode structure, the floating current source and the compensation zero adjustment circuit; the drain of the first transistor is respectively connected to the drain of the second transistor and the compensation zero adjustment circuit, and serves as the first differential signal output end; the drain of the third transistor is connected to the drain of the fourth transistor and the compensation zero adjustment circuit, and serves as the second differential signal output end; the sources of the second transistor and the fourth transistor are both grounded; and the gates of the second transistor and the fourth transistor are both connected to the floating current source.

3. The fully differential operational amplifier according to claim 2, wherein: In the cascode structure, the sources of the fifth transistor and the sixth transistor are both connected to the high level end; the gates of the fifth transistor and the sixth transistor are both connected to the zero-pole compensation circuit and the error amplifier; the drain of the sixth transistor is connected to the source of the eighth transistor and serves as the first differential signal input end; the drain of the fifth transistor is connected to the source of the seventh transistor and serves as the second differential signal input end; the gates of the seventh transistor and the eighth transistor are both connected to the first bias voltage; the drain of the seventh transistor is respectively connected to the gate of the first transistor, the compensation zero adjustment circuit and the floating current source; the drain of the eighth transistor is respectively connected to the gate of the third transistor, the compensation zero adjustment circuit and the floating current source.

4. The fully differential operational amplifier according to claim 3, wherein: The zero-pole compensation circuit includes: a first compensation circuit and a second compensation circuit; the first compensation circuit is connected to the cascode structure; the second compensation circuit is connected to the fully differential ClassAB output stage and the error amplifier.

5. The fully differential operational amplifier according to claim 4, characterized in that: The first compensation circuit includes: a first capacitor, a first resistor, and a sixth resistor; one end of the first capacitor, one end of the first resistor, and one end of the sixth resistor are connected in pairs; the other end of the first capacitor is connected to the gates of the fifth transistor and the sixth transistor in the cascode structure; the other end of the first resistor is connected to the drain of the sixth transistor and the source of the eighth transistor; the other end of the sixth resistor is connected to the drain of the fifth transistor and the source of the seventh transistor.

6. The fully differential operational amplifier according to claim 5, characterized in that: The second compensation circuit includes: a second capacitor, a third capacitor, a second resistor and a third resistor; one end of the second capacitor, one end of the third capacitor, one end of the second resistor and one end of the third resistor are all connected to the error amplifier; the other end of the second capacitor and the other end of the second resistor are both connected to the drain of the first transistor in the fully differential ClassAB output stage; the other end of the third capacitor and the other end of the third resistor are both connected to the drain of the third transistor.

7. The fully differential operational amplifier according to claim 6, wherein: The compensation zero adjustment circuit includes: a fourth resistor, a fifth resistor, a fourth capacitor and a fifth capacitor; one end of the fourth resistor is connected to the gate of the first transistor, and the other end is connected to one end of the fourth capacitor; the other end of the fourth capacitor is connected to the drain of the first transistor; one end of the fifth resistor is connected to the gate of the third transistor, and the other end is connected to one end of the fifth capacitor; the other end of the fifth capacitor is connected to the drain of the third transistor.

8. The fully differential operational amplifier according to claim 7, wherein: In the floating current source, the gates of the ninth transistor and the tenth transistor are both connected to the second bias voltage; the source of the ninth transistor is respectively connected to the drains of the seventh transistor and the eleventh transistor; the source of the tenth transistor is respectively connected to the drains of the eighth transistor and the twelfth transistor; the drain of the ninth transistor is respectively connected to the source of the eleventh transistor, the negative electrode of the first current source, and the gate of the second transistor; the drain of the tenth transistor is respectively connected to the source of the twelfth transistor, the negative electrode of the second current source, and the gate of the fourth transistor; the positive electrodes of the first current source and the second current source are both grounded; and the gates of the eleventh transistor and the twelfth transistor are both connected to the third bias voltage.

9. The fully differential operational amplifier according to claim 8, characterized in that: In the error amplifier, the sources of the thirteenth transistor and the fourteenth transistor are both connected to the high level end; the gates of the thirteenth transistor and the fourteenth transistor are both connected to the drain of the fourteenth transistor; the drain of the thirteenth transistor is connected to the drain of the fifteenth transistor; the drain of the fourteenth transistor is connected to the drain of the sixteenth transistor; the gate of the fifteenth transistor is connected to the common connection point of the second capacitor, the third capacitor, the second resistor and the third resistor in the second compensation circuit; the gate of the sixteenth transistor is connected to the common mode reference level; the sources of the fifteenth transistor and the sixteenth transistor are both connected to the negative electrode of the third current source; and the positive electrode of the third current source is grounded.

10. An electronic device, characterized in that: The electronic device comprises the fully differential operational amplifier as claimed in any one of claims 1 to 9.

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