Multi-channel ultrasonic imaging special integrated circuit suitable for integrated packaging

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a multichannel ultrasonic imaging special integrated circuit suitable for integrated packaging. The application-specific integrated circuit is formed by cascading a plurality of multi-channel single chips, the multi-channel single chips adopt four ultrasonic channel input architectures, and each channel comprises an ultrasonic analog front end, an analog-to-digital converter and an ultrasonic digital signal processing module; the ultrasonic analog front end comprises four sub-modules, namely a low-noise amplifier, a voltage control attenuator, a programmable gain amplifier and an anti-aliasing low-pass filter; the analog-to-digital converter adopts a three-stage successive approximation register pipeline cascade structure to realize 14-bit digital output; the ultrasonic digital signal processing module is used for processing the ultrasonic signals quantized by the ADC, including ADC data preprocessing, data demodulation, signal interpolation and extraction, beam forming, test signal generation and the like; the number of channels is expanded through SIP packaging, and the method can be used for ultrasonic imaging of medical ultrasonic diagnosis and has high flexibility and expandability.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a cascadeable multi-channel ultrasonic imaging special integrated circuit. Background Art

[0002] In modern medical imaging technology, ultrasound imaging has become one of the important tools for clinical diagnosis due to its advantages such as non-invasiveness, real-time and radiation-free. With the continuous improvement of the accuracy and real-time requirements of medical diagnosis, multi-channel ultrasound imaging technology has gradually become a hot spot for research and application. Multi-channel ultrasound imaging can significantly improve the spatial resolution and contrast of imaging, especially in applications with complex tissue structures and fast dynamic scenes.

[0003] Ultrasound imaging systems often require a larger number of channels to achieve better imaging effects. The increase in the number of channels will lead to an increase in the chip size, so the photolithography mask size and manufacturing defects will limit the maximum area of ​​a single chip. Traditional ultrasound imaging systems are usually limited by the number of channels, making it difficult to meet the application requirements of large-scale ultrasound probe arrays, and the delay alignment of signals from different channels is more complicated, which can easily lead to a decrease in imaging quality. Packaging multiple chips in the same lumen can achieve reusability, higher integration, and lower cost. SiP (System in Package) technology is an advanced integrated circuit packaging technology used to integrate multiple functional components in a single package. This technology enables different types of chips to be placed closely together, thereby achieving higher performance and functional integration, while also saving space. Summary of the invention

[0004] The purpose of the present invention is to provide a multi-channel ultrasound imaging dedicated integrated circuit suitable for integrated SiP packaging, which realizes the high sensitivity, high resolution and multi-channel flexible expansion requirements of the ultrasound imaging system by optimizing the analog front-end design and the digital signal processing module.

[0005] The multi-channel ultrasound imaging ASIC suitable for integrated SiP packaging provided by the present invention is composed of a plurality of (M) multi-channel single chips cascaded, wherein the multi-channel single chip includes a plurality of (N) ultrasound channels, specifically adopting a four (N=4) ultrasound channel input architecture, each channel includes an ultrasound analog front end, an analog-to-digital converter (ADC), and an ultrasound digital signal processing module; wherein:

[0006] (1) Ultrasound analog front end, including four sub-modules: low noise amplifier (LNA), voltage controlled attenuator (VCA), programmable gain amplifier (PGA) and anti-aliasing low-pass filter (LPF); among which:

[0007] The low noise amplifier (LNA) adopts a circuit structure with adjustable gain function. The input end of the LNA is connected to the receiving end of the ultrasound probe, which can receive the ultrasonic reflection signal and perform preliminary amplification. In the LNA circuit design, the optimization of the noise coefficient is focused on, so that the input reference noise can be as low as 2.2nV / √Hz. At the same time, by setting the adjustable gain function, the LNA can dynamically adjust the gain according to the strength of the input signal to adapt to different application scenarios;

[0008] Voltage controlled attenuator (VCA), located immediately after LNA, is used to adjust the amplitude of the signal to prevent the subsequent signal processing module from saturating due to excessive input signals. VCA dynamically adjusts the attenuation value by controlling the voltage, thereby avoiding signal distortion in a strong signal environment;

[0009] Programmable Gain Amplifier (PGA), immediately after VCA, PGA amplifies the signal of VCA. The gain of PGA can be controlled by external programming, providing more detailed gain adjustment to optimize the signal-to-noise ratio of the signal. The design of PGA can ensure stable signal amplification in a wide dynamic range.

[0010] Anti-aliasing low-pass filter (LPF), the signal passes through the LPF to filter out high-frequency components before entering the ADC to prevent aliasing. The LPF is designed as an adjustable bandwidth structure, which can dynamically adjust the filter cutoff frequency according to the ADC sampling rate to adapt to different signal bandwidth requirements.

[0011] (2) The analog-to-digital converter (ADC) adopts a three-stage successive approximation register (SAR) pipeline cascade structure to achieve 14-bit digital output; specifically, the analog-to-digital conversion of the signal is realized through a three-stage successive approximation register (SAR) circuit. Each stage of the pipeline independently completes part of the signal quantization and passes the residual to the next stage, and finally completes the 14-bit quantized output of the signal at the third stage. This structural design not only takes into account high precision and high speed, but also has the characteristics of low power consumption, that is, it improves the conversion speed and reduces the accuracy loss caused by single-stage quantization error.

[0012] Each SAR level uses a combination of capacitor arrays and comparators to achieve successive approximation quantization of the input signal, ensuring that each bit of the output has high precision. This design enables the ADC to provide high-resolution digital signal output without sacrificing speed.

[0013] (3) Ultrasonic digital signal processing module, used to process the ultrasonic signal after ADC quantization, including ADC data preprocessing, data demodulation, signal interpolation and extraction, beamforming, and test signal generation submodules; wherein:

[0014] ADC data preprocessing submodule performs preliminary filtering and noise reduction on the digital signal from the ADC to improve the signal quality;

[0015] The data demodulation submodule performs phase demodulation on the received ultrasonic signal to extract key information related to target imaging;

[0016] The signal interpolation and extraction submodule increases the sampling rate of the signal through the interpolation algorithm and performs extraction processing when necessary to meet different image resolution requirements;

[0017] Beamforming submodule: Based on the delay and amplitude information of each channel signal, the beamforming algorithm is executed to generate a more directional ultrasonic beam to improve the contrast and resolution of the image;

[0018] Test signal generation submodule: provides internal test signals for the system to calibrate and verify the functions of each signal processing module.

[0019] In addition, the present invention also includes:

[0020] (4) Weighted summation module: The channel signals of each ultrasonic transducer array are weighted differently according to their spatial positions and the relative positions of the imaging targets. These weights are used to adjust the amplitude and phase of each channel signal to ensure that they can be focused on a specific target area after synthesis, thereby improving the resolution and contrast of the imaging. Specifically, after the analog-to-digital conversion of each channel signal, the weighted summation module sets a corresponding weight for it, and then sums the weighted signals of all channels to achieve real-time, low-latency beamforming operations to meet the requirements of high-speed ultrasonic imaging.

[0021] In addition, the present invention also includes:

[0022] (5) Cascade chip select module: In the multi-chip cascade, the chip select control of each chip is realized to ensure the effective transmission and processing of each channel signal. Each chip can independently process a certain number of ultrasonic transducer channel signals. Multiple chips are cascaded in a serial manner, and the cascaded chips jointly complete the signal processing task of the entire ultrasonic array. After each chip processes the weighted sum signal of its own channel, it passes the sum result to the next level chip for further operation according to the predetermined synchronization mechanism.

[0023] In addition, the present invention also includes:

[0024] (6) Signal delay alignment module:

[0025] In a multi-channel ultrasound imaging system, signal delay alignment is the key to ensure the synchronization of signals in each channel, especially when beamforming is performed. The difference in signal delay between channels will directly affect the imaging quality. Since the physical position of each ultrasound transducer array is different, the arrival time of the collected echo signals will also be different. The delay alignment technology must be used to correct the delay difference between these channels to ensure the accuracy and clarity of the imaging results.

[0026] Signal delay alignment is an important technical guarantee to ensure the synchronization of signals in each channel. Through the dual mechanisms of fractional cycle and integer cycle delay alignment, the present invention successfully solves the time synchronization problem in multi-channel ultrasonic signal processing and ensures that signals from different channels maintain temporal consistency when entering beamforming processing.

[0027] The present invention designs a solution combining fractional cycle delay and integer cycle delay, which is as follows:

[0028] (1) Fractional cycle delay, which is implemented by a 64th-order finite impulse response (FIR) filter. The FIR filter makes a small time offset adjustment to the input signal to correct the sub-cycle delay difference between channels. The order and coefficients of the FIR filter can be optimized according to the specific application scenario to ensure the correction accuracy is within the nanosecond range.

[0029] (2) Integer cycle delay: Specifically, static random access memory (SRAM) is configured as an asynchronous first-in first-out (FIFO) buffer to achieve integer cycle delay of channel signals. The SRAM FIFO dynamically adjusts the FIFO depth according to the delay requirements of each channel, thereby compensating for the integer cycle delay caused by the difference in physical channel length.

[0030] By combining fractional cycle delay and integer cycle delay, the present invention can effectively achieve accurate alignment of signals of each channel and ensure the synchronization and consistency of the final imaging signal.

[0031] Furthermore, the signal delay alignment function is further optimized by:

[0032] (1) When performing delay alignment, first perform a preliminary analysis of the signals of each channel and calculate the relative delay of each channel relative to the reference channel;

[0033] (2) The fractional cycle delay of each channel signal is precisely adjusted through a 64-order FIR filter to eliminate the relative time deviation at the 1 / 4 cycle level caused by differences in transmission paths and component characteristics;

[0034] (3) After completing the fractional cycle delay correction, use SRAM as an asynchronous FIFO to perform integer cycle delay adjustment on the signal that needs further compensation, ensuring that the signal of each channel can enter the next processing stage within the appropriate time window;

[0035] (4) Through the combination of the above-mentioned fractional cycle and integer cycle delays, complete synchronization of signals between channels is achieved, ensuring the phase consistency of the final output signal, thereby optimizing the clarity and resolution of the ultrasound image.

[0036] In the present invention, these submodules give each channel excellent signal processing capabilities. In order to meet the needs of multi-channel applications, the integrated circuit of the present invention adopts a chip cascade architecture, so that multiple chips can be used in series, thereby realizing flexible expansion of the number of channels. Through this cascade mode, the number of channels of the ultrasound probe can be dynamically adjusted as needed, supporting ultrasound array configurations from small to large scales, which can greatly improve the versatility and scalability of the system. In addition, the cascade architecture also ensures the synchronization and consistency of the signals of each channel, eliminates the performance bottleneck caused by the limitation of the number of channels in the traditional system, and provides a more flexible and efficient solution.

[0037] In the present invention, the low noise amplifier (LNA) design pays special attention to the adjustability of gain and the reduction of input reference noise. Test results show that the input reference noise of the LNA is as low as 2.2nV / √Hz, which greatly improves the signal quality while reducing noise interference, providing higher accuracy guarantee for signal processing and analysis of ultrasound images.

[0038] In the present invention, a three-stage SAR ADC pipeline cascade structure is adopted to achieve 14-bit high-precision digital output. This design ensures the accuracy of signal conversion, helps to obtain high-resolution data during the imaging process, and thus generates clearer images.

[0039] In the present invention, in order to ensure accurate synchronization of multi-channel ultrasound signals in the final imaging process, the present invention designs an innovative signal delay alignment function, which eliminates the delay inconsistency problem caused by transmission path differences by performing fine time correction on the signal of each channel.

[0040] In the present invention, the ultrasonic digital signal processing module can realize functions including ADC data preprocessing, data demodulation, signal interpolation and extraction, beamforming, test signal generation, and cascade chip selection. The integration of these functions optimizes the overall performance of the system and improves the quality and efficiency of ultrasonic imaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The diagram is a multi-chip cascade diagram of a multi-channel ultrasound imaging ASIC suitable for integrated packaging according to the present invention.

[0042] Figure 2 The analog chip module of the multi-channel ultrasound imaging ASIC suitable for integrated packaging of the present invention is shown in FIG. Figure 1 The two modules marked with number 2 are the ultrasound analog front end (AFE) and the 14-bit analog-to-digital converter (ADC).

[0043] Figure 3 The digital chip module of the multi-channel ultrasound imaging ASIC suitable for integrated packaging of the present invention is shown in FIG. Figure 1 The digital signal processing part 4 and the weighted summation module 6 are included.

[0044] The numbers in the figure are: 1 is the raw data input of each ultrasound channel, 2 is the ultrasound analog front end (AFE), 3 is the 14-bit analog-to-digital converter (ADC), 4 is the digital signal processing part, 5 is the single-channel signal processing part, 6 is the weighted summation module, 7 is the cascade summation module, 8 is the multi-channel single chip, 9 is the output signal after single-chip processing, 10 is the output signal after multi-chip cascade summation, 11 is the low noise amplifier (LNA), 12 is the voltage controlled attenuator (VCA), 13 is the programmable gain amplifier (PGA), 14 is the anti-aliasing low-pass filter (LPF) , 15 is a 14-bit analog-to-digital converter (ADC), 16 is the input signal after analog chip processing, 17 is a first-in first-out data module (FIFO), 18 is an ADC data preprocessing module, 19 is a test signal generating module, 20 is a data multiplexer (MUX), 21 is a fractional cycle delay generating module, 22 is an integer delay generating module, 23 is a weighted summing module, 24 is a serial device interface module (SPI), 25 is a demodulation signal output I, 26 is a demodulation signal output Q, 27 is a digital demodulation module, and 28 is an analog front end and analog-to-digital converter control signal. DETAILED DESCRIPTION

[0045] The present invention provides a multi-channel ultrasonic imaging application-specific integrated circuit suitable for integrated SiP packaging, see Figure 1 As shown, it includes an ultrasound analog front end, an analog-to-digital converter and a digital signal processing module to achieve high sensitivity, high resolution and flexible expansion capabilities of multiple channels. The specific implementation of the present invention will be described in detail below.

[0046] Assume CH1, CH2, ..., CHN are ultrasound channels, and the original input data 1 of each ultrasound channel is processed in sequence by an ultrasound analog front end (AFE) 2, a 14-bit analog-to-digital converter (ADC) 3, and a digital signal processing part 4; the outputs of all ultrasound channels CH1, CH2, ..., CHN enter a weighted summing module 6; this part constitutes a multi-channel single chip 8;

[0047] The entire ASIC is composed of M multi-channel single chips 8 cascaded together; the output signals 9 of the M multi-channel single chips 8 enter the cascade summing module 7, and the output is a signal 10 after the multi-chip cascade summation;

[0048] The analog chip of the integrated packaged multi-channel ultrasound imaging ASIC of the present invention is shown in Figure 2 The analog chip corresponds to the ultrasound analog front end (AFE) 2 and the 14-bit analog-to-digital converter (ADC) 4. Specifically, it includes a low noise amplifier (LNA) 11, a voltage controlled attenuator (VCA) 12, a programmable gain amplifier (PGA) 13, an anti-aliasing low-pass filter (LPF) 14, and a 14-bit analog-to-digital converter (ADC) 15 connected in sequence;

[0049] The digital chip of the integrated packaged multi-channel ultrasound imaging ASIC of the present invention is shown in FIG. Figure 3 The digital chip corresponds to the digital signal processing part 4 and the weighted summation module 6. Specifically, it includes: a first-in first-out data module (FIFO) 17, an ADC data preprocessing module 18, a test signal generating module 19, a data multiplexer (MUX) 20, a fractional cycle delay generating module 21, an integer delay generating module 22, a weighted summation module 23, a serial device interface module (SPI) 24, and a digital demodulation module 27;

[0050] The data flow process of the digital chip is as follows: the input signal 16 processed by the analog chip passes through the first-in first-out data module (FIFO) 17 for cross-clock domain processing and data buffering, the ADC data preprocessing module 18 processes the output data of module 17 to obtain the ideal binary code value, and the data multiplexer (MUX) 20 selects the next level input as the module 19 to generate the test signal or the measured data signal generated by module 18. After selection, the following operation modules are performed in sequence: module 21 performs the fractional cycle delay operation, module 22 performs the integer cycle delay operation, module 23 performs the weighted summation operation, and module 27 performs the down-conversion operation to finally output two orthogonal demodulated signals 25 and 26. In addition, the serial device interface module (SPI) 24 controls the parameter configuration of the above modules as a control signal and outputs the analog chip control signal 28.

[0051] In order to verify the performance of the circuit of the present invention, an ultrasonic imaging test platform was designed and manufactured, and a comparative test was conducted with common ultrasonic imaging chips on the market. The following is an analysis of the key data in the test.

[0052] 1. Noise performance test: The low noise amplifier (LNA) of the present invention has been tested and its input reference noise is 2.2nV / √Hz, which is about 20% lower than the noise level of conventional commercial ultrasound imaging chips. This greatly improves the signal-to-noise ratio in imaging, allowing weak signals to be clearly captured.

[0053] 2. Gain and dynamic range test: The analog front end achieves a gain dynamic range of more than 80dB, and can flexibly adjust the gain to adapt to imaging targets at different depths in ultrasound imaging. Compared with traditional chips, the present invention has better signal capture capabilities when imaging deeper tissues.

[0054] 3. Delay alignment and beamforming effect: Through the optimization of the signal delay alignment mechanism, the delay compensation accuracy reaches the sub-nanosecond level (a 64-order FIR filter is used for fractional cycle delay), ensuring the phase alignment of multi-channel signals in beamforming. The imaging results show that the beam focusing effect is significant. Compared with the imaging results of traditional chips, the present invention achieves higher image resolution and contrast.

[0055] The advantages and advancement of the circuit of the present invention are:

[0056] 1. Multi-channel scalability: This invention solves the problem of limited number of channels in ultrasound imaging systems through chip cascade architecture, and can support expansion from a few channels to hundreds of channels to meet imaging requirements of different scales and resolutions. This flexibility makes this technology suitable not only for portable ultrasound equipment, but also for high-end medical imaging systems.

[0057] 2. High precision and low noise: Through optimized analog front-end design, the present invention achieves high gain and wide dynamic range while maintaining low noise, ensuring the imaging quality of deep tissues. The input reference noise of its LNA is 2.2nV / √Hz, which is significantly better than existing commercial chips.

[0058] 3. Accuracy of signal delay alignment: The present invention achieves high-precision delay compensation by combining fractional and integer cycle delays, ensuring the phase consistency of each channel in beamforming. This design directly improves imaging resolution, especially in complex scenes, and can better present subtle tissue structures.

[0059] In summary, the present invention realizes a high-performance integrated circuit for a multi-channel ultrasound imaging system by optimizing the design of analog front end, analog-to-digital conversion, signal delay alignment, and digital signal processing. The circuit has high flexibility and scalability, is suitable for various ultrasound imaging application scenarios, and can effectively improve the resolution and sensitivity of ultrasound imaging.

Claims

1. A multi-channel ultrasound imaging ASIC suitable for integrated packaging, characterized in that: It is composed of a plurality of multi-channel single chips cascaded together, wherein the multi-channel single chip adopts a four-ultrasound channel input architecture, and each channel includes an ultrasonic analog front end, an analog-to-digital converter (ADC), and an ultrasonic digital signal processing module; wherein: (1) Ultrasound analog front end, including four sub-modules: low noise amplifier (LNA), voltage controlled attenuator (VCA), programmable gain amplifier (PGA) and anti-aliasing low-pass filter (LPF); among which: The low noise amplifier (LNA) adopts a circuit structure with adjustable gain function. The input end of the LNA is connected to the receiving end of the ultrasound probe to receive the ultrasonic reflection signal and perform preliminary amplification. In the LNA design, the focus is on optimizing the noise coefficient to minimize the input reference noise to 2.2nV / √Hz. At the same time, by setting the adjustable gain function, the LNA dynamically adjusts the gain according to the strength of the input signal to adapt to different application scenarios. Voltage controlled attenuator (VCA), located immediately after the LNA, is used to adjust the amplitude of the signal to prevent the subsequent signal processing module from being saturated due to excessive input signals. The VCA dynamically adjusts the attenuation value by controlling the voltage, thereby avoiding signal distortion in a strong signal environment. Programmable Gain Amplifier (PGA), which follows the VCA, amplifies the signal from the VCA. The gain of the PGA is controlled by external programming, providing more detailed gain adjustment to optimize the signal-to-noise ratio. The design of the PGA ensures stable signal amplification over a wide dynamic range. Anti-aliasing low-pass filter (LPF), the signal passes through the LPF to filter out high-frequency components before entering the ADC to prevent aliasing; the LPF is designed as an adjustable bandwidth structure, which can dynamically adjust the filter cutoff frequency according to the ADC sampling rate to adapt to different signal bandwidth requirements; (2) Analog-to-digital converter, which adopts a three-stage successive approximation register (SAR) pipeline cascade structure to achieve 14-bit digital output; specifically, the analog-to-digital conversion of the signal is achieved through a three-stage successive approximation register (SAR) circuit, each stage of the pipeline independently completes partial quantization of the signal and passes the residual to the next stage, and finally completes the 14-bit quantization output of the signal in the third stage; Each level of SAR uses a combination of capacitor array and comparator to achieve successive approximation quantization of the input signal, ensuring that each bit of the output has high precision. (3) Ultrasonic digital signal processing module, used to process the ultrasonic signal after ADC quantization, including ADC data preprocessing, data demodulation, signal interpolation and extraction, beamforming, test signal generation and cascade chip selection function submodules; wherein: ADC data preprocessing submodule performs preliminary filtering and noise reduction on the digital signal from the ADC to improve the signal quality; The data demodulation submodule performs phase demodulation on the received ultrasonic signal to extract key information related to target imaging; The signal interpolation and extraction submodule increases the sampling rate of the signal through the interpolation algorithm and performs extraction processing when necessary to meet different image resolution requirements; Beamforming submodule: Based on the delay and amplitude information of each channel signal, the beamforming algorithm is executed to generate a more directional ultrasonic beam to improve the contrast and resolution of the image; Test signal generation submodule: provides internal test signals for the system to calibrate and verify the functions of each signal processing module; Cascade chip select submodule: In multi-chip cascade applications, it realizes chip select control of each chip to ensure effective transmission and processing of each channel signal.

2. The multi-channel ultrasound imaging ASIC according to claim 1, characterized in that: It also includes a weighted summation module, which is used to set different weights for the channel signals of each ultrasonic transducer array according to their spatial positions and the relative positions of the imaging targets; these weights are used to adjust the amplitude and phase of each channel signal to ensure that they can be focused on a specific target area after synthesis, thereby improving the resolution and contrast of imaging; specifically, after the signal of each channel is converted into a digital form, the weighted summation module sets a corresponding weight for it, and then sums the weighted signals of all channels to achieve real-time, low-latency beamforming operations to meet the requirements of high-speed ultrasonic imaging.

3. The multi-channel ultrasound imaging ASIC according to claim 2, characterized in that: It also includes a cascade chip select module: in the multi-chip cascade, the chip select control of each chip is realized to ensure the effective transmission and processing of each channel signal; since each chip independently processes a certain number of ultrasonic transducer channel signals, multiple chips are cascaded in a serial manner, and the cascaded chips jointly complete the signal processing task of the entire ultrasonic array; after each chip processes the weighted sum signal of its own channel, it passes the sum result to the next level chip for further operation according to a predetermined synchronization mechanism.

4. The multi-channel ultrasound imaging ASIC according to claim 3, characterized in that: It also includes a signal delay alignment module, which includes fractional cycle delay and integer cycle delay, as follows: (1) Fractional cycle delay, which is implemented by a 64th-order finite impulse response (FIR) filter. The FIR filter makes a slight time offset adjustment to the input signal to correct the sub-cycle delay difference between channels. The order and coefficients of the FIR filter are optimized according to the specific application scenario to ensure the correction accuracy is within the nanosecond range. (2) Integer cycle delay, specifically, static random access memory (SRAM) is configured as an asynchronous first-in first-out (FIFO) buffer to achieve integer cycle delay of channel signals; the SRAM FIFO dynamically adjusts the FIFO depth according to the delay requirements of each channel, thereby compensating for the integer cycle delay caused by the difference in physical channel length; By combining fractional cycle delay and integer cycle delay, accurate alignment of the signals of each channel can be effectively achieved, ensuring the synchronization and consistency of the final imaging signal.

5. The multi-channel ultrasound imaging ASIC according to claim 4, characterized in that: The signal delay alignment is further optimized by: (1) When performing delay alignment, first perform a preliminary analysis of the signals of each channel and calculate the relative delay of each channel relative to the reference channel; (2) The fractional cycle delay of each channel signal is precisely adjusted through a 64-order FIR filter to eliminate the relative time deviation at the 1 / 4 cycle level caused by differences in transmission paths and component characteristics; (3) After completing the fractional cycle delay correction, use SRAM as an asynchronous FIFO to perform integer cycle delay adjustment on the signal that needs further compensation, ensuring that the signal of each channel can enter the next processing stage within the appropriate time window; (4) Through the combination of the above-mentioned fractional cycle and integer cycle delays, complete synchronization of signals between channels is achieved, ensuring the phase consistency of the final output signal, thereby optimizing the clarity and resolution of the ultrasound image.

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