Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof. The method comprises the following steps: forming a plurality of modified regions in a substrate; performing oxidation treatment on the surfaces of the substrate and the modified region, forming a first oxide layer on the surface of the modified region, and forming a second oxide layer on the surface of the substrate; forming a floating gate layer on the surface of the second oxide layer; forming a plurality of mutually separated control gate structures on the surface of the floating gate layer, wherein the two sides of the first oxide layer are respectively provided with the control gate structures, and the part of the surface of the floating gate layer between the control gate structures and the first oxide layer is exposed; etching the first oxide layer exposed between the control gate structures, and forming an erase gate oxide layer on the surface of the substrate between the floating gate layers; etching and erasing the gate oxide layer and the floating gate layer at two sides of the control gate structure until the surface of the substrate is exposed, and forming a floating gate between the control gate structure and the substrate; according to the method, the technological process is simplified, and the shape of the sharp corner of the floating gate is easy to control.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] With the popularity of electronic products, flash memory has been rapidly promoted as the mainstream storage medium today, and its technology has also been rapidly developed. Flash memory is divided into NOT OR (NOR) type flash memory and NOT AND (NAND) type flash memory. As a type of flash memory, NOR type flash memory has received widespread attention due to its efficient programming speed and erasing ability. At present, NOR type flash memory has been widely used in personal computers, digital equipment, mobile terminals, automotive devices and other products.

[0003] For NOR-type flash memory, erasure is performed using the tunneling effect of electric field enhancement between the floating gate and erase gate polysilicon. The sharper the floating gate corner, the higher the local high voltage and the better the erasing capability. As the performance requirements for NOR-type flash memory applications increase, the memory is required to have more efficient erasing capabilities.

[0004] However, there are still many problems in the process of forming a NOR-type flash memory structure in the current technology. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the performance of the memory structure.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of modified regions in the substrate; performing oxidation treatment on the surfaces of the substrate and the modified regions, wherein the oxidation rate of the modified regions is higher than the oxidation rate of the substrate surface, forming a first oxide layer on the surface of the modified regions, and forming a second oxide layer on the surface of the substrate, wherein the surface of the first oxide layer is higher than the surface of the second oxide layer, and the sidewall of the first oxide layer is protruding; forming a floating gate layer on the surface of the second oxide layer, wherein the floating gate layer exposes the top surface of the first oxide layer, and the floating gate layer is The side wall surface in contact with the first oxide layer is recessed; a plurality of control gate structures separated from each other are formed on the surface of the floating gate layer, the control gate structures are respectively provided on both sides of the first oxide layer, and a portion of the floating gate layer surface between the control gate structure and the first oxide layer is exposed; the first oxide layer exposed between the control gate structures is etched to form an erase gate oxide layer on the substrate surface between the floating gate layers; the erase gate oxide layer and the floating gate layers on both sides of the control gate structure are etched until the substrate surface is exposed to form a floating gate between the control gate structure and the substrate; an erase gate located between adjacent control gate structures is formed on the erase gate oxide layer.

[0007] Optionally, the method for forming the modified zone includes: forming a first mask layer on the surface of the substrate, the first mask layer exposing a portion of the surface of the substrate; and performing a modification process on the substrate exposed by the first mask layer to form a plurality of the modified zones located in the substrate.

[0008] Optionally, the modification process is ion implantation.

[0009] Optionally, the parameters of the ion implantation process include: an ion implantation energy of 30 keV to 50 keV; an ion implantation dose of 2E15 ions / cm 2 ~3E15 ions / cm 2 .

[0010] Optionally, the material of the modified zone is amorphous.

[0011] Optionally, the surface of the first oxide layer is higher than the surface of the second oxide layer by

[0012] Optionally, the size range of the recess on the sidewall of the floating gate layer is

[0013] Optionally, the distance between the control gate structure and the first oxide layer along a direction parallel to the substrate ranges from

[0014] Optionally, the method for forming the floating gate layer includes: forming an initial floating gate layer on the surface of the second oxide layer; and performing a planarization process on the initial floating gate layer to form a floating gate layer located on the surface of the second oxide layer.

[0015] Optionally, the method for forming the floating gate layer further includes: forming a buffer layer on the surface of the initial floating gate layer before the planarization process; and performing the planarization process on the buffer layer before performing the planarization process on the initial floating gate layer.

[0016] Optionally, the material of the buffer layer includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0017] Optionally, the control gate structure includes: a control gate dielectric layer and a control gate layer located on a surface of the control gate dielectric layer.

[0018] Optionally, the control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on a surface of the first silicon oxide layer, and a second silicon oxide layer located on a surface of the silicon nitride layer.

[0019] Optionally, the method for forming the control gate structure includes: forming a control gate structure layer on the surface of the floating gate layer; forming a second mask layer on the surface of the control gate structure layer, the second mask layer exposing a portion of the surface of the control gate structure layer; etching the control gate structure layer using the second mask layer as a mask until the surface of the floating gate layer is exposed, thereby forming a plurality of discrete control gate structures.

[0020] Optionally, the second mask layer is a single-layer structure or a multi-layer structure; the multi-layer structure includes one or more overlapping layers of a silicon oxide layer and a silicon nitride layer.

[0021] Optionally, the method for etching the erase gate oxide layer and the floating gate layer on both sides of the control gate structure to form the floating gate includes: forming a third mask layer on the erase gate oxide layer and the surface of the control gate structure, the third mask layer exposing the erase gate oxide layer and the surface of the floating gate layer on both sides of the control gate structure; using the third mask layer as a mask, etching the floating gate layer until the substrate surface is exposed to form the floating gate.

[0022] Correspondingly, the technical solution of the present invention also provides a memory structure, including: a substrate; a plurality of modified regions located in the substrate; a first oxide layer located on the surface of the modified region, the sidewalls of the first oxide layer protruding; a second oxide layer located on the surface of the substrate, the surface of the second oxide layer being lower than the surface of the first oxide layer; a floating gate located on the surface of the second oxide layer, the floating gate exposing a portion of the second oxide layer surface and the top surface of the first oxide layer, and the sidewall surface of the floating gate in contact with the first oxide layer is recessed; a plurality of separate control gate structures located on the surface of the floating gate, the control gate structures being located on both sides of the first oxide layer, and a portion of the floating gate surface between the control gate structure and the first oxide layer is exposed; and an erase gate located between adjacent control gate structures.

[0023] Optionally, the material of the modified zone is amorphous.

[0024] Optionally, the surface of the first oxide layer is higher than the surface of the second oxide layer by

[0025] Optionally, the size range of the floating gate sidewall recess is

[0026] Optionally, the distance between the control gate structure and the first oxide layer along the direction parallel to the substrate ranges from

[0027] Optionally, the control gate structure includes: a control gate dielectric layer and a control gate layer located on a surface of the control gate dielectric layer.

[0028] Optionally, the control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on a surface of the first silicon oxide layer, and a second silicon oxide layer located on a surface of the silicon nitride layer.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the memory structure of the technical solution of the present invention, the floating gate is located on the surface of the second oxide layer, and the floating gate exposes the top surface of the first oxide layer. Therefore, the floating gate has a sharp corner, which makes it easier to form a tip electric field, thereby increasing the local electric field strength, thereby increasing the tunneling probability and improving the erasure efficiency.

[0031] In the method for forming a memory structure of the technical solution of the present invention, first, a plurality of modified areas are formed in a substrate and the substrate and the modified areas are oxidized. Since the oxidation rate of the surface of the modified area by the oxidation treatment is higher than the oxidation rate of the surface of the substrate, the surface of the first oxide layer is higher than the surface of the second oxide layer. Therefore, the floating gate layer formed on the surface of the second oxide layer and exposing the top surface of the first oxide layer has a sharp corner, and the floating gate formed subsequently has a sharp corner. The process for forming the sharp corner of the floating gate is simple, and the morphology of the sharp corner is easy to control, which improves the erasure efficiency and simplifies the process steps; secondly, when etching the first oxide layer exposed between the control gate structure to form an erase gate oxide layer, the thickness of the first oxide layer is reduced, thereby increasing the contact area between the erase gate formed on the erase gate oxide layer and the floating gate, and increasing the coupling capacitance between the floating gate and the erase gate; thirdly, the scheme forms the oxide layer before forming the floating gate layer, which reduces the thermal oxidation cost and is beneficial to process production. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 8 It is a schematic structural diagram of each step of a method for forming a memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the prior art still has many problems in the process of forming a NOT OR (NOR) type flash memory structure.

[0034] In an embodiment of a flash memory, a protective layer is formed on a floating gate layer as a mask to obtain a floating gate having a right-angle structure. On the one hand, the process is relatively complicated; on the other hand, the coupling capacitance between the floating gate and the erase gate is small, which reduces the erase efficiency.

[0035] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the same, wherein a plurality of modified areas are formed in a substrate and the substrate and the modified areas are oxidized so that the surface of the first oxide layer is higher than the surface of the second oxide layer, so that a subsequently formed floating gate has a sharp corner, thereby improving the erasure efficiency while simplifying the process steps; secondly, when etching the first oxide layer exposed between the control gate structures to form an erase gate oxide layer, the thickness of the first oxide layer is reduced, and the coupling capacitance between the floating gate and the erase gate is increased; thirdly, the scheme forms an oxide layer before forming a floating gate layer, thereby reducing the thermal oxidation cost and facilitating process production.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 1 to 8 It is a structural schematic diagram of the formation process of the memory structure of an embodiment of the present invention.

[0038] Please refer to Figure 1 , providing a substrate 100.

[0039] In this embodiment, the substrate 100 is made of silicon.

[0040] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0041] Please refer to Figure 2 , a plurality of modified regions 101 are formed in the substrate 100 .

[0042] The method for forming the modified area 101 includes: forming a first mask layer (unlabeled) on the surface of the substrate 100, wherein the first mask layer (unlabeled) exposes a portion of the surface of the substrate 100; and performing a modification treatment on the substrate 100 exposed by the first mask layer (unlabeled) to form a plurality of modified areas 101 located within the substrate 100.

[0043] The modification process is ion implantation.

[0044] The parameters of the ion implantation process include: the energy of the ion implantation is 30keV to 50keV; the ion implantation dose is 2E15 ions / cm 2 ~3E15 ions / cm 2 .

[0045] The material of the modified area 101 is amorphous.

[0046] The modified area 101 is modified so that in the subsequent oxidation treatment of the substrate 100 and the modified area 101, the oxidation rate of the surface of the modified area 101 is higher than the oxidation rate of the surface of the substrate 100, so that the surface of the first oxide layer 102 formed on the surface of the modified area 101 is higher than the surface of the second oxide layer 103 formed on the surface of the substrate 100, so that the floating gate layer 104 formed on the surface of the second oxide layer 103 that exposes the top surface of the first oxide layer 102 has a sharp corner, so the floating gate 109 formed subsequently has a sharp corner. The method of combining the modification treatment and the oxidation treatment makes the process of forming the floating gate sharp corner simple and the sharp corner morphology easy to control, thereby improving the erasing efficiency and simplifying the process steps.

[0047] Please refer to Figure 3 , the substrate 100 and the modified area 101 (such as Figure 2 The surface of the modified area 101 (as shown) is subjected to oxidation treatment, and the oxidation treatment has an effect on the surface of the modified area 101 (as shown) Figure 2 The oxidation rate of the surface of the modified area 101 (as shown) is higher than the oxidation rate of the surface of the substrate 100. Figure 2 A first oxide layer 102 is formed on the surface of the substrate 100, and a second oxide layer 103 is formed on the surface of the substrate 100. The surface of the first oxide layer 102 is higher than the surface of the second oxide layer 103, and the sidewall of the first oxide layer 102 is protruding.

[0048] The oxidation treatment process includes: furnace tube oxidation, rapid thermal oxidation and in-situ steam generation thermal oxidation. Specifically, in this embodiment, the oxidation treatment process is a furnace tube oxidation process; the oxidation treatment temperature of the oxidation treatment process is greater than 700°C.

[0049] The surface of the first oxide layer 102 is higher than the surface of the second oxide layer 103 by

[0050] The surface of the first oxide layer 102 is higher than the surface of the second oxide layer 103 , so that the floating gate layer subsequently formed on the surface of the second oxide layer 102 and exposing the top surface of the first oxide layer 103 has a sharp corner. Therefore, the subsequently formed floating gate has a sharp corner, which improves the erasure efficiency.

[0051] Please refer to Figure 4 A floating gate layer 104 is formed on the surface of the second oxide layer 103 , wherein the floating gate layer 104 exposes the top surface of the first oxide layer 102 , and the sidewall surface of the floating gate layer 104 in contact with the first oxide layer 102 is recessed.

[0052] The size range of the sidewall depression of the floating gate layer 104 is

[0053] The sidewall of the floating gate layer 104 contacting the first oxide layer 102 is recessed, so the floating gate layer 104 has a sharp corner, and the floating gate formed subsequently has a sharp corner, which improves the erasing efficiency.

[0054] In this embodiment, the method for forming the floating gate layer 104 includes: forming an initial floating gate layer (not labeled) on the surface of the second oxide layer 103; and planarizing the initial floating gate layer (not labeled) to form a floating gate layer 104 located on the surface of the second oxide layer 103.

[0055] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0056] The planarization process can form a sharp corner on the floating gate layer 104, thereby improving the erasing efficiency.

[0057] In another embodiment, the method for forming the floating gate layer further comprises: before the planarization process, forming a buffer layer on the surface of the initial floating gate layer; before the planarization process is performed on the initial floating gate layer, the buffer layer is further subjected to the planarization process. The material of the buffer layer comprises one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0058] The buffer layer can adjust the rate of the planarization process to avoid the planarization process causing loss to the floating gate layer.

[0059] Please refer to Figure 5 A plurality of separate control gate structures 105 are formed on the surface of the floating gate layer 104. The first oxide layer 102 has the control gate structures 105 on both sides, and a portion of the floating gate layer 104 surface between the control gate structures 105 and the first oxide layer 102 is exposed.

[0060] The method for forming the control gate structure 105 includes: forming a control gate structure layer (unlabeled) on the surface of the floating gate layer 104; forming a second mask layer (unlabeled) on the surface of the control gate structure layer (unlabeled), wherein the second mask layer (unlabeled) exposes a portion of the surface of the control gate structure layer (unlabeled); etching the control gate structure layer (unlabeled) using the second mask layer (unlabeled) as a mask until the surface of the floating gate layer 104 is exposed, thereby forming a plurality of discrete control gate structures 105.

[0061] The second mask layer (not labeled) is a single-layer structure or a multi-layer structure; the multi-layer structure includes one or more overlapping layers of a silicon oxide layer and a silicon nitride layer.

[0062] The control gate structure 105 includes a control gate dielectric layer 106 and a control gate layer 107 located on the surface of the control gate dielectric layer 106 .

[0063] The control gate dielectric layer 106 is an insulating layer that can prevent electrons from passing through. When a high voltage is applied to the control gate layer, electrons will penetrate the insulating layer from the source and enter the floating gate, forming a charge, representing a data bit; when a low voltage is applied to the control gate layer, electrons will penetrate the insulating layer from the floating gate and return to the source, eliminating the charge, representing another data bit.

[0064] The control gate dielectric layer 106 has advantages such as higher relative dielectric constant, higher breakdown electric field, and lower leakage current.

[0065] In this embodiment, the control gate dielectric layer 106 includes: a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

[0066] The formation method of the control gate structure 105 includes deposition. The deposition process includes atomic layer deposition, physical vapor deposition, and chemical vapor deposition. The atomic layer deposition process has the advantages of depositing a large area of ​​uniform thin film, nanometer-level controllable film thickness growth, deposition under low temperature conditions, and being suitable for various complex substrates; the physical vapor deposition process has the advantages of simple process, no pollution, less consumables, and uniform and dense film formation; the chemical vapor deposition process has the advantages of simple equipment, easy operation and maintenance, and good deposition effect. Specifically, in this embodiment, the deposition process is chemical vapor deposition.

[0067] The distance between the control gate structure 105 and the first oxide layer 102 along the direction parallel to the substrate 100 is

[0068] A portion of the floating gate layer 104 surface between the control gate structure 105 and the first oxide layer 102 is exposed, so that the contact area between the subsequently formed erase gate and the floating gate is increased, which can increase the coupling capacitance between the floating gate and the erase gate and improve the erase efficiency.

[0069] Please refer to Figure 6 , etching the first oxide layer 102 (such as Figure 5 As shown), an erase gate oxide layer 108 is formed on the surface of the substrate 100 between the floating gate layers 104.

[0070] In this embodiment, the etching process includes: a dry etching process.

[0071] The etching process is anisotropic etching, and the sidewall of the first oxide layer 102 is retained.

[0072] The etching gas of the etching process only selects the gas with an etching ratio to silicon oxide.

[0073] Specifically, in this embodiment, the etching depth range of the first oxide layer 102 is less than

[0074] Specifically, in this embodiment, the thickness range of the erase gate oxide layer 108 is greater than

[0075] On the one hand, the first oxide layer 102 (eg, Figure 5 When the erase gate oxide layer 108 is formed by removing the first oxide layer 102 (as shown in FIG. Figure 5 As shown in the figure, the thickness of the control gate structure 105 is increased, thereby increasing the contact area between the erase gate and the floating gate formed on the erase gate oxide layer 108, increasing the coupling capacitance between the floating gate and the erase gate, and improving the erasure efficiency; on the other hand, when etching the first oxide layer 102 exposed between the control gate structure 105, the sharp corners of the floating gate layer 104 are exposed, thereby improving the erasure efficiency.

[0076] Please refer to Figure 7 , etching the erase gate oxide layer 108 and the floating gate layer 104 on both sides of the control gate structure 105 (such as Figure 6 As shown), until the surface of the substrate 100 is exposed, a floating gate 109 is formed between the control gate structure 105 and the substrate 100.

[0077] Etch the erase gate oxide layer 108 and the floating gate layer 104 on both sides of the control gate structure 105 (eg Figure 6 The method for forming the floating gate 109 includes: forming a third mask layer (not labeled) on the erase gate oxide layer 108 and the surface of the control gate structure 105, wherein the third mask layer (not labeled) exposes the erase gate oxide layer 108 and the floating gate layer 104 on both sides of the control gate structure 105 (as shown in FIG. Figure 6 Using the third mask layer (not labeled) as a mask, etching the floating gate layer 104 (as shown) Figure 6 As shown), until the surface of the substrate 100 is exposed, the floating gate 109 is formed.

[0078] The floating gate 109 has a sharp corner, which makes it easier to form a sharp electric field, thereby increasing the local electric field strength, thereby increasing the tunneling probability and improving the erasure efficiency.

[0079] Please refer to Figure 8 , an erase gate 110 located between adjacent control gate structures 105 is formed on the erase gate oxide layer 108 .

[0080] In this embodiment, before forming the erase gate 110, the process further includes: forming an erase gate dielectric layer (not labeled) on the erase gate oxide 108; the erase gate dielectric layer (not labeled) is a single-layer or multi-layer structure.

[0081] The material of the erase gate dielectric layer (not labeled) includes: one or more of silicon oxide or silicon nitride.

[0082] The erase gate dielectric layer (not labeled) isolates the erase gate 110 from the control gate structure 105 and the floating gate 109, thereby reducing the tunneling effect of the current and improving the reliability of the memory structure.

[0083] Accordingly, the embodiment of the present invention also provides a memory structure, please continue to refer to Figure 8 , comprising: a substrate 100; a plurality of modified regions 101 (such as Figure 2 as shown); a first oxide layer 108 located on the surface of the modified area 101, the sidewalls of the first oxide layer 108 protruding; a second oxide layer 103 located on the surface of the substrate 100, the surface of the second oxide layer 103 being lower than the surface of the first oxide layer 108; a floating gate 109 located on the surface of the second oxide layer 103, the floating gate 109 exposing a portion of the surface of the second oxide layer 103 and the top surface of the first oxide layer 108, and the sidewall surface of the floating gate 109 in contact with the first oxide layer 108 is recessed; a plurality of separate control gate structures 105 located on the surface of the floating gate 109, the control gate structures 105 being located on both sides of the first oxide layer 108, and a portion of the surface of the floating gate 109 between the control gate structure 105 and the first oxide layer 108 is exposed; an erase gate 110 located between adjacent control gate structures 105.

[0084] The memory structure includes: a substrate 100 .

[0085] In this embodiment, the substrate 100 is made of silicon.

[0086] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0087] The memory structure includes: a plurality of modified regions 101 located in the substrate 100 .

[0088] The material of the modified area 101 is amorphous.

[0089] The memory structure includes: a first oxide layer 108 located on the surface of the modified area 101 , and a sidewall of the first oxide layer 108 is protruding.

[0090] The memory structure includes: a second oxide layer 103 located on the surface of the substrate 100 , wherein the surface of the second oxide layer 103 is lower than the surface of the first oxide layer 108 .

[0091] The surface of the first oxide layer 108 is higher than the surface of the second oxide layer 103 by

[0092] The memory structure includes: a floating gate 109 located on the surface of the second oxide layer 103, the floating gate 109 exposes a portion of the second oxide layer 103 surface and the top surface of the first oxide layer 108, and the sidewall surface of the floating gate 109 contacting the first oxide layer 108 is recessed.

[0093] The size range of the sidewall depression of the floating gate 109 is

[0094] The memory structure includes: a plurality of independent control gate structures 105 located on the surface of the floating gate 109, the control gate structures 105 are located on both sides of the first oxide layer 108, and a portion of the floating gate 109 surface between the control gate structures 105 and the first oxide layer 108 is exposed.

[0095] The control gate structure 105 includes a control gate dielectric layer 106 and a control gate layer 107 located on the surface of the control gate dielectric layer 106 .

[0096] The control gate dielectric layer 106 includes: a first silicon oxide layer, a silicon nitride layer located on a surface of the first silicon oxide layer, and a second silicon oxide layer located on a surface of the silicon nitride layer.

[0097] The distance between the control gate structure 105 and the first oxide layer 108 along the direction parallel to the substrate 100 is

[0098] The memory structure includes an erase gate 110 located between adjacent control gate structures 105 .

[0099] The memory structure includes an erase gate dielectric layer located between an erase gate oxide layer 108 and an erase gate 110 .

[0100] The erase gate dielectric layer (not labeled) is a single layer or multi-layer structure. The material of the erase gate dielectric layer (not labeled) includes: one or more of silicon oxide or silicon nitride.

[0101] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: substrate; a plurality of modified regions located within the substrate; A first oxide layer located on the surface of the modified area, wherein the sidewall of the first oxide layer protrudes; A second oxide layer located on the surface of the substrate, wherein the surface of the second oxide layer is lower than the surface of the first oxide layer; a floating gate located on the surface of the second oxide layer, wherein the floating gate exposes a portion of the surface of the second oxide layer and a top surface of the first oxide layer, and a sidewall surface of the floating gate in contact with the first oxide layer is recessed; A plurality of control gate structures separated from each other are located on the surface of the floating gate, wherein the control gate structures are located on both sides of the first oxide layer, and a portion of the floating gate surface between the control gate structures and the first oxide layer is exposed; An erase gate is located between adjacent control gate structures.

2. The memory structure according to claim 1, characterized in that: The material of the modified area is amorphous.

3. The memory structure according to claim 1, characterized in that: The range in which the surface of the first oxide layer is higher than the surface of the second oxide layer is 4. The memory structure according to claim 1, characterized in that: The size range of the floating gate sidewall recess is 5. The memory structure according to claim 1, characterized in that: The distance between the control gate structure and the first oxide layer along the direction parallel to the substrate ranges from 6. The memory structure according to claim 1, characterized in that: The control gate structure comprises: a control gate dielectric layer and a control gate layer located on the surface of the control gate dielectric layer.

7. The memory structure according to claim 6, characterized in that: The control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

8. A method for forming a memory structure, characterized in that: include: providing a substrate; forming a plurality of modified regions in the substrate; Performing oxidation treatment on the surfaces of the substrate and the modified area, wherein the oxidation rate of the modified area surface is higher than the oxidation rate of the substrate surface, forming a first oxide layer on the modified area surface, and forming a second oxide layer on the substrate surface, wherein the surface of the first oxide layer is higher than the surface of the second oxide layer, and the sidewall of the first oxide layer is protruding; forming a floating gate layer on the surface of the second oxide layer, wherein the floating gate layer exposes the top surface of the first oxide layer, and the sidewall surface of the floating gate layer in contact with the first oxide layer is recessed; A plurality of control gate structures separated from each other are formed on the surface of the floating gate layer, the control gate structures are respectively provided on both sides of the first oxide layer, and a portion of the floating gate layer surface between the control gate structure and the first oxide layer is exposed; Etching the first oxide layer exposed between the control gate structures to form an erase gate oxide layer on the substrate surface between the floating gate layers; Etching the erase gate oxide layer and the floating gate layers on both sides of the control gate structure until the substrate surface is exposed, thereby forming a floating gate between the control gate structure and the substrate; An erase gate located between adjacent control gate structures is formed on the erase gate oxide layer.

9. The method for forming a memory structure according to claim 8, wherein: The method for forming the modified area includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes part of the surface of the substrate; and performing a modification process on the substrate exposed by the first mask layer to form a plurality of modified areas located in the substrate.

10. The method for forming a memory structure according to claim 9, wherein: The modification process is ion implantation.

11. The method for forming a memory structure according to claim 10, wherein: The parameters of the ion implantation process include: the energy of the ion implantation is 30keV to 50keV; the ion implantation dose is 2E15ions / cm 2 ~3E15 ions / cm 2 .

12. The method for forming a memory structure according to claim 8, wherein: The material of the modified area is amorphous.

13. The method for forming a memory structure according to claim 8, wherein: The range in which the surface of the first oxide layer is higher than the surface of the second oxide layer is 14. The method for forming a memory structure according to claim 8, wherein: The size range of the recess on the sidewall of the floating gate layer is 15. The method for forming a memory structure according to claim 8, wherein: The distance between the control gate structure and the first oxide layer along the direction parallel to the substrate is 16. The method for forming a memory structure according to claim 8, wherein: The method for forming the floating gate layer comprises: forming an initial floating gate layer on the surface of the second oxide layer; and performing a planarization process on the initial floating gate layer to form a floating gate layer located on the surface of the second oxide layer.

17. The method for forming a memory structure according to claim 16, wherein: The method for forming the floating gate layer further includes: before the planarization process, forming a buffer layer on the surface of the initial floating gate layer; before the planarization process is performed on the initial floating gate layer, further performing the planarization process on the buffer layer.

18. The method for forming a memory structure according to claim 17, wherein: The material of the buffer layer includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

19. The method for forming a memory structure according to claim 8, wherein: The control gate structure comprises: a control gate dielectric layer and a control gate layer located on the surface of the control gate dielectric layer.

20. The method for forming a memory structure according to claim 19, wherein: The control gate dielectric layer includes: a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

21. The method for forming a memory structure according to claim 19, wherein: The method for forming the control gate structure includes: forming a control gate structure layer on the surface of the floating gate layer; forming a second mask layer on the surface of the control gate structure layer, wherein the second mask layer exposes a portion of the surface of the control gate structure layer; etching the control gate structure layer using the second mask layer as a mask until the surface of the floating gate layer is exposed, thereby forming a plurality of discrete control gate structures.

22. The method for forming a memory structure according to claim 21, wherein: The second mask layer is a single-layer structure or a multi-layer structure; the multi-layer structure includes one or more overlapping layers of a silicon oxide layer and a silicon nitride layer.

23. The method for forming a memory structure according to claim 8, wherein: The method for etching the erase gate oxide layer and the floating gate layer on both sides of the control gate structure to form the floating gate comprises: forming a third mask layer on the erase gate oxide layer and the surface of the control gate structure, wherein the third mask layer exposes the erase gate oxide layer and the surface of the floating gate layer on both sides of the control gate structure; using the third mask layer as a mask, etching the floating gate layer until the substrate surface is exposed to form the floating gate.

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