Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel, the array substrate comprises a substrate and a pixel circuit located on one side of the substrate, and the pixel circuit comprises a first thin film transistor and a second thin film transistor which are stacked in the direction perpendicular to the substrate; wherein the first thin film transistor comprises a first drain electrode, and the first drain electrode is multiplexed as a third grid electrode of the second thin film transistor. According to the array substrate, the layout area required by the first thin film transistor and the second thin film transistor in a single pixel is reduced, layout arrangement is simplified, the number of pixels in a fixed range is increased, and high-PPI products can be prepared conveniently.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] At present, people's demand for high-definition display quality is constantly increasing, and how to achieve higher pixel density (Pixels Per Inch, PPI) has gradually become an important factor in the production of various display panel products.

[0003] Nowadays, Organic Light Emitting Diode (OLED) is often used in display devices. The pixel circuit of an OLED display panel usually requires multiple thin-film transistors to drive. Multiple thin-film transistors will occupy a large layout space. When applied to high-PPI products, the problem of low screen display resolution will arise. Summary of the invention

[0004] In order to solve the above problems, the embodiments of the present application provide an array substrate and a method for preparing the same, and a display panel.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising: a substrate, and a pixel circuit located on one side of the substrate, the pixel circuit comprising a first thin film transistor and a second thin film transistor stacked in a direction perpendicular to the substrate; wherein the first thin film transistor comprises a first drain, and the first drain is reused as a third gate of the second thin film transistor.

[0006] In combination with the first aspect, the first thin film transistor further comprises a first source electrode and a first active layer, and the first source electrode, the first active layer and the first drain electrode are arranged in a direction parallel to the substrate. Preferably, in a direction perpendicular to the substrate, the thickness of the first drain electrode is greater than the thickness of the first active layer, and the thickness of the first drain electrode is greater than the thickness of the first source electrode. Preferably, the first thin film transistor further comprises a first gate electrode, and the first gate electrode is located on a side of the first active layer close to the substrate, or the first gate electrode is located on a side of the first active layer away from the substrate.

[0007] In combination with the first aspect, the second thin film transistor further includes a second source electrode, a second active layer, and a second drain electrode located on the same side of the first drain electrode, and the second source electrode, the second active layer, and the second drain electrode are stacked in a direction perpendicular to the substrate. Preferably, the first thin film transistor further includes a first active layer, and the first active layer and the second active layer are located on the same side of the first drain electrode. Preferably, the second thin film transistor further includes a second gate electrode, which is located on the side of the second active layer away from the third gate electrode.

[0008] In combination with the first aspect, the pixel circuit further includes: a first storage capacitor, wherein the first storage capacitor includes a third gate. Preferably, the second thin film transistor further includes a second active layer, and the first memory further includes a first capacitor substrate; in a direction parallel to the substrate, the first capacitor substrate is located on a side of the third gate away from the second active layer.

[0009] In combination with the first aspect, the second thin film transistor further includes a second gate, and in a direction parallel to the substrate, the second gate is located on one side of the third gate; the pixel circuit further includes: a second storage capacitor, and the second storage capacitor includes the second gate. Preferably, the second storage capacitor further includes a second capacitor substrate, and the second capacitor substrate is located on a side of the second gate away from the third gate.

[0010] In a second aspect, an embodiment of the present application provides a method for preparing an array substrate, comprising: providing a substrate, forming a first gate on the substrate; forming a first gate insulating layer on the first gate and the substrate, the first gate insulating layer comprising a first part and a second part, wherein the height of the second part is greater than the height of the first part in a direction perpendicular to the substrate; forming a first active layer on the first part; forming a first source on one side of the first active layer, and forming a second gate insulating layer on the first source and the first active layer; forming a first hole, a second hole and a third hole arranged in sequence along a direction parallel to the substrate in the second gate insulating layer, wherein a portion of the side wall of the third hole is formed by the first gate insulating layer; forming a second gate, a second source and a first drain in the first hole, the second hole and the third hole, respectively, wherein the first drain is reused as the third gate; etching on the second source, and forming a second active layer on the second source; forming a second drain on the second active layer.

[0011] In combination with the second aspect, the method also includes forming a first capacitor substrate on a surface of the first gate insulating layer away from the second gate insulating layer along a direction parallel to the substrate; and / or forming a first hole, a second hole and a third hole arranged in sequence along a direction parallel to the substrate in the second gate insulating layer, while forming a groove in the second gate insulating layer, the groove being located on the side of the first hole away from the second hole; and forming a second capacitor substrate in the groove.

[0012] In combination with the second aspect, the thickness of each part of the first gate insulating layer is greater than 1 um; and / or the thickness of each part of the second gate insulating layer is greater than 1 um.

[0013] In combination with the second aspect, the second gate, the second source and the first drain are made of the same material; wherein, forming the second gate, the second source and the first drain in the first hole, the second hole and the third hole respectively includes: simultaneously performing deposition and patterning in the first hole, the second hole and the third hole to form the second gate, the second source and the first drain.

[0014] In a third aspect, an embodiment of the present application provides a display panel, comprising the above-mentioned array substrate.

[0015] Through the above technical solution, the first thin film transistor and the second thin film transistor are stacked, which reduces the layout area required by the first thin film transistor and the second thin film transistor in a single pixel, increases the number of pixels within a fixed range, and facilitates the preparation of high PPI products. In addition, the drain of the first thin film transistor is reused as the gate of the second thin film transistor, omitting the circuit connection, further simplifying the layout of the layout. Furthermore, the first thin film transistor can also compensate for the second thin film transistor to avoid the threshold voltage offset of the second thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic structural diagram of an array substrate provided by an exemplary embodiment of the present application.

[0017] Figure 2 yes Figure 1 The shown is a cross-sectional view of the array substrate along line AA.

[0018] Figure 3 It is a structural schematic diagram of an array substrate provided by another exemplary embodiment of the present application.

[0019] Figure 4 yes Figure 1 An exemplary equivalent circuit diagram of a pixel circuit in an array substrate.

[0020] Figure 5 Detailed description of the invention The figure is a flow chart of a method for preparing an array substrate provided by an exemplary embodiment of the present application.

[0021] Figures 6A-6G It is a schematic diagram of a method for preparing an array substrate provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] With the rapid development and application of information technology, wireless mobile communications and information appliances, people are increasingly dependent on electronic products, which not only brings about the vigorous development of various display technologies and display devices, but also promotes and improves people's demand for screen resolution.

[0024] At present, the pixel circuit of an OLED display panel usually requires multiple thin film transistors to drive, where the thin film transistors include drive thin film transistors (Drive Thin Film Tranistor, DTFT) and switch thin film transistors (Switch Thin Film Transistor, STFT). However, in an OLED display panel, the drive thin film transistor and the switch thin film transistor are arranged horizontally, which will occupy a large layout space and cause the problem of low screen resolution. In some cases, in order to ensure high PPI and reduce the area occupied by the thin film transistor, the switch thin film transistor can be cancelled. However, if the switch thin film transistor is cancelled, the drive thin film transistor cannot be compensated, which will cause the threshold voltage of the drive thin film transistor to shift, resulting in deterioration of image quality.

[0025] In view of the above technical problems, the present application provides an array substrate on the one hand.

[0026] Figure 1 is a schematic diagram of the structure of an array substrate provided by an exemplary embodiment of the present application. Figure 1 As shown, the array substrate includes a substrate and a pixel circuit located on one side of the substrate, the pixel circuit includes a first thin film transistor and a second thin film transistor stacked in a direction perpendicular to the substrate, wherein the first thin film transistor includes a first drain Drain1, and the first drain Drain1 is reused as a third gate Gate3 of the second thin film transistor.

[0027] Specifically, the pixel circuit may include a thin film transistor having a switching function (i.e., a switching thin film transistor) and a thin film transistor having a driving function (i.e., a driving thin film transistor). In the embodiment of the present application, the first thin film transistor is a switching thin film transistor, and the second thin film transistor is a driving thin film transistor. Optionally, the pixel circuit may also include other transistors, for example, a transistor having a compensation function.

[0028] It is understood that the embodiment of the present application is based on two transistor stacks. In other embodiments, three or more transistors may be stacked, as long as the gate of one transistor and the drain of another transistor are the same electrode.

[0029] Continue to refer Figure 1As shown, the first thin film transistor also includes a first source electrode Source1 and a first active layer Channel1, and the first source electrode Source1, the first active layer Channel1 and the first drain electrode Drain1 are arranged in a direction parallel to the substrate. In this case, the channel direction is parallel to the substrate. That is, the first thin film transistor is a lateral thin film transistor. In this way, the thickness of the array substrate can be reduced. Further, in a direction perpendicular to the substrate, the thickness of the first drain electrode Drain1 is greater than the thickness of the first active layer Channel1, and the thickness of the first drain electrode Drain1 is greater than the thickness of the first source electrode Source1.

[0030] The second thin film transistor also includes a second source electrode Source2, a second active layer Channel2, and a second drain electrode Drain2 located on the same side as the first drain electrode Drain1. The first active layer Channel1 and the second active layer Channel2 are located on the same side as the first drain electrode Drain1. The second source electrode Source2, the second active layer Channel2, and the second drain electrode Drain2 are stacked in a direction perpendicular to the substrate. In this case, the channel direction is perpendicular to the substrate. That is, the second thin film transistor is a vertical thin film transistor. The second thin film transistor also includes a second gate Gate2, and in a direction parallel to the substrate, the second gate Gate2 is located on one side of the third gate Gate3, that is, the second thin film transistor is a dual-gate structure. The second source electrode Source2, the second active layer Channel2, and the second drain electrode Drain2 of the second thin film transistor are stacked vertically, and the second gate Gate2 and the third gate Gate3 are respectively arranged on both sides of the second active layer Channel2, which can reduce the layout area required by the second thin film transistor and reduce the space occupied by the second thin film transistor.

[0031] Figure 2 for Figure 1 The cross-sectional view of the array substrate along line AA is shown in FIG. Figure 2 As shown, the pixel circuit is a circular ring structure. It should be understood that the pixel circuit may also be a structure of other shapes, such as a rectangle. Figure 2 , from left to right, they are the second capacitor substrate, the second gate insulating layer GI2, the second gate Gate2, the second gate insulating layer GI2, the second active layer Channel2, the third gate Gate3, the first gate insulating layer GI1 and the first capacitor substrate. Figure 2 It can be seen that in the direction perpendicular to the substrate, the second thin film transistor completely covers the first thin film transistor, that is, the first thin film transistor and the second thin film transistor are completely stacked.

[0032] In the array substrate provided by the embodiment of the present application, a first thin film transistor and a second thin film transistor are stacked, and the first drain of the first thin film transistor is reused as the third gate of the second thin film transistor, thereby reducing the layout area required for the first thin film transistor (for example, a switching thin film transistor) and the second thin film transistor (for example, a driving thin film transistor) in a single pixel, omitting circuit connections, simplifying the layout of the layout, and increasing the number of pixels within a fixed range, thereby facilitating the preparation of high PPI products.

[0033] Continue to refer Figure 1 As shown, the first gate Gate1 is located on a side of the first active layer Channel1 close to the substrate, that is, the first thin film transistor is a bottom gate structure.

[0034] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided by another exemplary embodiment of the present application. Figure 3 As shown, the array substrate and Figure 1 The difference between the array substrate and the substrate is that the first gate Gate1 is located on the side of the first active layer Channel1 away from the substrate, that is, the first thin film transistor is a top gate structure. In the embodiment of the present application, the first thin film transistor can be a bottom gate structure or a top gate structure. When the first thin film transistor is a top gate structure, parasitic capacitance is easily formed between the first gate Gate1 and the second source Source2, so the first thin film transistor is preferably a bottom gate structure.

[0035] In the embodiment of the present application, the pixel circuit further includes a first storage capacitor Cst1 and a second storage capacitor Cst2. The first storage capacitor includes a third gate Gate3 and a first capacitor substrate, and the first capacitor substrate is located on a side of the third gate Gate3 away from the second active layer Channel2. The second storage capacitor includes a second gate Gate2 and a second capacitor substrate, and the second capacitor substrate is located on a side of the second gate Gate2 away from the third gate Gate3. The first storage capacitor is used to store a signal of a driving level of the second thin film transistor (driving thin film transistor); the second storage capacitor is used to store a signal for compensating the threshold voltage of the second thin film transistor (driving thin film transistor).

[0036] Figure 4 yes Figure 1 An exemplary equivalent circuit diagram of a pixel circuit in an array substrate is shown in FIG. Figure 4 As shown, the pixel circuit includes a switch thin film transistor STFT, a drive thin film transistor DTFT, and two storage capacitors Cst1 and Cst2, wherein the drive thin film transistor DTFT is a thin film transistor with a dual-gate structure. Figure 4The device also includes an AFE detection chip and a second switch thin film transistor STFT2, which are used to determine the threshold voltage Vth of the driving thin film transistor DTFT, wherein one end of the second switch thin film transistor STFT2 is connected to one end of the driving thin film transistor DTFT.

[0037] The working principle of the pixel circuit is described below.

[0038] The first stage (detection stage): the switching thin film transistor STFT is turned off, the driving thin film transistor DTFT is turned on, a voltage is applied to the driving thin film transistor DTFT, the current flowing out of the driving thin film transistor DTFE is obtained through the AFE chip, and the threshold voltage Vth is calculated.

[0039] The second stage (compensation stage): the second switching thin film transistor STFT2 is disconnected from the driving thin film transistor DTFT (that is, the AFE detection chip and the second switching thin film transistor STFT2 are removed from the pixel circuit), the switching thin film transistor STFT inputs the Vdata2 signal, the second storage capacitor Cst2 stores the Vdata2 signal, and the driving thin film transistor DTFT is compensated according to the threshold voltage Vth.

[0040] The third stage (writing stage): the switching thin film transistor STFT and the driving thin film transistor DTFT are both turned off, and the Vdata1 signal is written into the first storage capacitor Cst1 and stored.

[0041] The fourth stage (output stage): the switch thin film transistor STFT is turned off, the drive thin film transistor DTFT is turned on, and the current is output according to the Vdata1 signal stored in the first storage capacitor Cst1.

[0042] It can be seen from the above working process that the switching thin film transistor STFT (first thin film transistor) in the embodiment of the present application can compensate the driving thin film transistor DTFT (second thin film transistor) to avoid the threshold voltage offset of the driving thin film transistor DTFT, resulting in poor image quality.

[0043] In addition, a second aspect of the present application provides a method for preparing an array substrate.

[0044] Figure 5 FIG. 1 is a flow chart of a method for preparing an array substrate provided by an exemplary embodiment of the present application. Figure 5 As shown, the method for preparing the array substrate is applied to the array substrate mentioned in the first aspect. The method for preparing the array substrate comprises the following steps.

[0045] Step S510: provide a substrate and form a first gate on the substrate. Fig. 6AAs shown, a first gate Gate1 is formed on a substrate. The thickness of the first gate Gate1 is 100-300 nm.

[0046] Specifically, the substrate is an insulating material, which may be an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (Al2O3), ceramics, etc., or an organic insulating material, such as polyethylene (PE), polyimide (PI), etc. The first gate Gate1 is a conductive material, such as molybdenum (Mo), titanium (Ti), copper (Cu), indium tin oxide (ITO), etc.

[0047] Specifically, the substrate is formed by deposition or coating. The first gate Gate1 is formed by deposition and patterning.

[0048] Step S520, forming a first gate insulating layer on the first gate and the substrate. Figure 6B As shown, the first gate insulating layer includes a first portion and a second portion. In a direction perpendicular to the substrate, the height of the second portion is greater than the height of the first portion.

[0049] Specifically, the first gate insulating layer GI1 is an insulating material, which can be an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (Al2O3), ceramics, etc., or an organic insulating material, such as polyethylene (PE), polyimide (PI), etc.

[0050] Specifically, a first gate insulating layer is deposited on the first gate Gate1 and the substrate, and then the first gate insulating layer is etched to form Figure 6B The first gate insulating layer GI1 shown in FIG. When etching is performed, on one side of the second portion ( Figure 6B The thickness of each part of the first gate insulating layer GI1 (for example, the first part and the second part) is greater than 1um, and the thickness of the first part and the second part can be adjusted according to the size of the first capacitor Cst1. Optionally, on the other side of the second part ( Figure 6B The entire etching is performed to expose the substrate (right side in the middle), or only a portion of the etching is performed, and the etching depth can be adjusted according to the size of the first capacitor Cst1.

[0051] Step S530, forming a first active layer on the first portion. The structure of the first active layer Channel1 is as follows: Figure 6C The thickness of the first active layer Channel1 is 30-50 nm.

[0052] Specifically, the material of the first active layer Channel1 includes a P-type semiconductor material or an N-type semiconductor material. For example, the first active layer Channel1 is indium gallium zinc oxide (IGZO), polycrystalline silicon (Poly-Si), or the like.

[0053] Specifically, a first active layer is deposited on a first portion of the first gate insulating layer GI1 and patterned to form Figure 6C The first active layer Channel1 is shown.

[0054] Step S540, forming a first source electrode on one side of the first active layer, forming a second gate insulating layer on the first source electrode and the first active layer, and forming a first hole, a second hole and a third hole arranged in sequence parallel to the substrate direction in the second gate insulating layer. Part of the sidewall of the third hole is formed by the first gate insulating layer GI1, such as Fig.6D shown.

[0055] Specifically, the first source electrode Source1 is a conductive material, for example, molybdenum (Mo), titanium (Ti), copper (Cu), indium tin oxide (ITO), etc. The first source electrode Source1 is formed by deposition and patterning processes.

[0056] Specifically, the second gate insulating layer GI2 is an insulating material, which may be an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (Al2O3), ceramics, etc., or an organic insulating material, such as polyethylene (PE), polyimide (PI), etc. The materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 may be the same or different.

[0057] Specifically, a second gate insulating layer GI2 is deposited on the first source electrode Source1 and the first active layer Channel1, and the second gate insulating layer GI2 is etched to form a first hole, a second hole and a third hole sequentially arranged in a direction parallel to the substrate, such as Fig.6D As shown. When etching, the etching depth of the third hole needs to expose the first part of the first gate insulating layer GI1, so that when the first drain electrode Drain1 is subsequently deposited, the first drain electrode Drain1 contacts the first active layer Channel1. The etching depths of the first hole and the second hole are determined according to the performance requirements of the second thin film transistor. The thickness of each part of the second gate insulating layer GI2 is greater than 1um, and the thickness of each part of the second gate insulating layer GI2 can be adjusted according to the size of the second capacitor Cst2.

[0058] Step S550, forming a second gate, a second source and a first drain in the first hole, the second hole and the third hole respectively. The first drain Drain1 is reused as the third gate Gate3, as shown in FIG. Fig. 6E shown.

[0059] The second gate Gate2, the second source Source2 and the first drain Drain1 are all made of conductive materials, such as molybdenum (Mo), titanium (Ti), copper (Cu), indium tin oxide (ITO), etc. The materials of the second gate Gate2, the second source Source2 and the first drain Drain1 can be the same or different. If the second gate Gate2, the second source Source2 and the first drain Drain1 are made of the same material, deposition and patterning are performed simultaneously in the first hole, the second hole and the third hole to form the second gate Gate2, the second source Source2 and the first drain Drain1, thereby simplifying the preparation process. If the second gate Gate2, the second source Source2 and the first drain Drain1 are made of different materials, deposition and patterning are performed separately.

[0060] Optionally, a first capacitor substrate is formed on a surface of the first gate insulating layer GI1 away from the second gate insulating layer GI2 in a direction parallel to the substrate. While forming a first hole, a second hole, and a third hole in sequence in a direction parallel to the substrate in the second gate insulating layer GI2, a groove is formed in the second gate insulating layer GI2, the groove is located on a side of the first hole away from the second hole, and a second capacitor substrate is formed in the groove.

[0061] The first capacitor substrate and the second capacitor substrate are both made of conductive materials, such as molybdenum (Mo), titanium (Ti), copper (Cu), indium tin oxide (ITO), etc. The materials of the first capacitor substrate and the second capacitor substrate can be the same as or different from the materials of the second gate Gate2, the second source Source2, and the first drain Drain1. If the materials of the first capacitor substrate and the second capacitor substrate are the same as the materials of the second gate Gate2, the second source Source2, and the first drain Drain1, the first capacitor substrate, the second capacitor substrate, the second gate Gate2, the second source Source2, and the first drain Drain1 can be deposited at the same time, and then formed through patterning.

[0062] Step S560, etching is performed on the second source electrode, and a second active layer is formed on the second source electrode. Fig. 6F As shown, along the direction perpendicular to the substrate, the second source Source2 and the second active layer Channel2 are stacked and arranged.

[0063] Specifically, the material of the second active layer Channel2 includes P-type semiconductor material or N-type semiconductor material, for example, the second active layer Channel2 is Indium Gallium Zinc Oxide (IGZO), Polycrystalline Silicon (Poly-Si), etc. The materials of the first active layer Channel1 and the second active layer Channel2 can be the same or different.

[0064] Specifically, a portion of the second source electrode Source2 is etched away, and a second active layer is deposited at the etched portion and patterned to form Fig. 6F The second active layer Channel2 is shown.

[0065] Step S570, forming a second drain electrode on the second active layer. Figure 6G As shown, the second drain electrode Drain2 is stacked on the second active layer Channel2.

[0066] Specifically, the second drain electrode Drain2 is a conductive material, for example, molybdenum (Mo), titanium (Ti), copper (Cu), indium tin oxide (ITO), etc. The second active layer Channel2 is deposited and patterned to form the second drain electrode Drain2.

[0067] The present application provides a method for preparing an array substrate. The array substrate prepared based on the method has a first thin film transistor and a second thin film transistor stacked in a direction perpendicular to a substrate, and the drain of the first thin film transistor is reused as the gate of the second thin film transistor, thereby reducing the layout area required for the first thin film transistor and the second thin film transistor in a single pixel, simplifying the layout, increasing the number of pixels within a fixed range, and facilitating the preparation of high PPI products.

[0068] In another embodiment of the present application, step S510 may be performed after step S530 is completed. Specifically, the steps include: forming a first gate insulating layer GI1 on a substrate, the first gate insulating layer GI1 including a first portion and a second portion, in a direction perpendicular to the substrate, the height of the second portion is greater than the height of the first portion; forming a first active layer Channel1 on the first portion; forming a first gate Gate1 on the first active layer Channel1; forming a first source Source1 on one side of the first active layer Channel1, forming a second gate insulating layer GI2 on the first source Source1, the first gate Gate1 and the first active layer Channel1, and forming a second gate insulating layer GI2 on the second gate A first hole, a second hole and a third hole are formed in the gate insulating layer GI2, which are arranged in sequence along a direction parallel to the substrate, wherein part of the sidewall of the third hole is formed by the first gate insulating layer GI1; a second gate Gate2, a second source Source2 and a first drain Drain1 are formed in the first hole, the second hole and the third hole, respectively, wherein the first drain Drain1 is reused as the third gate Gate3; etching is performed on the second source Source2, and a second active layer Channel2 is formed on the second source Source2; and a second drain Drain2 is formed on the second active layer Channel2. The array substrate structure formed according to the method is as follows Figure 3 shown.

[0069] An embodiment of the present application provides a display panel, which includes the array substrate of any one of the above embodiments.

[0070] Exemplarily, the display panel can be a rigid display panel or a flexible display panel (i.e., bendable and foldable); its type can be a twisted nematic (TN), vertical alignment (VA), in-plane switching (IPS) or advanced super dimensional switch (ADS) type liquid crystal display panel, or it can be an organic light-emitting diode (OLED) display panel; or it can be a Micro LED display panel or a Mini LED display panel, which is not limited here.

[0071] It is understandable that the display panel can be applied to a display device, and the display device can be, for example, a mobile terminal, a tablet computer, a computer monitor, a television, a wearable device, an information query machine, or any other product or component with a display function. The display panel includes an array substrate as in any embodiment of the present application, and its technical principle and the effects produced are similar, which will not be repeated here.

[0072] The display panel provided in the embodiment of the present application includes a first thin film transistor and a second thin film transistor stacked in a method perpendicular to the substrate, and the drain of the first thin film transistor is reused as the gate of the second thin film transistor. Through this arrangement, the layout area required for the first thin film transistor and the second thin film transistor in a single pixel is reduced, the layout design is simplified, the number of pixels within a fixed range is increased, and the preparation of high PPI products is facilitated.

[0073] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0074] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0075] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0076] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0077] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: include: substrate; and A pixel circuit, located on one side of the substrate, the pixel circuit comprising a first thin film transistor and a second thin film transistor stacked in a direction perpendicular to the substrate; The first thin film transistor includes a first drain electrode, and the first drain electrode is multiplexed as a third gate electrode of the second thin film transistor.

2. The array substrate according to claim 1, characterized in that: The first thin film transistor further includes a first source electrode and a first active layer, wherein the first source electrode, the first active layer and the first drain electrode are arranged in a direction parallel to the substrate; Preferably, in a direction perpendicular to the substrate, the thickness of the first drain electrode is greater than the thickness of the first active layer, and the thickness of the first drain electrode is greater than the thickness of the first source electrode; Preferably, the first thin film transistor further includes a first gate, and the first gate is located on a side of the first active layer close to the substrate, or the first gate is located on a side of the first active layer far from the substrate.

3. The array substrate according to claim 1 or 2, characterized in that: The second thin film transistor further includes a second source electrode, a second active layer and a second drain electrode located on the same side as the first drain electrode, and the second source electrode, the second active layer and the second drain electrode are stacked in a direction perpendicular to the substrate; Preferably, the first thin film transistor further comprises a first active layer, and the first active layer and the second active layer are located on the same side of the first drain electrode; Preferably, the second thin film transistor further includes a second gate located on a side of the second active layer away from the third gate.

4. The array substrate according to claim 1 or 2, characterized in that: The pixel circuit further includes: a first storage capacitor, wherein the first storage capacitor includes the third gate; Preferably, the second thin film transistor further includes a second active layer, and the first memory further includes a first capacitor substrate; in a direction parallel to the substrate, the first capacitor substrate is located on a side of the third gate away from the second active layer.

5. The array substrate according to claim 1 or 2, characterized in that: The second thin film transistor further includes a second gate, and in a direction parallel to the substrate, the second gate is located on one side of the third gate; the pixel circuit further includes: a second storage capacitor, and the second storage capacitor includes the second gate; Preferably, the second storage capacitor further includes a second capacitor substrate, and the second capacitor substrate is located on a side of the second gate away from the third gate.

6. A method for preparing an array substrate, characterized in that: include: Providing a substrate, and forming a first gate on the substrate; forming a first gate insulating layer on the first gate and the substrate, wherein the first gate insulating layer comprises a first portion and a second portion, and in a direction perpendicular to the substrate, a height of the second portion is greater than a height of the first portion; forming a first active layer on the first portion; forming a first source electrode on one side of the first active layer, and forming a second gate insulating layer on the first source electrode and the first active layer; forming a first hole, a second hole and a third hole sequentially arranged in a direction parallel to the substrate in the second gate insulating layer, wherein a part of the sidewall of the third hole is formed by the first gate insulating layer; A second gate, a second source and a first drain are formed in the first hole, the second hole and the third hole respectively, wherein the first drain is reused as the third gate; Etching the second source electrode and forming a second active layer on the second source electrode; A second drain electrode is formed on the second active layer.

7. The method for preparing an array substrate according to claim 6, characterized in that: Also includes: Forming a first capacitor substrate on a surface of the first gate insulating layer away from the second gate insulating layer in a direction parallel to the substrate; and / or While forming a first hole, a second hole and a third hole sequentially arranged in a direction parallel to the substrate in the second gate insulating layer, a groove is formed in the second gate insulating layer, the groove being located on a side of the first hole away from the second hole; A second capacitor substrate is formed in the groove.

8. The method for preparing an array substrate according to claim 6 or 7, characterized in that: The thickness of each part of the first gate insulating layer is greater than 1 um; and / or The thickness of each part of the second gate insulating layer is greater than 1 um.

9. The method for preparing an array substrate according to claim 6 or 7, characterized in that: The second gate, the second source and the first drain are made of the same material; Wherein, forming a second gate, a second source and a first drain in the first hole, the second hole and the third hole respectively comprises: Deposition and patterning are simultaneously performed in the first hole, the second hole, and the third hole to form the second gate, the second source, and the first drain.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 5.

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