Display panel and method for manufacturing same

Abstract

The invention relates to a display panel and a method for manufacturing the same. The display panel includes a substrate layer, a circuit element layer, and a light emitting element layer. The circuit element layer includes a power supply electrode. The light emitting element layer includes: an auxiliary electrode provided on a side surface of the power supply electrode; a pixel defining film defining a pixel opening; a conductive partition wall disposed on the pixel defining film; a lower electrode disposed in the pixel opening; a light emitting pattern disposed on the lower electrode; and an upper electrode disposed on the light emitting pattern. The conductive partition wall includes a first conductive layer disposed on the pixel defining film and a second conductive layer disposed on the first conductive layer, and a side surface of the second conductive layer protrudes from a side surface of the first conductive layer. The upper electrode is electrically connected to the power supply electrode via the auxiliary electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0098334 filed on Jul. 27, 2023 and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display panel and a method for manufacturing the display panel, and more particularly, to a display panel having improved processability and reliability and a method for manufacturing the display panel. Background Art

[0003] Multimedia electronic devices such as televisions, mobile phones, tablet computers, computers, navigation devices, and game consoles are equipped with display panels for displaying images.

[0004] The display panel includes a light emitting element and a pixel circuit for operating the light emitting element. The light emitting element included in the display panel emits light based on a voltage applied from the pixel circuit and creates an image.

[0005] A scheme for patterning a light emitting element is being studied to improve the reliability of a display panel, and recently, a scheme for patterning a commonly provided light emitting material in units of pixels using an open mask is being studied. Summary of the invention

[0006] Embodiments of the present disclosure provide a display panel with improved reliability.

[0007] Embodiments of the present disclosure provide a method for manufacturing a display panel having improved processability and reliability.

[0008] In an embodiment of the present disclosure, a display panel includes: a substrate layer; a circuit element layer, which is arranged on the substrate layer; and a light-emitting element layer, which is arranged on the circuit element layer, the circuit element layer includes a power electrode, and the light-emitting element layer includes: an auxiliary electrode, which is arranged on the side surface of the power electrode; a pixel defining film, which defines a pixel opening; a conductive partition wall, which is arranged on the pixel defining film; a lower electrode, which is arranged in the pixel opening; a light-emitting pattern, which is arranged on the lower electrode; and an upper electrode, which is arranged on the light-emitting pattern, the conductive partition wall includes a first conductive layer arranged on the pixel defining film and a second conductive layer arranged on the first conductive layer, the side surface of the second conductive layer protrudes more than the side surface of the first conductive layer, and the upper electrode is electrically connected to the power electrode via the auxiliary electrode.

[0009] In an embodiment, the circuit element layer may further include a first circuit layer disposed on the base layer and a second circuit layer defining the opening and disposed on the first circuit layer, and the power electrode may be disposed in the opening of the second circuit layer.

[0010] In an embodiment, in a plan view, the opening of the second circuit layer may be defined to be spaced apart from the lower electrode.

[0011] In an embodiment, the auxiliary electrode may be disposed directly on a side surface of the power electrode in a plan view.

[0012] In an embodiment, a pixel defining film may be disposed on the second circuit layer.

[0013] In an embodiment, the auxiliary electrode may include or consist of the same material as that of the lower electrode.

[0014] In an embodiment, the auxiliary electrode may be spaced apart from the lower electrode in a plan view and electrically insulated from the lower electrode.

[0015] In an embodiment, the circuit element layer may further include a transistor, and the lower electrode may be electrically connected to the transistor.

[0016] In an embodiment, the conductive partition wall may further include a third conductive layer disposed between the first conductive layer and the pixel defining film, and a side surface of the third conductive layer may protrude more than a side surface of the first conductive layer.

[0017] In an embodiment, the power electrode may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and side surfaces of the first layer and the third layer may protrude more than side surfaces of the second layer.

[0018] In an embodiment, the lower electrode and the auxiliary electrode may include ITO, or consist of ITO.

[0019] In an embodiment, the power electrode may include Al, or consist of Al.

[0020] In an embodiment of the present disclosure, a method for manufacturing a display panel includes: preparing a base layer; forming a circuit element layer on the base layer; and forming a light-emitting element layer on the circuit element layer, the formation of the circuit element layer includes: forming a power electrode on a first circuit layer; and forming a second circuit layer on the first circuit layer to define an opening for exposing the power electrode, the formation of the light-emitting element layer includes: forming a lower electrode and an auxiliary electrode; forming a pixel defining film covering a portion of the lower electrode; forming a conductive partition wall on the pixel defining film; forming a light-emitting pattern on the lower electrode; and forming an upper electrode on the light-emitting pattern, the formation of the conductive partition wall includes: forming a first conductive layer; and forming a second conductive layer on the first conductive layer, and the side surface of the second conductive layer is formed to protrude more than the side surface of the first conductive layer.

[0021] In an embodiment, the lower electrode and the auxiliary electrode may include or consist of the same material and may be formed in the same process operation.

[0022] In an embodiment, the lower electrode and the auxiliary electrode may be spaced apart from each other in a plan view.

[0023] In an embodiment, the auxiliary electrode may be formed at least on a side surface of the power electrode.

[0024] In an embodiment, the upper electrode may be formed to overlap the lower electrode and the auxiliary electrode in a plan view.

[0025] In an embodiment, the upper electrode may be formed to contact a portion of an auxiliary electrode disposed on a side surface of the power electrode.

[0026] In an embodiment, an etch rate of the first conductive layer may be greater than an etch rate of the second conductive layer.

[0027] In an embodiment, the forming of the conductive partition wall may further include forming a third conductive layer on the pixel defining film, and a side surface of the third conductive layer may be formed to protrude more than a side surface of the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other embodiments, advantages, and features of the present disclosure will become apparent by describing an embodiment of the present disclosure in detail with reference to the attached drawings.

[0029] Figure 1A is a combined perspective view of an embodiment of a display device according to the present disclosure.

[0030] Figure 1B is an exploded perspective view of an embodiment of a display device according to the present disclosure.

[0031] Figure 2 is a cross-sectional view of an embodiment of a display module according to the present disclosure.

[0032] Figure 3 is a plan view of an embodiment of a display panel according to the present disclosure.

[0033] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to the present disclosure.

[0034] Figure 5 is a cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0035] Fig. 6A and Figure 6B They are respectively cross-sectional views of embodiments of a display panel according to the present disclosure.

[0036] FIG. 7A to FIG. 9Each of is a cross-sectional view illustrating an embodiment of one operation of a method for manufacturing a display panel according to the present disclosure. DETAILED DESCRIPTION

[0037] The present disclosure may be subject to various changes and may take various forms, so that the illustrative embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present disclosure to a predetermined disclosure form, and should be understood to include all changes, equivalents or substitutes included within the scope of the present disclosure and technology.

[0038] As used herein, when a component (or region, layer or portion, etc.) is also referred to as being "on," "connected to" or "coupled to" another component, this means that the component may be directly disposed on, directly connected to or directly coupled to the other component, or a third component may be disposed between the component and the other component.

[0039] In the present application, "directly disposed" may mean that there is no added layer, film, region, plate, etc. between one part and another part of the layer, film, region, plate, etc. In an embodiment, "directly disposed" may mean "between two layers or two members, disposed without using an additional member such as an adhesive member".

[0040] The same reference numerals refer to the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the components are exaggerated.

[0041] “And / or” includes all of one or more combinations that the associated components can define.

[0042] Terms such as first or second can be used to describe various components, but the components should not be limited by these terms. The above terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component can be named a second component, and similarly, a second component can also be named a first component. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0043] In addition, terms such as "below", "below", "on", and "above" are used to describe the relationship of the components shown in the drawings. The above terms are relative concepts and are described with reference to the directions indicated in the drawings. As used herein, "disposed on..." may refer not only to the case of being disposed on the top of a member, but also to the case of being disposed below a member.

[0044] It should be understood that terms such as “including” or “having” are intended to specify the presence of the features, numbers, steps, operations, components, parts, or any combination thereof described herein, and do not exclude the possibility of adding or existing one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that those terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1A is a combined perspective view of an embodiment of a display device DD according to the present disclosure. Figure 1B is an exploded perspective view of a display device DD according to the present disclosure. Figure 2 is a cross-sectional view of an embodiment of a display module DM according to the present disclosure.

[0048] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, and an external billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer, a laptop computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, and a camera. These are presented only as examples, and other display devices may be employed as long as they do not deviate from the concept of the present disclosure. In the illustrated embodiment, an embodiment in which the display device DD is a smart phone is shown.

[0049] refer to Figure 1A , Figure 1B and Figure 2 , the display device DD can display an image IM in a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a static image and a dynamic image. Figure 1A , a clock window and an icon are shown in an embodiment of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0050] In the illustrated embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of each component are defined based on the direction in which the image IM is displayed. The front surface and the rear surface may face each other in a third direction DR3, and the normal directions of the front surface and the rear surface may be parallel to the third direction DR3. In an embodiment, the directions indicated by the first direction to the third directions DR1, DR2 and DR3 are relative concepts and can be converted to other directions. As used herein, "in a plan view" may mean "when viewed in the third direction DR3".

[0051] like Figure 1B As shown in FIG. 1 , the display device DD in the illustrated embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form an appearance of the display device DD.

[0052] The window WP may include or consist of an optically transparent insulating material. In an embodiment, for example, the window WP may include or consist of glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD.

[0053] The display surface FS may include a transmission area TA and a border area BZA. The transmission area TA may be an optically transparent area. In an embodiment, for example, the transmission area TA may be a region having a visible light transmittance equal to or higher than 90%. The border area BZA may be a region having a relatively low light transmittance compared to the transmission area TA. The border area BZA may define the shape of the transmission area TA. The border area BZA may be adjacent to the transmission area TA and may surround the transmission area TA. This is an exemplary illustration, and in the window WP according to the present disclosure, the border area BZA may be omitted. The window WP may further include at least one functional layer among an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and may not be limited to a specific embodiment.

[0054] The display module DM may be disposed below the window WP. The display module DM may be a component that actually creates the image IM. The image IM created by the display module DM is displayed on the display surface IS of the display module DM and is visible to the user from the outside via the transmission area TA.

[0055] The display module DM includes a display area DA and a non-display area NDA. The display area DA may be an area activated in response to an electrical signal. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the bezel area BZA and is not visible from the outside.

[0056] like Figure 2As shown in the figure, the display module DM in the illustrated embodiment may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD in the embodiment of the present disclosure may further include a protection member disposed under the display panel DP or an anti-reflection member disposed on top of the input sensor INS.

[0057] The display panel DP may be a light-emitting display panel and may not be particularly limited. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel includes an organic light-emitting material, or is composed of an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel includes quantum dots, quantum rods, or micro light-emitting diodes (LEDs), or is composed of quantum dots, quantum rods, or micro light-emitting diodes (LEDs). Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0058] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a light emitting element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be disposed directly on the thin film encapsulation layer TFE. As used herein, "component A is disposed directly on component B" means that a separate layer such as an adhesive layer is not disposed between component A and component B.

[0059] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc. The reference numerals may be defined in the base layer BL in the same manner. Figure 1B A display area DA and a non-display area NDA are described.

[0060] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines or pixel driving circuits, etc.

[0061] The light emitting element layer DP-OLED includes a conductive partition wall and a light emitting element. The light emitting element includes a lower electrode, a light emitting pattern and an upper electrode.

[0062] The thin film encapsulation layer TFE includes a plurality of thin films, some of which are provided to improve optical efficiency, and some of which are provided to protect the organic light emitting element.

[0063] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a conductive layer of a single-layer structure or a multi-layer structure. The input sensor INS may include an insulating layer of a single-layer structure or a multi-layer structure. The input sensor INS may sense the external input using, for example, a capacitive scheme. The operation scheme of the input sensor INS in the present disclosure is not particularly limited. In an embodiment of the present disclosure, the input sensor INS may sense the external input using an electromagnetic induction scheme or a pressure sensing scheme. In another embodiment of the present disclosure, the input sensor INS may be omitted.

[0064] like Figure 1B As shown in , the housing HAU may be combined with the window WP. The housing HAU may be combined with the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0065] The housing HAU may include a material having relatively high rigidity, or may be composed of a material having relatively high rigidity. In an embodiment, for example, the housing HAU may include a plurality of frames and / or a plurality of plates including glass, plastic, or metal or consisting of glass, plastic, or metal, or a plurality of frames and / or a plurality of plates including any combination of glass, plastic, or metal or consisting of any combination of glass, plastic, or metal. The housing HAU may reliably protect the components of the display device DD housed in the internal space from external impacts.

[0066] Figure 3 is a plan view of an embodiment of a display panel DP according to the present disclosure.

[0067] refer to Figure 3 , the display panel DP may include a reference Figure 2 The display area DA and the base layer BL of the non-display area NDA are described.

[0068] The display panel DP may include pixels PX arranged in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and pads PLD disposed in the non-display area NDA.

[0069] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0070] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel among the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0071] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0072] The pad PLD may be a portion for connecting the flexible circuit board. The pad PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pad D-PD may be connected to the corresponding pixel PX via the signal line SGL. In addition, one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0073] In addition, the pad PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (refer to Figure 2 However, the present disclosure may not be limited thereto, and the input pad may be provided at the input sensor INS (reference Figure 2 ) and connected to the pixel pad D-PD and a separate circuit board. In an alternative embodiment, the input sensor INS (reference Figure 2 ), and may not include additional input pads.

[0074] Figure 4 is an enlarged plan view of an embodiment of a portion of a display area DA of a display panel according to the present disclosure.

[0075] Figure 4 is from the display module DM (reference Figure 1B ) display surface IS (reference Figure 1B )Observe the display module DM (reference Figure 1B ) is an enlarged view of a portion of the display area DA in the plane of FIG. 1 , and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0076] refer to Figure 4, the display area DA may include first to third light-emitting areas PXA-R, PXA-G, and PXA-B and non-light-emitting areas NPXA surrounding the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be connected to the light-emitting elements ED1, ED2, and ED3 (reference Figure 5 ) corresponds to the area of ​​light provided by Figure 4 For the convenience of description, only the light emitting elements ED1, ED2 and ED3 are shown in the embodiment (refer to Figure 5 ) among the lower electrodes LE1, LE2 and LE3 of the components. The first to third light emitting areas PXA-R, PXA-G and PXA-B may be based on the direction toward the display module DM (reference Figure 1B ) are distinguished from each other by the color of the light emitted externally.

[0077] The first to third light emitting areas PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. In an embodiment, for example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the embodiments of the first to third color lights are not necessarily limited to the above examples.

[0078] The non-light emitting area NPXA may set the boundaries of the first to third light emitting areas PXA-R, PXA-G, and PXA-B, and may prevent color mixing between the first to third light emitting areas PXA-R, PXA-G, and PXA-B.

[0079] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may include a plurality of first light-emitting areas, a plurality of second light-emitting areas, and a plurality of third light-emitting areas that are repeatedly arranged in a predetermined arrangement within the display area DA, respectively. In an embodiment, for example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting area PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the "second group" may include a plurality of first groups and a plurality of second groups, respectively, and the "first group" and the "second group" may be alternately arranged with each other along the second direction DR2.

[0080] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0081] Figure 4The arrangement of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B in the embodiment is shown, and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged in various forms without being limited thereto. In the embodiment, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have a Figure 4 As shown in In an alternative embodiment, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have a stripe arrangement or a diamond arrangement. Layout form.

[0082] In a plan view, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes. In an embodiment, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have shapes such as polygons, circles, or ellipses. For example, Figure 4 It is shown that the first and third light emitting regions PXA-R and PXA-B have a square shape (or a diamond shape) in a plan view and the second light emitting region PXA-G has an octagonal shape in the embodiment.

[0083] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as one another in a plan view, or at least some of them may have different shapes. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shapes as each other in a plan view and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B in the embodiment are shown.

[0084] In a plan view, at least some of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different areas. In an embodiment, the area of ​​the first light-emitting area PXA-R emitting red light may be larger than the area of ​​the second light-emitting area PXA-G emitting green light, and may be smaller than the area of ​​the third light-emitting area PXA-B emitting blue light. However, the size relationship between the areas of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B based on the color of the emitted light may not be limited thereto, and may depend on the display module DM (refer to Figure 2 ) is designed to be various. In addition, without being limited thereto, in a plan view, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same area.

[0085] In an embodiment, the display module DM (refer to Figure 1BThe shapes, areas or arrangements of the first to third light emitting areas PXA-R, PXA-G and PXA-B in the display module DM (reference Figure 1B ) may be designed in various ways depending on the size and components of the Figure 4 The shapes, areas or arrangements etc. in the embodiments shown in FIG.

[0086] The lower electrodes LE1, LE2 and LE3 may be connected to the above-mentioned circuit element layer DP-CL via connection contact holes CNT-R, CNT-G and CNT-B, respectively (refer to Figure 2 ) in the driving circuit of the pixel. The connection contact holes CNT-R, CNT-G and CNT-B may include a first connection contact hole CNT-R, a second connection contact hole CNT-G and a third connection contact hole CNT-B. The first connection contact hole CNT-R may be defined as a region where the first lower electrode LE1 is connected to the driving circuit of the corresponding pixel, the second connection contact hole CNT-G may be defined as a region where the second lower electrode LE2 is connected to the driving circuit of the corresponding pixel, and the third connection contact hole CNT-B may be defined as a region where the third lower electrode LE3 is connected to the driving circuit of the corresponding pixel.

[0087] The connection contact holes CNT-R, CNT-G, and CNT-B may be spaced apart from the light emitting regions PXA-R, PXA-G, and PXA-B defined in the lower electrodes LE1, LE2, and LE3, respectively. However, this is only one of the embodiments, and the connection contact holes CNT-R, CNT-G, and CNT-B may be disposed to overlap the light emitting regions PXA-R, PXA-G, and PXA-B defined in the lower electrodes LE1, LE2, and LE3, respectively.

[0088] Figure 4 Auxiliary electrodes AXE-R, AXE-G, and AXE-B and power supply electrodes PL-R, PL-G, and PL-B disposed in the non-emission area NPXA are shown.

[0089] The auxiliary electrodes AXE-R, AXE-G, and AXE-B may include the same material as that of the lower electrodes LE1, LE2, and LE3, or be composed of the same material as that of the lower electrodes LE1, LE2, and LE3. The auxiliary electrodes AXE-R, AXE-G, and AXE-B may be formed via the same process operation as that of the lower electrodes LE1, LE2, and LE3. The auxiliary electrodes AXE-R, AXE-G, and AXE-B may be electrically insulated from the lower electrodes LE1, LE2, and LE3 by being disposed to be spaced apart from the lower electrodes LE1, LE2, and LE3 in a plan view.

[0090] Upper electrodes UE1, UE2 and UE3 (reference Figure 5) are electrically connected to the power supply electrodes PL-R, PL-G and PL-B, respectively, with the auxiliary electrodes AXE-R, AXE-G and AXE-B interposed therebetween, and a detailed description thereof will be provided later.

[0091] Figure 5 is a cross-sectional view of an embodiment of a display panel DP according to the present disclosure. Fig. 6A and Figure 6B They are respectively cross-sectional views of embodiments of the display panel DP according to the present disclosure.

[0092] Figure 5 Shown along Figure 4 The cross section is taken along line II'. Fig. 6A and Figure 6B They are shown along Figure 4 The cross section is taken along line II-II'.

[0093] refer to Figures 5 to 6B , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a light emitting element layer DP-OLED and a thin film encapsulation layer TFE.

[0094] The base layer BL may include a synthetic resin film. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0095] refer to Fig. 6A , at least one inorganic layer is disposed on the top surface of the base layer BL. The buffer layer BFL improves the bonding strength between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0096] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns or signal lines, etc. The insulating layers, semiconductor layers and conductive layers are formed via schemes such as coating or deposition, etc. Thereafter, the insulating layers, semiconductor layers and conductive layers may be selectively patterned by photolithography and etching. With this scheme, semiconductor patterns, conductive patterns or signal lines, etc. included in the circuit element layer DP-CL and the light emitting element layer DP-OLED are formed.

[0097] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon, or consist of polycrystalline silicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide, or consist of amorphous silicon or metal oxide.

[0098] Fig. 6AOnly a portion of the semiconductor pattern is shown, and the semiconductor pattern may be further arranged in a plurality of light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may be arranged in a predetermined order across a plurality of light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region having a relatively high doping concentration and a second region having a relatively low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a first region doped with a P-type dopant.

[0099] The first region has a greater conductivity than the second region and substantially functions as an electrode or a signal line. The second region substantially corresponds to an active portion (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active portion of a transistor, another portion thereof may be a source or drain of the transistor, and another portion thereof may be a conductive region.

[0100] like Fig. 6A As shown in , the source S1 , the active portion A1 , and the drain D1 of the transistor TR1 are formed of a semiconductor pattern. Fig. 6A A portion of a signal transmission region SCL formed of a semiconductor pattern is shown Although not separately shown, the signal transmission region SCL may be connected to the drain D1 of the transistor TR1 in a plan view.

[0101] The first to sixth insulating layers 10 to 60 are disposed on the buffer layer BFL. The first to sixth insulating layers 10 to 60 may be inorganic layers or organic layers. The gate G1 is disposed on the first insulating layer 10. The upper electrode UE may be disposed on the second insulating layer 20. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL via a contact hole CNT-1 extending through the first to third insulating layers 10 to 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the first connection electrode CNE1. The fifth and sixth insulating layers 50 and 60 may be disposed on the fourth insulating layer 40. In an embodiment, the fifth and sixth insulating layers 50 and 60 may be organic layers. In the comparison to be performed later FIG. 7A to FIG. 9 In the description of the manufacturing method, the buffer layer BFL and the first to fifth insulating layers 10 , 20 , 30 , 40 , and 50 may also be referred to as a first circuit layer DP-CL1 , and the sixth insulating layer 60 may also be referred to as a second circuit layer 60 .

[0102] The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 extending through the fourth insulating layer 40 and the fifth insulating layer 50.

[0103] refer to Fig. 6A , the power electrode PL and the auxiliary electrode AXE-R may be disposed on the fifth insulating layer 50 of the non-light emitting area NPXA adjacent to the first light emitting area PXA-R.

[0104] A bias voltage may be applied to the power electrode PL. The power electrode PL may have a single-layer structure or a multi-layer structure. In an embodiment, for example, the power electrode PL may include a first layer PL1, a second layer PL2, and a third layer PL3. In an embodiment, for example, the first layer PL1, the second layer PL2, and the third layer PL3 may be ITO, Ag, and ITO, respectively. The side surfaces of the first layer PL1 and the third layer PL3 may protrude more than the side surface of the second layer PL2. The side surface of the third layer PL3 may protrude more than the side surface of the second layer PL2 to form a tip. Fig. 6A , the power electrode PL is illustrated as having a three-layer structure and forming a pointed tip, but the stacking structure and shape of the power electrode PL are not limited thereto.

[0105] The auxiliary electrode AXE-R may be formed through the same process as that of the lower electrode LE1 to be described later and may include or consist of the same material as that of the lower electrode LE1. The auxiliary electrode AXE-R may be disposed on a side surface of the power electrode PL.

[0106] The upper electrode UE1 to be described later may extend from the first light emitting region PXA-R and be electrically connected to the power electrode PL. Specifically, the upper electrode UE1 may be electrically connected to the power electrode PL with the auxiliary electrode AXE-R interposed therebetween. The upper electrode UE1 may be disposed in contact with the auxiliary electrode AXE-R disposed on the side surface of the power electrode PL. Accordingly, the upper electrode UE1 may receive a bias voltage applied to the power electrode PL.

[0107] Since the upper electrode UE1 is connected to the power electrode PL with the auxiliary electrode AXE-R interposed therebetween, electrical contact stability is improved, thereby improving the brightness of the display panel DP and reducing defects.

[0108] In addition, a process for connecting the upper electrode UE1 and the power electrode PL, which makes the upper electrode UE1 contact the side surface of the conductive partition wall CPW and defines a separate contact hole to connect the upper electrode UE1 to the power electrode PL, may be omitted, thereby simplifying the process.

[0109] The dummy portion DMP1-1 may be disposed on the power electrode PL. The dummy portion DMP1-1 may include a first dummy portion L0 formed together with the lower electrode LE1 and the auxiliary electrode AXE-R and including or consisting of the same material as the lower electrode LE1 and the auxiliary electrode AXE-R, a second dummy portion L1 formed together with the light emitting pattern EP1 and including or consisting of the same material as the light emitting pattern EP1, a third dummy portion L2 formed together with the upper electrode UE1 and including or consisting of the same material as the upper electrode UE1, and a fourth dummy portion L3 formed together with the capping pattern CP1 and including or consisting of the same material as the capping pattern CP1.

[0110] The power electrode PL and the dummy part DMP1 - 1 may be covered by the inorganic layer LIL1 of the encapsulation layer TFE.

[0111] The light emitting element layer DP-OLED may be disposed on the circuit element layer DP-CL. In the illustrated embodiment, the light emitting element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, an insulating film ISL, a conductive partition wall CPW, dummy patterns DMP1, DMP2, and DMP3, and a dummy inorganic film LIL2-D.

[0112] The light emitting elements ED1, ED2 and ED3 include a first light emitting element ED1, a second light emitting element ED2 and a third light emitting element ED3. The first light emitting element ED1 may include a first lower electrode LE1, a first light emitting pattern EP1 and a first upper electrode UE1, the second light emitting element ED2 may include a second lower electrode LE2, a second light emitting pattern EP2 and a second upper electrode UE2, and the third light emitting element ED3 may include a third lower electrode LE3, a third light emitting pattern EP3 and a third upper electrode UE3. The light emitting patterns EP1, EP2 and EP3 may also be referred to as light emitting layers.

[0113] The first to third lower electrodes LE1, LE2, and LE3 may be provided in a plurality of patterns. Hereinafter, the description will focus on the first lower electrode LE1, and the description of the first lower electrode LE1 may be equally applied to the second and third lower electrodes LE2 and LE3.

[0114] The first lower electrode LE1 may be disposed on the sixth insulating layer 60 of the circuit element layer DP-CL. The first lower electrode LE1 may be connected to the second connection electrode CNE2 via a connection contact hole CNT-3 defined through the sixth insulating layer 60. Accordingly, the first lower electrode LE1 may be electrically connected to the signal transmission region SCL via the first connection electrode CNE1 and the second connection electrode CNE2, and electrically connected to the corresponding circuit element. Fig. 6A The connecting contact hole CNT-3 can be connected with Figure 4 Corresponding to the first connection contact hole CNT-R in.

[0115] The first lower electrode LE1 may be a (semi) transparent electrode or a reflective electrode. In the illustrated embodiment, the first lower electrode LE1 may include a multilayer structure. In an embodiment, for example, the first lower electrode LE1 may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer.

[0116] The second layer may include a metal material, or be composed of a metal material. In an embodiment, for example, the second layer may be a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any combination thereof, or composed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any combination thereof.

[0117] Each of the first layer and the third layer may include a transparent conductive oxide, or may consist of a transparent conductive oxide. In an embodiment, for example, each of the first layer and the third layer may include a transparent conductive oxide selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO) or at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO) composed of at least one of the group.

[0118] The sacrificial patterns SP1 , SP2 , and SP3 may include a first sacrificial pattern SP1 disposed on a top surface of the first lower electrode LE1 , a second sacrificial pattern SP2 disposed on a top surface of the second lower electrode LE2 , and a third sacrificial pattern SP3 disposed on a top surface of the third lower electrode LE3 .

[0119] A first lower opening OP1-L exposing a portion of the top surface of the first lower electrode LE1 may be defined in the first sacrificial pattern SP1, a second lower opening OP2-L exposing a portion of the top surface of the second lower electrode LE2 may be defined in the second sacrificial pattern SP2, and a third lower opening OP3-L exposing a portion of the top surface of the third lower electrode LE3 may be defined in the third sacrificial pattern SP3.

[0120] In the illustrated embodiment, each of the first to third sacrificial patterns SP1, SP2, and SP3 may include or consist of an amorphous transparent conductive oxide. According to the present disclosure, during the etching process of the first sacrificial pattern SP1 for defining the first lower opening OP1-L therein, the first lower electrode LE1 may be prevented from being etched and damaged together, and the description thereof may also be similarly applied to the second sacrificial pattern SP2 and the third sacrificial pattern SP3.

[0121] The insulating film ISL may be disposed on the sixth insulating layer 60 of the circuit element layer DP-CL. The insulating film ISL may cover the first to third lower electrodes LE1, LE2, and LE3 and the first to third sacrificial patterns SP1, SP2, and SP3. That is, the insulating film ISL may cover the top surface of each of the first to third sacrificial patterns SP1, SP2, and SP3. Here, the insulating film ISL may also be referred to as a pixel defining film, a pixel defining layer, or an insulating layer.

[0122] like Figure 5 As shown in , first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the insulating film ISL. The first light emitting opening OP1-E may correspond to the first lower opening OP1-L of the first sacrificial pattern SP1, the second light emitting opening OP2-E may correspond to the second lower opening OP2-L of the second sacrificial pattern SP2, and the third light emitting opening OP3-E may correspond to the third lower opening OP3-L of the third sacrificial pattern SP3.

[0123] The first to third light emitting openings OP1-E, OP2-E, and OP3-E may also be referred to as pixel openings. The pixel openings may refer to areas exposed by the pixel defining layer ISL. Figure 6B The pixel opening may include the first light emitting region PXA-R, and may include a portion of the non-light emitting region NPXA where the power electrode PL is disposed.

[0124] In the illustrated embodiment, in a plan view, the first light emitting opening OP1-E may overlap with the first lower opening OP1-L, and the area of ​​the first light emitting opening OP1-E may be smaller than the area of ​​the first lower opening OP1-L. In other words, the inner surface of the insulating film ISL in which the first light emitting opening OP1-E is defined may be closer to the center of the first lower electrode LE1 than the inner surface of the first sacrificial pattern SP1 in which the first lower opening OP1-L is defined to the center of the first lower electrode LE1. In this regard, a portion of the insulating film ISL closer to the center of the first lower electrode LE1 than the inner surface of the first sacrificial pattern SP1 in which the first lower opening OP1-L is defined may define a tip. The description of the first light emitting opening OP1-E and the first lower opening OP1-L may be similarly applied to the second light emitting opening OP2-E and the second lower opening OP2-L and the third light emitting opening OP3-E and the third lower opening OP3-L.

[0125] The insulating film ISL may include an inorganic insulating material (eg, silicon nitride (SiN x )), or inorganic insulating materials (e.g., silicon nitride (SiN x The insulating film ISL may be disposed between the first to third lower electrodes LE1, LE2, and LE3 and the conductive partition wall CPW, and prevent the first to third lower electrodes LE1, LE2, and LE3 and the conductive partition wall CPW from being electrically connected to each other.

[0126] The conductive partition wall CPW may be disposed on the insulating film ISL. First to third upper openings OP1-U, OP2-U, and OP3-U may be defined in the conductive partition wall CPW. The first upper opening OP1-U may correspond to the first light emitting opening OP1-E, the second upper opening OP2-U may correspond to the second light emitting opening OP2-E, and the third upper opening OP3-U may correspond to the third light emitting opening OP3-E.

[0127] In the illustrated embodiment, the conductive partition wall CPW may include a first conductive layer CDL1 and a second conductive layer CDL2. Each of the first conductive layer CDL1 and the second conductive layer CDL2 may include a conductive material, or be composed of a conductive material. The first conductive layer CDL1 may be disposed on the insulating film ISL and may have a first conductivity and a first thickness. The second conductive layer CDL2 may be disposed on the first conductive layer CDL1, have a second conductivity lower than the first conductivity, and have a second thickness less than the first thickness.

[0128] The etch rate of the first conductive layer CDL1 may be greater than that of the second conductive layer CDL2. That is, the first conductive layer CDL1 may include or consist of a material having a higher etch selectivity than that of the second conductive layer CDL2.

[0129] In an embodiment, each of the first conductive layer CDL1 and the second conductive layer CDL2 may include a metal material, or be composed of a metal material. In addition, in an embodiment, the second conductive layer CDL2 may include a material having a lower reflectivity than the first conductive layer CDL1 or be composed of a material having a lower reflectivity than the first conductive layer CDL1, and the reflectivity at the top surface of the second conductive layer CDL2 forming the top surface US_CPW of the conductive partition wall CPW may be significantly reduced, thereby improving the display quality of the display panel DP. In an embodiment, for example, the first conductive layer CDL1 may include aluminum (Al), or be composed of aluminum (Al), and the second conductive layer CDL2 may include titanium (Ti), or be composed of titanium (Ti). However, the materials of the first conductive layer CDL1 and the second conductive layer CDL2 are not limited to specific embodiments.

[0130] In the illustrated embodiment, in a plan view, the first upper opening OP1-U defined in the second conductive layer CDL2 may overlap with the first upper opening OP1-U defined in the first conductive layer CDL1, and an area of ​​the first upper opening OP1-U defined in the second conductive layer CDL2 may be smaller than an area of ​​the first upper opening OP1-U defined in the first conductive layer CDL1.

[0131] like Fig. 6A As shown in , in the cross section, the first upper opening OP1-U may include a first region OP1-U1 defined by an inner surface of the first conductive layer CDL1 and a second region OP1-U2 defined by an inner surface of the second conductive layer CDL2. In the cross section, the width of the first region OP1-U1 may be greater than the width of the second region OP1-U2. In the cross section, the inner surface of the second conductive layer CDL2 defining the second region OP1-U2 may be closer to the center of the first lower electrode LE1 than the inner surface of the first conductive layer CDL1 defining the first region OP1-U1 is to the center of the first lower electrode LE1. In the present disclosure, in the conductive partition wall CPW, a portion of the second conductive layer CDL2 that is closer to the center of the first lower electrode LE1 than the inner surface of the first conductive layer CDL1 defining the first region OP1-U1 may be defined as a tip.

[0132] In an embodiment, in a plan view, an area of ​​the first region OP1-U1 defined in the first conductive layer CDL1 may be greater than an area of ​​the first light emitting opening OP1-E defined in the insulating film ISL, and the first conductive layer CDL1 may expose a portion of the top surface of the insulating film ISL through the first region OP1-U1.

[0133] Each of the first to third light emitting patterns EP1, EP2, and EP3 may be disposed on a corresponding lower electrode among the first to third lower electrodes LE1, LE2, and LE3. The first light emitting pattern EP1 may be disposed on the first upper electrode UE1, the second light emitting pattern EP2 may be disposed on the second upper electrode UE2, and the third light emitting pattern EP3 may be disposed on the third upper electrode UE3. In an embodiment, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0134] Each of the first to third light emitting patterns EP1, EP2, and EP3 may include a light emitting layer including a light emitting material or consisting of a light emitting material. Each of the first to third light emitting patterns EP1, EP2, and EP3 may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light emitting layer and the corresponding lower electrode among the first to third lower electrodes LE1, LE2, and LE3, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light emitting layer. Each of the first to third light emitting patterns EP1, EP2, and EP3 may also be referred to as an “organic pattern”.

[0135] According to the present disclosure, the first to third light-emitting patterns EP1, EP2, and EP3 may be patterned by a tip defined in the conductive partition wall CPW. The first light-emitting pattern EP1 may be disposed inside the first lower opening OP1-L, the first light-emitting opening OP1-E, and the first upper opening OP1-U. The first light-emitting pattern EP1 may cover a portion of the top surface of the insulating film ISL exposed by the first upper opening OP1-U. The second light-emitting pattern EP2 may be disposed inside the second lower opening OP2-L, the second light-emitting opening OP2-E, and the second upper opening OP2-U. The second light-emitting pattern EP2 may cover a portion of the top surface of the insulating film ISL exposed by the second upper opening OP2-U. The third light-emitting pattern EP3 may be disposed inside the third lower opening OP3-L, the third light-emitting opening OP3-E, and the third upper opening OP3-U. The third light-emitting pattern EP3 may cover a portion of the top surface of the insulating film ISL exposed by the third upper opening OP3-U.

[0136] According to the present disclosure, the plurality of first light emitting patterns EP1 may be patterned in units of pixels and deposited through the tips defined in the conductive partition wall CPW. That is, the plurality of first light emitting patterns EP1 may be formed together using an open mask, but may be easily separated from each other in units of pixels by the conductive partition wall CPW.

[0137] When a plurality of first light emitting patterns EP1 are patterned using a separate mask (e.g., a fine metal mask (FMM)), a spacer for support protruding from the partition wall should be provided to support the separate mask. In addition, since the separate mask is separated from the substrate surface where patterning is performed by the height of the partition wall and the spacer, there may be a limit to the improvement of resolution.

[0138] In addition, since the mask contacts the spacer, foreign matter may remain on the spacer after the patterning process of the plurality of first light emitting patterns EP1, and the spacer may be damaged by scratches of the mask. Accordingly, a defective display panel may be formed.

[0139] In the present disclosure, since the plurality of first light emitting patterns EP1 are patterned without a separate mask contacting the internal components of the display panel DP, a display panel DP having improved reliability due to a reduced defect rate can be provided. Specifically, when manufacturing a large-area display panel DP, the process cost can be reduced by omitting the manufacture of a large-area mask, and a display panel DP that is not affected by defects occurring in the large-area mask and thus has improved reliability can be provided.

[0140] exist Fig. 6A , an embodiment in which the first light emitting pattern EP1 does not contact the inner surface of the first conductive layer CDL1 in which the first upper opening OP1-U is defined is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the first light emitting pattern EP1 may contact the inner surface of the first conductive layer CDL1 in which the first upper opening OP1-U is defined.

[0141] The above description of the first light emitting pattern EP1 may be equally applied to the second light emitting pattern EP2 and the third light emitting pattern EP3 .

[0142] Each of the first to third upper electrodes UE1, UE2, and UE3 may be disposed on a corresponding light emitting pattern among the first to third light emitting patterns EP1, EP2, and EP3. The first upper electrode UE1 may be disposed on the first light emitting pattern EP1, the second upper electrode UE2 may be disposed on the second light emitting pattern EP2, and the third upper electrode UE3 may be disposed on the third light emitting pattern EP3. The first to third upper electrodes UE1, UE2, and UE3 may be patterned by a tip defined in the conductive partition wall CPW.

[0143] In the present disclosure, the first upper electrode UE1 may contact an inner surface of the first region OP1 -U1 of the first conductive layer CDL1 in which the first upper opening OP1 -U is defined.

[0144] According to the present disclosure, since the first to third upper electrodes UE1, UE2, and UE3 are not provided in the form of a common layer overlapping all the first to third light emitting patterns EP1, EP2, and EP3, lateral leakage current occurring through the common layer may not occur.

[0145] The capping patterns CP1, CP2, and CP3 may include a first capping pattern CP1 disposed on the first upper electrode UE1 inside the first upper opening OP1-U, a second capping pattern CP2 disposed on the second upper electrode UE2 inside the second upper opening OP2-U, and a third capping pattern CP3 disposed on the third upper electrode UE3 inside the third upper opening OP3-U. The first to third capping patterns CP1, CP2, and CP3 may be patterned by a tip defined in the conductive partition wall CPW. In another embodiment of the present disclosure, the first to third capping patterns CP1, CP2, and CP3 may be omitted.

[0146] although Fig. 6A An embodiment in which the first capping pattern CP1 does not contact the inner surface of the first conductive layer CDL1 in which the first upper opening OP1-U is defined is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the first capping pattern CP1 may be formed to contact the inner surface of the first conductive layer CDL1 in which the first upper opening OP1-U is defined.

[0147] Return to reference Figure 5 , the dummy patterns DMP1, DMP2, and DMP3 may be disposed on the conductive partition wall CPW. The dummy patterns DMP1, DMP2, and DMP3 may include a first dummy pattern DMP1, a second dummy pattern DMP2, and a third dummy pattern DMP3.

[0148] The first dummy pattern DMP1 may be disposed on the top surface US_CPW of the conductive partition wall CPW. The first dummy pattern DMP1 may cover at least a portion of an inner surface of the second conductive layer CDL2 defining the first upper opening OP1-U therein. The first dummy pattern DMP1 may be at least partially covered by the first lower encapsulation inorganic film LIL1.

[0149] like Fig. 6AAs shown in , the first dummy pattern DMP1 may include a first organic layer L1, a first conductive layer L2, and a first capping layer L3. The first organic layer L1 may be formed via the same process as the process of the first light emitting pattern EP1, have the same structure as the structure of the first light emitting pattern EP1, and may include the same material as the material of the first light emitting pattern EP1 or consist of the same material as the material of the first light emitting pattern EP1. The first organic layer L1 may be spaced apart from the first to third light emitting patterns EP1, EP2, and EP3. When the first light emitting pattern EP1 is formed together, the first organic layer L1 may correspond to a residue separated from the first light emitting pattern EP1 by the conductive partition wall CPW. The first conductive layer L2 may be disposed on the first organic layer L1. The first conductive layer L2 may be formed via the same process as the process of the first upper electrode UE1, have the same structure as the structure of the first upper electrode UE1, and may include the same material as the material of the first upper electrode UE1 or consist of the same material as the material of the first upper electrode UE1. The first conductive layer L2 may be spaced apart from the first to third upper electrodes UE1, UE2, and UE3. When the first upper electrode UE1 is formed together, the first conductive layer L2 may correspond to a residue separated from the first upper electrode UE1 by the conductive partition wall CPW. The first capping layer L3 may be disposed on the first conductive layer L2. The first capping layer L3 may be formed via the same process as that of the first capping pattern CP1, have the same structure as that of the first capping pattern CP1, and may include the same material as that of the first capping pattern CP1 or be composed of the same material as that of the first capping pattern CP1. The first capping layer L3 may be spaced apart from the first to third capping patterns CP1, CP2, and CP3. When the first capping pattern CP1 is formed together, the first capping layer L3 may correspond to a residue separated from the first capping pattern CP1 by the conductive partition wall CPW.

[0150] The second dummy pattern DMP2 may include a first dummy portion DPP1 and a second dummy portion DPP2.

[0151] A portion of the first dummy portion DPP1 may be disposed on the first dummy pattern DMP1 on the top surface of the conductive partition wall CPW. The second dummy portion DPP2 may be spaced apart from the first dummy portion DPP1 and may be disposed on the first dummy pattern DMP1 on the top surface of the conductive partition wall CPW. Each of the first dummy portion DPP1 and the second dummy portion DPP2 of the second dummy pattern DMP2 may include a second organic layer, a second conductive layer, and a second capping layer. The description of the first organic layer L1, the first conductive layer L2, and the first capping layer L3 may be similarly applied to the second organic layer, the second conductive layer, and the second capping layer. The second organic layer may include the same material as the material of the second light emitting pattern EP2 or consist of the same material as the material of the second light emitting pattern EP2, and may be spaced apart from the first to third light emitting patterns EP1, EP2, and EP3. The second conductive layer may be disposed on the second organic layer. The second conductive layer may include the same material as the material of the second upper electrode UE2 or consist of the same material as the material of the second upper electrode UE2, and may be spaced apart from the first to third upper electrodes UE1, UE2, and UE3. The second capping layer may be disposed on the second conductive layer. The second capping layer may include or consist of the same material as the second capping pattern CP2 and may be spaced apart from the first to third capping patterns CP1, CP2, and CP3.

[0152] A portion of the third dummy pattern DMP3 may be disposed on side surfaces of the first dummy pattern DMP1, the second dummy portion DPP2, and the second conductive layer CDL2. A portion of the third dummy pattern DMP3 may be disposed on the first and second dummy patterns DMP1 and DMP2 on the top surface of the conductive partition wall CPW.

[0153] The third dummy pattern DMP3 may include a third organic layer including or consisting of the same material as the third light emitting pattern EP3, a third conductive layer including or consisting of the same material as the third upper electrode UE3 and disposed on the third organic layer, and a third capping layer including or consisting of the same material as the third capping pattern CP3 and disposed on the third conductive layer. The description of the first organic layer L1, the first conductive layer L2, and the first capping layer L3 may be similarly applied to the third organic layer, the third conductive layer, and the third capping layer.

[0154] The dummy inorganic film LIL2-D may be disposed between the second dummy portion DPP2 and the third dummy pattern DMP3. The dummy inorganic film LIL2-D may be disposed on the first lower encapsulation inorganic film LIL1. The dummy inorganic film LIL2-D may overlap the first lower encapsulation inorganic film LIL1.

[0155] The thin film encapsulation layer TFE may be disposed on the light emitting element layer DP-OLED and may include a first lower encapsulation inorganic film LIL1, a second lower encapsulation inorganic film LIL2, a third lower encapsulation inorganic film LIL3, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0156] The first lower encapsulation inorganic film LIL1 may be formed on the conductive partition wall CPW and the first upper electrode UE1, and may be disposed inside the first upper opening OP1-U. Specifically, the first lower encapsulation inorganic film LIL1 may cover the first dummy pattern DMP1 and the first upper electrode UE1 (or the first capping pattern CP1). In addition, the first lower encapsulation inorganic film LIL1 may contact the inner surface of the first conductive layer CDL1 in which the first upper opening OP1-U is defined.

[0157] The second lower encapsulation inorganic film LIL2 may be disposed on the second upper electrode UE2 and the first dummy portion DPP1 of the second dummy pattern DMP2, and may be disposed inside the second upper opening OP2-U. Specifically, the second lower encapsulation inorganic film LIL2 may cover the second upper electrode UE2 (or the second capping pattern CP2). In addition, the second lower encapsulation inorganic film LIL2 may contact the inner surface of the first conductive layer CDL1 in which the second upper opening OP2-U is defined. The second lower encapsulation inorganic film LIL2 may overlap with the inner surface of the first lower encapsulation inorganic film LIL1 in which the first encapsulation opening OP1-IL is defined. A portion of the second lower encapsulation inorganic film LIL2 may be disposed on the first lower encapsulation inorganic film LIL1 above the top surface of the conductive partition wall CPW.

[0158] The third lower encapsulation inorganic film LIL3 may be disposed on the third upper electrode UE3 and the third dummy pattern DMP3 and may be disposed inside the third upper opening OP3-U. Specifically, the third lower encapsulation inorganic film LIL3 may cover the third upper electrode UE3 (or the third capping pattern CP3).

[0159] In an embodiment, each of the first lower encapsulation inorganic film LIL1 , the second lower encapsulation inorganic film LIL2 , and the third lower encapsulation inorganic film LIL3 may also contact the bottom surface of the second conductive layer CDL2 exposed from the first conductive layer CDL1 .

[0160] The first to third lower encapsulation inorganic films LIL1, LIL2 and LIL3 and the upper encapsulation inorganic film UIL can protect the light emitting element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL can protect the light emitting element layer DP-OLED from foreign substances such as dust particles.

[0161] refer to Figure 6B , the conductive partition wall CPW in the embodiment may include a first conductive layer CDL1, a second conductive layer CDL2, and a third conductive layer CDL3. The third conductive layer CDL3 may be disposed below the first conductive layer CDL1. The third conductive layer CDL3 may have a third conductivity lower than the first conductivity and a third thickness less than the first thickness.

[0162] The third conductive layer CDL3 may include a conductive material, or be composed of a conductive material. In an embodiment, the third conductive layer CDL3 may include the same material as the material of the second conductive layer CDL2 or be composed of the same material as the material of the second conductive layer CDL2, and the first conductive layer CDL1 may include a material different from the materials of the second conductive layer CDL2 and the third conductive layer CDL3 or be composed of a material different from the materials of the second conductive layer CDL2 and the third conductive layer CDL3. In an embodiment, the second conductive layer CDL2 and the third conductive layer CDL3 may include titanium (Ti) or be composed of titanium (Ti), and the first conductive layer CDL1 may include aluminum (Al) or be composed of aluminum (Al). For example, compared with the adhesion of the second conductive layer CDL2 to the insulating layer ISL, the third conductive layer CDL3 may include a material having a greater adhesion to the insulating layer ISL, or be composed of a material having a greater adhesion to the insulating layer ISL. Accordingly, the conductive partition wall CPW can be bonded to the insulating film ISL with a large adhesion, and the process reliability can be improved.

[0163] The etching rate of the third conductive layer CDL3 may be lower than that of the first conductive layer CDL1. In other words, the first conductive layer CDL1 may include or consist of a material having a higher etching selectivity than that of the third conductive layer CDL3.

[0164] FIG. 7A to FIG. 9 Each of is a cross-sectional view illustrating an embodiment of one operation of a method for manufacturing a display panel according to the present disclosure. FIG. 7A to FIG. 9 Shown with Fig. 6A The corresponding part.

[0165] Reference above Figures 5 to 6B The same components described can also be applied to FIG. 7A to FIG. 9 .

[0166] The method for manufacturing a display panel according to the present disclosure may include preparing a base layer BL, forming a circuit element layer DP-CL on the base layer BL, forming a light emitting element layer DP-OLED on the circuit element layer DP-CL, and forming an encapsulation layer TFE on the light emitting element layer DP-OLED.

[0167] Fig. 7A and Figure 7B The preparation of the base layer BL and the formation of the circuit element layer DP-CL on the base layer BL are shown.

[0168] In the preparation of the base layer BL, the above-mentioned Figures 5 to 6B The content described in the base layer BL.

[0169] The formation of the circuit element layer DP-CL may include preparing a first circuit layer DP-CL1, forming a power electrode PL on the first circuit layer DP-CL1, and forming a second circuit layer 60 defining an opening therein to expose the power electrode PL on the first circuit layer DP-CL1.

[0170] The first circuit layer DP-CL1 may be formed across the base layer BL and may include the above Fig. 6A The buffer layer, the first insulating layer to the fifth insulating layer, and the plurality of components disposed between the buffer layer and the fifth insulating layer described in Fig. 7A and Figure 7B In the figure, for convenience, the above components are collectively illustrated as a first circuit layer DP-CL1.

[0171] refer to Fig. 7A , the second connection electrode CNE2 and the power electrode PL may be formed on the first circuit layer DP-CL1 to be spaced apart from each other. The power electrode PL may include a first layer PL1, a second layer PL2, and a third layer PL3. However, the stacking structure of the power electrode PL is not limited thereto. Figures 5 to 6B The contents described in can be similarly applied to the power supply electrode PL.

[0172] refer to Figure 7B , the second circuit layer 60 may be formed on the first circuit layer DP-CL1. The second circuit layer 60 may define an opening OP-60 therein. The opening OP-60 of the second circuit layer 60 may expose the power electrode PL. The first circuit layer DP-CL1 may include a connection contact hole CNT-3. The connection contact hole CNT-3 may expose at least a portion of the second connection electrode CNE2.

[0173] FIG. 8A to FIG. 8D The formation of the light emitting element layer DP-OLED on the circuit element layer DP-CL is shown.

[0174] The formation of the light emitting element layer DP-OLED may include forming a lower electrode LE1 and an auxiliary electrode AXE-R, forming a pixel defining film ISL covering a portion of the lower electrode LE1, forming a conductive partition wall CPW on the pixel defining film ISL, forming a light emitting pattern EP1 on the lower electrode LE1, and forming an upper electrode UE1 on the light emitting pattern EP1.

[0175] refer to Fig. 8A The lower electrode LE1 may be formed on the second circuit layer 60 while filling the connection contact hole CNT-3, and may contact and be electrically connected to the second connection electrode CNE2. The auxiliary electrode AXE-R may include or consist of the same material as that of the lower electrode LE1, and may be formed in the same process operation.

[0176] The auxiliary electrode AXE-R may be spaced apart from the lower electrode LE1. The auxiliary electrode AXE-R may be formed in the opening OP-60 of the second circuit layer 60. Fig. 8A , the auxiliary electrode AXE-R is shown to cover the entire opening OP-60, but the present disclosure is not limited thereto. In an embodiment, for example, the auxiliary electrode AXE-R may be formed without covering a portion of the first circuit layer DP-CL1 exposed by the opening OP-60.

[0177] The auxiliary electrode AXE-R may be formed directly on the power electrode PL. Specifically, the auxiliary electrode AXE-R may be formed to cover at least a portion of the side surface of the power electrode PL. In the formation of the lower electrode LE1 and the auxiliary electrode AXE-R, a first dummy portion L0 including or consisting of the same material as that of the lower electrode LE1 and the auxiliary electrode AXE-R may be formed on the power electrode PL. The power electrode PL and the auxiliary electrode AXE-R may be electrically connected to each other.

[0178] refer to Figure 8B , a first sacrificial pattern SP1 and a pixel defining film ISL may be formed on the lower electrode LE1. The pixel defining film ISL may define a pixel opening OP1-E (refer to Fig. 9 ).

[0179] refer to Figure 8C , a conductive partition wall CPW may be formed on the pixel definition layer ISL. The conductive partition wall CPW may include a first conductive layer CDL1 and a second conductive layer CDL2.

[0180] refer to Fig.8D, the light emitting pattern EP1, the upper electrode UE1 and the first capping pattern CP1 may be formed on the lower electrode LE1, the auxiliary electrode AXE-R and the conductive partition wall CPW. The first capping pattern CP1 may be omitted. The light emitting pattern EP1, the upper electrode UE1 and the first capping pattern CP1 formed on the auxiliary electrode AXE-R may also be referred to as the first-first dummy pattern DMP1-1. The light emitting pattern EP1, the upper electrode UE1 and the first capping pattern CP1 formed on the conductive partition wall CPW may also be referred to as the first dummy pattern DMP1.

[0181] The upper electrode UE1 may be continuously formed from the top of the first lower electrode LE1 to the top of the auxiliary electrode AXE-R. The upper electrode UE1 may also be formed on a portion of the auxiliary electrode AXE-R formed on the side surface of the power electrode PL and may be electrically connected to the power electrode PL via the auxiliary electrode AXE-R.

[0182] refer to Fig. 9 , the formation of the encapsulation layer TFE may include forming a first lower encapsulation inorganic film LIL1, forming an encapsulation organic film OL, and forming an upper encapsulation inorganic film UIL.

[0183] The first lower encapsulation inorganic film LIL1 may be formed to cover the conductive partition wall CPW, the capping pattern CP1, and the first dummy pattern DMP1 and the first-first dummy pattern DMP1-1. For the purpose of planarization, the encapsulation organic film OL may be formed by covering the steps caused by the circuit element layer DP-CL and the light emitting element layer DP-OLED. The upper encapsulation inorganic film UIL may be formed on the encapsulation organic film OL.

[0184] According to the above, since the contact stability of the upper electrode is improved, the reliability of the display panel according to the present disclosure can be improved.

[0185] In addition, the method for manufacturing a display panel according to the present disclosure can simplify the process.

[0186] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display panel, comprising: basal layer; A circuit element layer, disposed on the base layer, wherein the circuit element layer includes a power supply electrode; as well as A light emitting element layer is disposed on the circuit element layer, and the light emitting element layer includes: an auxiliary electrode, disposed on a side surface of the power electrode; A pixel defining film, defining a pixel opening; a conductive partition wall disposed on the pixel definition film, the conductive partition wall comprising a first conductive layer disposed on the pixel definition film and a second conductive layer disposed on the first conductive layer, a side surface of the second conductive layer protruding more than a side surface of the first conductive layer; A lower electrode, disposed in the pixel opening; a light emitting pattern, disposed on the lower electrode; and an upper electrode, arranged on the light-emitting pattern, Wherein, the upper electrode is electrically connected to the power electrode via the auxiliary electrode.

2. The display panel according to claim 1, wherein: The circuit element layer further includes a first circuit layer disposed on the base layer and a second circuit layer defining an opening and disposed on the first circuit layer, and Wherein, the power electrode is arranged in the opening of the second circuit layer.

3. The display panel according to claim 2, wherein: The opening of the second circuit layer is spaced apart from the lower electrode in a plan view.

4. The display panel according to claim 2, wherein: The auxiliary electrode is provided directly on the side surface of the power electrode in a plan view.

5. The display panel according to claim 2, wherein: The pixel definition film is disposed on the second circuit layer.

6. The display panel according to claim 1, wherein: The auxiliary electrode includes or consists of the same material as that of the lower electrode.

7. The display panel according to claim 1, wherein: The auxiliary electrode is spaced apart from the lower electrode in a plan view and is electrically insulated from the lower electrode.

8. The display panel according to claim 1, wherein: The circuit element layer further includes transistors, and Wherein, the lower electrode is electrically connected to the transistor.

9. The display panel according to any one of claims 1 to 8, wherein: The conductive partition wall further includes a third conductive layer disposed between the first conductive layer and the pixel definition film, and Wherein, a side surface of the third conductive layer protrudes more than a side surface of the first conductive layer.

10. The display panel according to claim 1, wherein: The power electrode includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and The side surface of the first layer and the side surface of the third layer are more protruding than the side surface of the second layer.

11. The display panel according to claim 1, wherein: The lower electrode and the auxiliary electrode include ITO.

12. The display panel according to claim 1, wherein: The power electrode includes Al.

13. A method for manufacturing a display panel, the method comprising: preparing a base layer; forming a circuit element layer on the base layer, the forming of the circuit element layer comprising: forming a power electrode on the first circuit layer; and forming a second circuit layer on the first circuit layer defining an opening exposing the power electrode; and A light emitting element layer is formed on the circuit element layer, wherein the forming of the light emitting element layer comprises: forming a lower electrode and an auxiliary electrode; forming a pixel definition film covering a portion of the lower electrode; forming a conductive partition wall on the pixel definition film, wherein the forming of the conductive partition wall comprises: forming a first conductive layer; and forming a second conductive layer on the first conductive layer; forming a light emitting pattern on the lower electrode; and forming an upper electrode on the light emitting pattern, The side surface of the second conductive layer is formed to protrude more than the side surface of the first conductive layer.

14. The method according to claim 13, wherein: The lower electrode and the auxiliary electrode include the same material and are formed in the same process operation.

15. The method according to claim 13, wherein: The lower electrode and the auxiliary electrode are spaced apart from each other in a plan view.

16. The method according to claim 13, wherein: The auxiliary electrode is formed at least on a side surface of the power electrode.

17. The method according to claim 13, wherein: The upper electrode is formed to overlap the lower electrode and the auxiliary electrode in a plan view.

18. The method according to claim 13, wherein: The upper electrode is formed to contact a portion of the auxiliary electrode disposed on a side surface of the power electrode.

19. The method according to claim 13, wherein: An etching rate of the first conductive layer is greater than an etching rate of the second conductive layer.

20. The method according to any one of claims 13 to 19, wherein: The forming of the conductive partition wall further includes forming a third conductive layer on the pixel definition film, and The side surface of the third conductive layer is formed to protrude more than the side surface of the first conductive layer.

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