Layout of deep groove process, design method of layout and image sensor

By designing a layout of deep grooves, using the cross-circling deep groove patterns and connection structures, the problem of inconsistent size of deep groove patterns in the prior art is solved, the etching load effect is reduced, and the performance of image sensors is improved and yield.

CN119395939APending Publication Date: 2025-02-07GALAXYCORE SHANGHAI
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Patent Information

Application Number
CN202411409276.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-10-09
Publication Date
2025-02-07

AI Technical Summary

Technical Problem

In the prior art, when designing deep groove patterns, it is difficult to achieve dimensional consistency, resulting in etching load effects and affecting the performance and yield of image sensors.

Method used

Using a deep groove layout design method, by providing a mask pattern that includes a deep groove pattern crossing around the pixel area arranged in an array, disconnecting the intersection to form a connection structure connecting adjacent pixels, ensuring arbitrary The four corners of a pixel correspond to four connection structures, and the connection structure rotates and symmetrically along the center of the pixel.

Benefits of technology

The dimensional consistency of the deep groove pattern is achieved, the etching load effect is reduced, and the deep groove structure with good etching depth consistency is obtained, which reduces the difficulty of subsequent processes and improves the performance and yield of the image sensor.

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Abstract

The invention discloses a deep groove layout design method of an image sensor, which comprises the following steps of: providing a mask plate which comprises a plurality of deep groove patterns which are mutually crossed and encircled to form pixel areas which are arranged in an array; the intersections between the deep groove patterns are disconnected to form connecting structures for connecting the adjacent pixels; wherein the four corners of any pixel correspond to the four connecting structures, the two diagonal connecting structures in the four connecting structures are parallel to each other, and the two adjacent connecting structures in the four connecting structures are perpendicular to each other. According to the layout design, deep groove patterns with consistent sizes can be obtained, interconnection between any adjacent pixels can be realized, the etching loading effect can be reduced, a deep groove structure with relatively good etching depth consistency can be obtained, the subsequent process difficulty is reduced, and the performance and the yield of the image sensor are improved.
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Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep trench layout and a design method thereof, and an image sensor. Background Art

[0002] With the development of semiconductor process nodes and the market's demand for image sensor performance, the pixel size of image sensors is shrinking. However, the requirement for pixel signal-to-noise ratio is not decreasing, but gradually increasing.

[0003] To resolve the contradiction between the two, the proportion of photodiodes in pixel volume has gradually increased to improve signal strength, but this has introduced a new problem, which is the requirement to form good pinning at each silicon interface to reduce pixel dark current. Limited by the resolution of photoresist, photodiodes formed using ion implantation cannot meet the above requirements.

[0004] The above problems can be solved by using epitaxial method to prepare photodiodes. A new process for the photosensitive unit of an image sensor is to form a PN junction or a PIN junction by deep trench etching and selective epitaxy, such as patents CN204632760U and CN113224093A. This scheme first performs deep trench etching on the semiconductor substrate, and then selectively epitaxies P-type, intrinsic or N-type semiconductor materials. This scheme can finely control the doping concentration and the size of the PN junction. In the existing layout design, each pixel unit is interconnected by a connecting structure, and then the substrate below the connecting structure is etched through to form a cantilever beam. In the existing mask design, the different sizes of the light-transmitting area or the non-light-transmitting area result in different etching depths, resulting in a large etching load effect (Loading effect), which brings greater process difficulty and affects the performance and yield of the pixel.

[0005] The above and other prior art in the semiconductor processing art shows that it would be beneficial to design a deep trench pattern mask technology with consistent dimensions to obtain deep trenches of uniform depth. Summary of the invention

[0006] Based on the above-described problems, the present invention proposes a deep trench layout and a design method thereof, as well as an image sensor.

[0007] On the one hand, the present invention proposes a deep groove layout design method, comprising: providing a mask, the mask comprising: a plurality of deep groove patterns, the plurality of deep groove patterns intersecting each other to form an array-arranged pixel area; the intersections between the deep groove patterns are disconnected to form a connection structure connecting adjacent pixels; wherein the four corners of any one of the pixels correspond to four connection structures, two diagonal connection structures of the four connection structures are parallel to each other, and two adjacent connection structures of the four connection structures are perpendicular to each other.

[0008] Optionally, the four connection structures are rotationally symmetric along the center of the pixel.

[0009] Optionally, the deep groove patterns include horizontal deep groove patterns extending in a horizontal direction and vertical deep groove patterns extending in a vertical direction, wherein each of the deep groove patterns spans across two pixels on one side of its extending direction.

[0010] Optionally, the widths of both ends of the deep groove pattern in the extending direction are increased.

[0011] Optionally, a length of the horizontal deep trench pattern along the horizontal direction is equal to a length of the vertical deep trench pattern along the vertical direction.

[0012] Optionally, the deep groove pattern at the periphery of the pixel is rotationally symmetric along the center of the pixel.

[0013] Optionally, the horizontal deep grooves separate the pixels of different numbers of rows, and the vertical deep grooves separate the pixels of different numbers of columns.

[0014] Optionally, the deep groove pattern is a light-transmitting area, and the pixel pattern and the connection structure are light-impermeable areas, or the deep groove pattern is a light-impermeable area, and the pixel pattern and the connection structure are light-transmitting areas.

[0015] In a second aspect, the present invention provides a layout for an image sensor, which is designed using the aforementioned design method.

[0016] In a third aspect, the present invention proposes an image sensor manufactured using the aforementioned layout during the formation process.

[0017] Optionally, the connection structure is a cantilever beam structure.

[0018] Optionally, the image sensor further includes a floating diffusion region (FD), a source follower transistor (SF), a reset transistor (RST) and a ground (GND) disposed at the connection structure.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The layout design of the present invention can obtain a deep groove pattern with consistent size, and any adjacent pixels can be interconnected, which can reduce the etching loading effect, obtain a deep groove structure with good etching depth consistency, reduce the difficulty of subsequent processes, and improve the performance and yield of image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings of the present invention constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and together with the description are used to explain the principle of the present invention.

[0021] Figure 1 A schematic diagram of a deep trench layout design for an image sensor in the prior art.

[0022] Figure 2 It is a schematic diagram of the deep trench layout design of the image sensor of the present invention.

[0023] Figure 3A , 3B It is a cross-sectional view of the connection structure of the present invention.

[0024] Figure 4 FIG. 4 is a diagram showing the position distribution of transistors in the image sensor of the present invention. DETAILED DESCRIPTION

[0025] In the existing deep trench layout design of image sensors, see the attached Figure 1 , a plurality of first grooves 101, second grooves 102, third grooves 103 and fourth grooves 104 are provided, which are used to form a semiconductor island structure after etching the substrate to form a pixel area 105. And a connecting structure 106 is also included between adjacent pixel areas 105 to achieve connection between pixels. The above layout is applied to the photolithography process, and the mask pattern is transferred to the substrate, wherein the bottom of the connecting structure is etched into a cantilever structure. It can be seen from the accompanying drawings that the length dimensions of the first groove 101, the second groove 102, the third groove 103 and the fourth groove 104 are inconsistent. Due to the inconsistent length of the groove pattern, it is easy to cause an etching load effect, resulting in inconsistent etching groove depth, which in turn brings process difficulties and affects the performance and yield of the image sensor.

[0026] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] Figure 2 A schematic diagram of the layout structure of the deep trench provided in this embodiment.

[0028] During the manufacturing process of the image sensor, before selective epitaxy, the semiconductor substrate is etched to form an array of semiconductor island structures to form a number of pixels and grooves surrounding the semiconductor island structures, and the upper parts of the semiconductor island structures are interconnected by at least one connecting structure.

[0029] According to a method for designing a mask layout provided by the present invention, a plurality of deep groove patterns 201 and 202 are arranged, and the plurality of deep groove patterns cross each other to form an array of pixels 203. The intersections between the deep groove patterns 201 and 202 are disconnected to form a connection structure 204 connecting adjacent pixels 203. The mask is a photoresist. According to different types of photoresists, the deep groove pattern is set as a light-transmitting area, and the pixel pattern and the connection structure are non-light-transmitting areas, or the deep groove pattern is set as a non-light-transmitting area, and the pixel pattern and the connection structure are light-transmitting areas. When the mask layout of the deep groove is applied to the photolithography process, the mask layout is transferred to the substrate.

[0030] refer to Figure 2 , the connection structure extends outward from the corner of the pixel 203 to the adjacent pixel, and the four corners of any one of the pixels correspond to four connection structures 204, and two diagonal connection structures of the four connection structures are parallel to each other, and two adjacent connection structures of the four connection structures are perpendicular to each other. The sizes of the four connection structures may be the same or different. In a specific embodiment, the four connection structures have the same size and are rotationally symmetrical about the center of the pixel. With the above connection structure, any adjacent pixels in the image sensor can be interconnected.

[0031] Further, the deep groove pattern includes a horizontal deep groove pattern 201 extending in the horizontal direction and a vertical deep groove pattern 202 extending in the vertical direction, wherein the horizontal deep grooves separate the pixels of different rows, and the vertical deep grooves separate the pixels of different columns, wherein each of the deep groove patterns crosses two pixels 203 on any side of its extension direction. In a specific embodiment, see the attached Figure 2 , the length of the horizontal deep groove pattern along the horizontal direction is equal to the length of the vertical deep groove pattern along the vertical direction. Preferably, the four deep groove structures around a pixel 203 are of the same size, and the deep groove pattern around a pixel 203 is rotationally symmetrically arranged along the center of the pixel. In a specific embodiment, in the entire layout, the horizontal deep groove pattern and the vertical deep groove pattern of one or several pixel array units are exactly the same size, and the deep groove size in the remaining pixel array units may be different from the deep groove pattern size in the aforementioned one or several pixel array units, and the number of pixel areas 203 in one pixel array unit can be selected as needed.

[0032] The shape of the deep groove pattern can be selected according to needs, preferably, as Figure 2 As shown, the deep groove pattern is in a polygonal shape, and the widths of the two end positions of the deep groove pattern in the extending direction are larger than those of the center position.

[0033] In this embodiment, the semiconductor substrate may be a silicon substrate, and the silicon substrate is etched using the deep trench mask as a mask to form array-arranged silicon pillars 303 (semiconductor island structure) in the silicon substrate. Figure 3A , and then the bottom of the connection structure is hollowed out by controlling the etching process, so that the bottom of the connection structure can be suspended, that is, only the upper parts of the silicon pillars are connected to each other, and a cantilever-shaped connection structure 301 spanning the groove 302 is formed between the silicon pillars. The connection structure can not only realize the interconnection between adjacent pixels but also reduce the defects caused by the subsequent epitaxial process.

[0034] Then, see Appendix Figure 3B According to actual needs, an epitaxial layer 304 , a first dielectric layer 305 and a second dielectric layer 306 are sequentially prepared in the trench 302 .

[0035] In addition, see Appendix Figure 4 Taking a 2×2 pixel array unit 401 as an example, the image sensor manufactured using the deep trench layout in this embodiment further includes a floating diffusion region 402 (FD), a source follower transistor 405 (SF), a reset transistor 404 (RST) and a ground 403 (GND) arranged on the upper part of the connection structure, wherein the floating diffusion region 402 (FD) is located on the upper part of the connection structure in the middle area of ​​the pixel array unit, and the source follower transistor 405 (SF), the reset transistor 404 (RST) and the ground 403 (GND) are located on the upper part of the connection structure in the edge area of ​​the pixel array unit.

[0036] In summary, the layout design of the present invention can obtain a deep groove pattern with consistent size, and any adjacent pixels can be interconnected, which can reduce the etching loading effect, obtain a deep groove structure with good etching depth consistency, reduce the difficulty of subsequent processes, and improve the performance and yield of image sensors.

[0037] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0038] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A deep trench layout design method, characterized in that: A mask is provided, the mask comprising: A plurality of deep groove patterns, wherein the plurality of deep groove patterns cross each other and surround a pixel area arranged in an array; The intersections between the deep groove patterns are disconnected to form a connection structure connecting adjacent pixels; Among them, the four corners of any one of the pixels correspond to four connection structures, two diagonal connection structures among the four connection structures are parallel to each other, and two adjacent connection structures among the four connection structures are perpendicular to each other.

2. The layout design method according to claim 1, characterized in that: The four connection structures are rotationally symmetric along the center of the pixel.

3. The layout design method according to claim 1, characterized in that: The deep groove patterns include a horizontal deep groove pattern extending in a horizontal direction and a vertical deep groove pattern extending in a vertical direction, wherein each of the deep groove patterns spans across two pixels on one side of its extending direction.

4. The layout design method according to claim 3, characterized in that: The widths of both ends of the deep groove pattern in the extending direction are increased.

5. The layout design method according to claim 4, characterized in that: The length of the horizontal deep trench pattern along the horizontal direction is equal to the length of the vertical deep trench pattern along the vertical direction.

6. The layout design method according to claim 5, characterized in that: The deep groove pattern at the periphery of the pixel is rotationally symmetric about the center of the pixel.

7. The layout design method according to claim 3, characterized in that: The horizontal deep trenches separate the pixels of different numbers of rows, and the vertical deep trenches separate the pixels of different numbers of columns.

8. The layout design method according to claim 1, characterized in that: The deep groove pattern is a light-transmitting area, and the pixel pattern and the connection structure are light-impermeable areas, or the deep groove pattern is a light-impermeable area, and the pixel pattern and the connection structure are light-transmitting areas.

9. A layout for an image sensor, characterized in that: The invention is designed by adopting the design method according to any one of claims 1 to 8.

10. An image sensor, characterized in that: The layout as claimed in claim 9 is used in the forming process.

11. The image sensor according to claim 10, characterized in that: The connection structure is a cantilever beam structure.

12. The image sensor according to claim 11, characterized in that: The image sensor further includes a floating diffusion region (FD), a source follower transistor (SF), a reset transistor (RST), and a ground (GND) disposed at the connection structure.

Citation Information

Patent Citations

  • Silicon epitaxy filling method for hole

    CN113224093A