On-chip power supply current-limiting protection circuit with adjustable load current

Abstract

The invention discloses an on-chip power supply current-limiting protection circuit with an adjustable load current, and relates to the field of integrated circuit design, the on-chip power supply current-limiting protection circuit comprises a regulator tube MP, an error amplifier EA, a current-limiting circuit, a first feedback resistor RF1 and a second feedback resistor RF2, an output voltage VOUT is divided by the first feedback resistor RF1 and the second feedback resistor RF2 to generate a feedback voltage VFB; the feedback voltage VFB is connected with the positive end of the error amplifier EA, and the reference voltage VREF is connected with the negative end of the error amplifier; the output Vea of the error amplifier is connected with the current-limiting protection circuit and the gate end of the adjusting tube MP; the source end of the adjusting tube MP is connected with the VDD; and the second feedback resistor RF2 is connected with the GND at the same time. Compared with a traditional current-limiting protection circuit, the maximum load current can be adjusted, the reliability is high, and the problem that when the load current is too large or the output is short-circuited to the ground, a chip is burnt down at a high temperature is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an on-chip power supply current limiting protection circuit with calibrable load current. Background Art

[0002] In the power supply inside the chip, the low-dropout linear regulator (LDO) has become the most common structure due to its advantages such as fewer peripheral components, low cost, small output ripple, and fast load response. Due to the limited chip area, the size of the core component of the LDO, the adjustment tube, will be determined according to the load requirements of the application scenario, so its maximum output current will be limited. When the load current is too large or the output is short-circuited to the ground due to misoperation, the adjustment tube will burn out at high temperature, causing irreversible damage to the chip.

[0003] The common LDO current limiting protection circuit samples the LDO output voltage or output current, and then passes it through the amplifier circuit to feedback control the gate end of the adjustment tube. This method requires feedback loop control composed of an amplifier, has a slow response speed, and needs to consider its own stability, which will cause stability problems for the LDO.

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0005] In view of the above technical problems in the related art, the present invention proposes an on-chip power supply current limiting protection circuit with load current calibration, which includes an adjustment tube MP, an error amplifier EA, a current limiting circuit, a first feedback resistor RF1 and a second feedback resistor RF2, and is characterized in that: the output voltage VOUT is divided by the first feedback resistor RF1 and the second feedback resistor RF2 to generate a feedback voltage VFB; the feedback voltage VFB is connected to the positive end of the error amplifier EA, and the reference voltage VREF is connected to the negative end of the error amplifier; the output Vea of ​​the error amplifier is connected to the current limiting protection circuit and the gate end of the adjustment tube MP; the source end of the adjustment tube MP is connected to VDD; the second feedback resistor RF2 is also connected to GND; the adjustment tube MP is a PMOS transistor; the current limiting circuit includes: a reference current Ibias, a first transistor MP1, and a fourth transistor MN1; a first current mirror, the first current mirror is connected to the reference current Ibias; a second current mirror, the second current mirror is connected to the first transistor MP1 and the first current mirror; the first transistor MP1 is connected to the output voltage VOUT, and the first transistor MP1 is connected to the adjustment tube MP.

[0006] Specifically, the current limiting circuit also includes: a first switch tube MS1, a second switch tube MS2, a sixth transistor MN3 and a seventh transistor MN4; the drain ends of the sixth transistor MN3 and the seventh transistor MN4 are connected in series, the second switch tube MS2 and the first switch tube MS1 are connected to the gate end, and the gate end is connected to the gate-drain of the fifth transistor MN2, and the gate ends of the first switch tube MS1 and the second switch tube MS2 are respectively connected to the first control voltage V1 and the second control voltage V2.

[0007] Specifically, the output voltage VOUT is the output end of a low voltage dropout linear regulator LDO; and the reference voltage VREF is a reference voltage.

[0008] Specifically, when the low voltage dropout linear regulator LDO works normally, the current limiting circuit is bypassed; when the load current of the low voltage dropout linear regulator LDO is overloaded, the current limiting circuit limits the current of the adjustment tube MP by limiting the Vea voltage.

[0009] Specifically, the current limiting circuit further includes: a second transistor MP2, a second transistor MP3, an eighth transistor MN5, a ninth transistor MN6, a first resistor R1 and a second resistor R2; the first current mirror is composed of a fifth transistor MN2, an eighth transistor MN5 and a ninth transistor MN6; the second current mirror is composed of a second transistor MP2 and a second transistor MP3; the output voltage VOUT is connected to the drain end of the first transistor MP1; the output Vea of ​​the error amplifier EA is connected to the gate end of the first transistor MP1 and the drain end of the fourth transistor MN1; the source end of the fourth transistor MN1 is connected to VDD; the gate end of the fifth transistor MN2 is connected to VDD; The drain is short-circuited, the source is connected to GND, and the gate and drain are connected to the reference current Ibias; the gate of the fifth transistor MN2 is connected to the gate of the eighth transistor MN5 and the gate of the ninth transistor MN6; the gate and drain of the second transistor MP2 are short-circuited, and the source is connected in series with the first resistor R1 and connected to VDD; the gate of the third transistor MP3 is connected to the gate of the second transistor MP2, the drain is connected to the gate of the fourth transistor MN1, the source is connected in series with the second resistor R2 and connected to VDD, and the source is connected to the source of the first transistor MP1; the drain of the eighth transistor MN5 is connected to the drain of the second transistor MP2; the drain of the ninth transistor MN6 is connected to the drain of the third transistor MP3.

[0010] Specifically, the eighth transistor MN5 and the ninth transistor MN6 have the same size, and the size ratio of the fifth transistor MN2 and the eighth transistor MN5 is 1:N, where N>1.

[0011] Specifically, the size ratio of the fifth transistor MN2 , the sixth transistor MN3 , and the seventh transistor MN4 is 3:2:1.

[0012] Specifically, the second transistor MP2 and the third transistor MP3 have the same size; the resistance ratio of the first resistor R1 to the second resistor R2 is M:1, where M>1.

[0013] Specifically, when the gate-source voltage of the second transistor MP2 is less than the gate-source voltage of the third transistor MP3, the fourth transistor MN1 is in a turned-off state, and the current limiting circuit does not work.

[0014] Specifically, when the gate-source voltage of the second transistor MP2 is greater than the gate-source voltage of the third transistor MP3, the fourth transistor MN1 is turned on, and the current limiting circuit starts to work.

[0015] Specifically, the first transistor MP1, the second transistor MP2, the third transistor MP3 and the fourth transistor MN1 are PMOS transistors; the fifth transistor MN2, the sixth transistor MN3, the seventh transistor MN4, the eighth transistor MN5, the ninth transistor MN6, the first switch tube MS1 and the second switch tube MS2 are NMOS transistors.

[0016] Compared with the traditional current limiting protection circuit, the current limiting protection circuit of the present invention has an adjustable maximum load current and high reliability, and effectively solves the problem of high temperature burning of the chip when the load current is too large or the output is short-circuited to the ground.

[0017] Furthermore, the current limiting protection circuit of the present invention has a simple structure, quick response, is not affected by power supply voltage, process, and temperature, can adapt to the current limiting protection requirements of various on-chip power supplies more quickly, and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of the structure of an on-chip power supply current limiting protection circuit with calibrable load current provided according to an embodiment of the present invention;

[0020] Figure 2 Schematic diagram of the structure of a current limiting circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0022] Embodiment 1

[0023] refer to Figure 1-2 The present embodiment provides an on-chip power supply current limiting protection circuit with load current calibration, which includes an adjustment tube MP, an error amplifier EA, a current limiting circuit, a first feedback resistor RF1 and a second feedback resistor RF2, and is characterized in that: the output voltage VOUT is divided by the first feedback resistor RF1 and the second feedback resistor RF2 to generate a feedback voltage VFB; the feedback voltage VFB is connected to the positive end of the error amplifier EA, and the reference voltage VREF is connected to the negative end of the error amplifier; the output Vea of ​​the error amplifier is connected to the current limiting protection circuit and the gate end of the adjustment tube MP; the source end of the adjustment tube MP is connected to VDD; the second feedback resistor RF2 is also connected to GND; the adjustment tube MP is a PMOS transistor; the current limiting circuit includes: a reference current Ibias, a first transistor MP1, and a fourth transistor MN1; a first current mirror, the first current mirror is connected to the reference current Ibias; a second current mirror, the second current mirror is connected to the first transistor MP1 and the first current mirror; the first transistor MP1 is connected to the output voltage VOUT, and the fourth transistor MN1 is connected to the adjustment tube MP.

[0024] The current limiting circuit also includes: a first switch tube MS1, a second switch tube MS2, a sixth transistor MN3 and a seventh transistor MN4; the drain ends of the sixth transistor MN3 and the seventh transistor MN4 are connected in series, the second switch tube MS2 and the first switch tube MS1 are connected to the gate end, and the gate end is connected to the gate-drain of the fifth transistor MN2, and the gate ends of the first switch tube MS1 and the second switch tube MS2 are respectively connected to the first control voltage V1 and the second control voltage V2.

[0025] The drain terminals of the sixth transistor MN3 and the seventh transistor MN4 are connected in series with the second switch tube MS2 and the first switch tube MS1 and the gate terminal, and the gate terminal is connected to the gate-drain of the fifth transistor MN2, for adjusting the maximum load current of the LDO.

[0026] The output voltage VOUT in this example is the output end of the low voltage dropout linear regulator LDO; the reference voltage VREF is a reference voltage.

[0027] In this embodiment, a reference voltage module is used to generate a reference voltage as the reference voltage VREF.

[0028] The adjustment tube MP is the core component of LDO, and the current limiting circuit controls and limits the current through the Vea point.

[0029] When the low dropout linear regulator LDO works normally (the load current is within the design range), the current limiting circuit is bypassed;

[0030] When the load current of the low dropout linear regulator LDO is overloaded, the current limiting circuit limits the current of the adjustment tube MP by limiting the Vea voltage.

[0031] This embodiment uses simple negative feedback to implement the LDO current limiting circuit, has a simple structure, does not require an additional comparison circuit, and has a rapid response.

[0032] Further, refer to Figure 2 , the current limiting circuit further includes: a second transistor MP2, a second transistor MP3, an eighth transistor MN5, a ninth transistor MN6, a first resistor R1 and a second resistor R2; the first current mirror is composed of the fifth transistor MN2, the eighth transistor MN5 and the ninth transistor MN6; the second current mirror is composed of the second transistor MP2 and the second transistor MP3;

[0033] The output voltage VOUT is connected to the source terminal of the first transistor MP1; the output Vea of ​​the error amplifier EA is connected to the gate terminal of the first transistor MP1 and the drain terminal of the fourth transistor MN1; the source terminal of the fourth transistor MN1 is connected to VDD; the gate and drain of the fifth transistor MN2 are short-circuited, the source terminal is connected to GND, and the gate and drain terminals are connected to the reference current Ibias; wherein Ibias is the reference current provided by the LDO circuit, and the current flows into the fifth transistor MN2, and MN2 is a diode connection mode;

[0034] The gate terminal of the fifth transistor MN2 is connected to the gate terminals of the eighth transistor MN5 and the ninth transistor MN6; the second transistor MP2 is connected in a diode connection manner, with the gate and drain short-circuited, and the source terminal is connected in series with the first resistor R1 and connected to VDD; the gate terminal of the third transistor MP3 is connected to the gate terminal of the second transistor MP2, the drain terminal is connected to the gate terminal of the fourth transistor MN1, the source terminal is connected in series with the second resistor R2 and connected to VDD, and the source terminal is connected to the drain terminal of the first transistor MP1; the drain terminal of the eighth transistor MN5 is connected to the drain terminal of the second transistor MP2; the drain terminal of the ninth transistor MN6 is connected to the drain terminal of the third transistor MP3.

[0035] In the current limiting circuit of this embodiment, the eighth transistor MN5 and the ninth transistor MN6 have the same size; the size ratio of the fifth transistor MN2 and the eighth transistor MN5 is 1:N, N>1; the fifth transistor MN2, the eighth transistor MN5 and the ninth transistor MN6 form a first current mirror, and the current ratio is 1:N.

[0036] A current mirror is a basic circuit module in an integrated circuit. Its main function is to copy or mirror a reference current to one or more output branches. The current mirror can accurately control the current in the circuit so that the output current is proportional to the reference current or equal to the reference current. This is a prior art and will not be described here.

[0037] In the current limiting circuit of this embodiment, the size ratio of the fifth transistor MN2 , the sixth transistor MN3 and the seventh transistor MN4 is 3:2:1.

[0038] In the current limiting circuit of this embodiment, the second transistor MP2 and the second transistor MP3 have the same size and form a second current mirror with a current ratio of 1:1. The resistance ratio of the first resistor R1 and the second resistor R2 is M:1, where M>1.

[0039] The current flowing into the eighth transistor MN5 is the same as that flowing into the ninth transistor MN6, and the gate terminal voltages of the second transistor MP2 and the third transistor MP3 are equal. Since the resistance value of the first resistor R1 is greater than the resistance value of the second resistor R2, the gate-source voltage of the second transistor MP2 is less than the gate-source voltage of the third transistor MP3, and the current of the second transistor MP2 is the same as that of the third transistor MP3. The third transistor MP3 enters the linear region, and the fourth transistor MN1 is in a closed state, and the current limiting circuit does not work.

[0040] As the load current of the adjustment tube MP gradually increases, that is, the Vea voltage becomes lower, the first transistor MP1 is turned on, the current on the second resistor R2 gradually increases, and the source terminal voltage of the third transistor MP3 gradually decreases. When the gate-source voltage of the second transistor MP2 is greater than the gate-source voltage of the third transistor MP3, the drain terminal voltage of the third transistor MP3 is pulled down, the ninth transistor MN6 enters the linear region, the fourth transistor MN1 is turned on, and the current limiting circuit starts to work.

[0041] The principle of adjustable maximum load current:

[0042] The opening and closing of the first switch tube MS1 and the second switch tube MS2 can adjust the ratio of the fifth transistor MN2 to the eighth transistor MN5 and the ninth transistor MN6, that is, adjust the current of the eighth transistor MN5 and the ninth transistor MN6. When the current of the eighth transistor MN5 and the ninth transistor MN6 increases, the voltage difference between the gate-source voltage of the second transistor MP2 and the third transistor MP3 increases. To turn on the current limiting circuit (when the gate-source voltage of the second transistor MP2 is greater than the gate-source voltage of the third transistor MP3, the ninth transistor MN6 enters the linear region and the fourth transistor MN1 turns on), a smaller Vea is required, that is, the maximum load current of the LDO increases. Similarly, when the current of the eighth transistor MN5 and the ninth transistor MN6 is adjusted to be smaller, a larger Vea is required to turn on the current limiting circuit, and the maximum load current of the LDO decreases.

[0043] In this embodiment, the first transistor MP1, the second transistor MP2, the third transistor MP3 and the fourth transistor MN1 are PMOS transistors; the fifth transistor MN2, the sixth transistor MN3, the seventh transistor MN4, the eighth transistor MN5, the ninth transistor MN6, the first switch tube MS1 and the second switch tube MS2 are NMOS transistors.

[0044] Compared with the traditional current limiting protection circuit, the current limiting protection circuit of this embodiment has an adjustable maximum load current and high reliability, and effectively solves the problem of high temperature burning of the chip when the load current is too large or the output is short-circuited to the ground.

[0045] Furthermore, the current limiting protection circuit of this embodiment has a simple structure, a quick response, is not affected by power supply voltage, process, and temperature, can adapt to the current limiting protection requirements of various on-chip power supplies more quickly, and has a wider range of applications.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A load current calibrated on-chip power supply current limiting protection circuit, comprising a regulating tube MP, an error amplifier EA, a current limiting circuit, a first feedback resistor RF1 and a second feedback resistor RF2, characterized in that: The output voltage VOUT is divided by the first feedback resistor RF1 and the second feedback resistor RF2 to generate a feedback voltage VFB; the feedback voltage VFB is connected to the positive terminal of the error amplifier EA, and the reference voltage VREF is connected to the negative terminal of the error amplifier; the output Vea of ​​the error amplifier is connected to the current limiting protection circuit and the gate terminal of the adjustment tube MP; the source terminal of the adjustment tube MP is connected to VDD; The second feedback resistor RF2 is connected to GND at the same time; the adjustment tube MP is a PMOS transistor; the current limiting circuit includes: a reference current Ibias, a first transistor MP1, and a fourth transistor MN1; a first current mirror, the first current mirror is connected to the reference current Ibias; a second current mirror, the second current mirror is connected to the first transistor MP1 and the first current mirror; the first transistor MP1 is connected to the output voltage VOUT, and the fourth transistor MN1 is connected to the adjustment tube MP.

2. The on-chip power supply current limiting protection circuit according to claim 1, characterized in that: The current limiting circuit also includes: a first switch tube MS1, a second switch tube MS2, a fifth transistor MN2, a sixth transistor MN3 and a seventh transistor MN4; the drain ends of the sixth transistor MN3 and the seventh transistor MN4 are connected in series, the second switch tube MS2 and the first switch tube MS1 are connected to the gate end, and the gate end is connected to the gate-drain of the fifth transistor MN2, and the gate ends of the first switch tube MS1 and the second switch tube MS2 are respectively connected to the first control voltage V1 and the second control voltage V2.

3. The on-chip power supply current limiting protection circuit according to claim 1, characterized in that: The output voltage VOUT is the output end of the low voltage dropout linear regulator LDO; the reference voltage VREF is a reference voltage.

4. The on-chip power supply current limiting protection circuit according to claim 1, characterized in that: When the low voltage dropout linear regulator LDO operates normally, the current limiting circuit is bypassed; when the load current of the low voltage dropout linear regulator LDO is overloaded, the current limiting circuit limits the current of the adjustment tube MP by limiting the Vea voltage.

5. The on-chip power supply current limiting protection circuit according to claim 2, characterized in that: The current limiting circuit also includes: a second transistor MP2, a second transistor MP3, an eighth transistor MN5, a ninth transistor MN6, a first resistor R1 and a second resistor R2; the first current mirror is composed of a fifth transistor MN2, an eighth transistor MN5 and a ninth transistor MN6; the second current mirror is composed of a second transistor MP2 and a second transistor MP3; the output voltage VOUT is connected to the drain end of the first transistor MP1; the output Vea of ​​the error amplifier EA is connected to the gate end of the first transistor MP1 and the drain end of the fourth transistor MN1; the source end of the fourth transistor MN1 is connected to VDD; the gate-drain short circuit of the fifth transistor MN2 is connected to the drain end of the fifth transistor MN2; The gate terminal of the fifth transistor MN2 is connected to the gate terminals of the eighth transistor MN5 and the ninth transistor MN6; the gate and drain of the second transistor MP2 are short-circuited, and the source terminal is connected in series with the first resistor R1 and is connected to VDD; the gate terminal of the third transistor MP3 is connected to the gate terminal of the second transistor MP2, the drain terminal is connected to the gate terminal of the fourth transistor MN1, the source terminal is connected in series with the second resistor R2 and is connected to VDD, and the source terminal is connected to the source terminal of the first transistor MP1; the drain terminal of the eighth transistor MN5 is connected to the drain terminal of the second transistor MP2; the drain terminal of the ninth transistor MN6 is connected to the drain terminal of the third transistor MP3.

6. The on-chip power supply current limiting protection circuit according to claim 5, characterized in that: The eighth transistor MN5 and the ninth transistor MN6 have the same size, and the size ratio of the fifth transistor MN2 and the eighth transistor MN5 is 1:N, where N>1.

7. The on-chip power supply current limiting protection circuit according to claim 5, characterized in that: The size ratio of the fifth transistor MN2 , the sixth transistor MN3 and the seventh transistor MN4 is 3:2:

1.

8. The on-chip power supply current limiting protection circuit according to claim 5, characterized in that: The second transistor MP2 and the third transistor MP3 have the same size; the resistance ratio of the first resistor R1 to the second resistor R2 is M:1, M>1.

9. The on-chip power supply current limiting protection circuit according to claim 5, characterized in that: When the gate-source voltage of the second transistor MP2 is less than the gate-source voltage of the third transistor MP3, the fourth transistor MN1 is in a turned-off state, and the current limiting circuit does not work.

10. The on-chip power supply current limiting protection circuit according to claim 5, characterized in that: When the gate-source voltage of the second transistor MP2 is greater than the gate-source voltage of the third transistor MP3 , the fourth transistor MN1 is turned on, and the current limiting circuit starts to work.

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