Power management method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a power management method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring state information of a chip, wherein the state information comprises a power management state of the chip; if the power management state represents that the target management item of the chip is power-off management, generating a power control instruction based on the power-off management; electric connection between the Ethernet and the chip is cut off based on the power supply control instruction, and a power-on state between the Ethernet and the controller is kept; and if the power-off between the Ethernet and the chip is completed, controlling the power-off operation between the Ethernet and the controller. According to the embodiment of the invention, electric leakage of the input and output ports can be avoided, the problem of chip burnout caused by electric leakage is solved, and the chip can be ensured to quickly respond and be switched to a correct power supply state when needed through fine power supply management.

Description

Technical Field

[0001] The present application relates to the field of communication management technology, and in particular to a power management method, device, electronic device, and computer-readable storage medium. Background Art

[0002] In modern automotive systems, the stability and reliability of the system on chip (SOC) are crucial to the performance of the entire vehicle. In order to improve the remote fault diagnosis and analysis capabilities of the SOC and optimize its flashing process, the existing technology introduces the SOC diagnostic information reading function through the Ethernet DOIP diagnostic network (Diagnostic over IP, DOIP) and realizes the direct Ethernet flashing capability of the SOC. These functions significantly reduce the flashing time of the SOC chip by reducing the packet forwarding requirements for the microcontroller unit (MCU), thereby improving maintenance efficiency.

[0003] However, SOC chips generally lack GPIO leakage safety protection mechanisms. In scenarios where the SOC needs to be powered off separately for maintenance or replacement, such as under high temperature conditions, if the SOC does not have GPIO leakage protection, the Ethernet switch or the GPIO pins connected to the MCU may leak electricity to the SOC, causing damage to the internal circuits of the SOC chip. Damage to the SOC not only increases maintenance costs, but may also cause unplanned downtime of the vehicle system, affecting user experience and the normal operation of the vehicle. Summary of the invention

[0004] To solve the above technical problems, the embodiments of the present application provide a power management method and device, an electronic device, a computer-readable storage medium, and a computer program product.

[0005] According to one aspect of an embodiment of the present application, there is provided a power management method, which is applied to a chip management system, wherein the chip management system includes a chip, an Ethernet and a controller, wherein the controller is used to control the connection between the Ethernet and the chip, and forward the management message of the chip to a corresponding host computer through the Ethernet, wherein the method includes: obtaining status information of the chip, wherein the status information includes the power management status of the chip; if the power management status indicates that the target management item of the chip is power-off management, generating a power control instruction based on the power-off management; disconnecting the electrical connection between the Ethernet and the chip based on the power control instruction, and maintaining the power-on state between the Ethernet and the controller; if the power-off between the Ethernet and the chip is completed, controlling the power-off operation between the Ethernet and the controller.

[0006] According to one aspect of an embodiment of the present application, the controller includes a register, and generating a power control instruction based on the power-off management includes: generating a power control register value corresponding to the register based on the power control instruction; writing the power control register value into the controller to disconnect the port between the Ethernet and the chip.

[0007] According to one aspect of an embodiment of the present application, the method further includes: generating a power-off signal based on the power control register value; controlling the port between the Ethernet and the chip to be disconnected based on the power-off signal, and controlling the port not to send synchronization data to the host computer.

[0008] According to one aspect of an embodiment of the present application, controlling the port not to send synchronous data includes: determining a bit field of the clock signal corresponding to the port in the register; generating a clock signal control instruction for the clock signal based on the power control register value and the bit field; and clearing the data on the bit field based on the clock signal control instruction to turn off the clock signal so that the clock signal does not send synchronous data to the host computer.

[0009] According to one aspect of an embodiment of the present application, the method also includes: if the chip is in a power-off state and receives a power-on detection request, detecting whether the Ethernet is powered normally; if the Ethernet is powered normally, clearing the residual data between the Ethernet switch and the chip to restart the Ethernet; and establishing an electrical connection between the restarted Ethernet and the chip.

[0010] According to one aspect of an embodiment of the present application, the method also includes: during the electrical connection between the Ethernet and the chip, obtaining the power-on status of the chip, the power-on status including the power-on voltage and the power-on current; if the power-on voltage reaches a preset voltage threshold or the power-on current reaches a preset current threshold, generating a power-off control instruction between the Ethernet and the chip.

[0011] According to one aspect of an embodiment of the present application, the method also includes: obtaining temperature information of the chip, the temperature information including the surface temperature of the chip; if the surface temperature reaches a preset temperature threshold, disconnecting the electrical connection between the Ethernet and the chip, and controlling the chip to perform power-off management.

[0012] According to one aspect of an embodiment of the present application, there is provided a power management device, which is applied to a chip management system, wherein the chip management system includes a chip, an Ethernet and a controller, wherein the controller is used to control the connection between the Ethernet and the chip, and forward the management message of the chip to a corresponding host computer through the Ethernet, wherein the device includes: an acquisition module, which is used to acquire the management status of the chip, wherein the management status includes the power management status of the chip; a generation module, which is used to generate a power control instruction based on the power-off management if the power management status indicates that the target management item of the chip is power-off management; a disconnection module, which is used to disconnect the electrical connection between the Ethernet and the chip based on the power control instruction, and maintain the power-on state between the Ethernet and the controller; and a control module, which is used to control the power-off operation between the Ethernet and the controller if the power-off between the Ethernet and the chip is completed.

[0013] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the power management method as described above.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the power management method as described above.

[0015] According to one aspect of an embodiment of the present application, a computer program product is also provided, including a computer program, which implements the steps in the power management method described above when executed by a processor.

[0016] In the technical solution provided in the embodiment of the present application, when it is detected that the chip needs to be powered off, the port between the Ethernet and the chip is powered off first, thereby avoiding input and output leakage, thereby solving the problem of chip burning due to leakage, and through sophisticated power management, it can ensure that the system responds quickly and switches to the correct power state when needed. This helps to reduce system crashes or data loss caused by power problems, thereby improving the overall stability and reliability of the system, and through reasonable power-off management, unnecessary power fluctuations and overheating can be avoided, thereby extending the service life of the chip and the entire chip.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 is a schematic diagram of performing chip diagnosis via Ethernet according to an exemplary embodiment of the present application;

[0020] Figure 2 is a schematic structural diagram of a chip management system shown in an exemplary embodiment of the present application;

[0021] Figure 3 is a schematic diagram of an implementation environment of a power management system shown in an exemplary embodiment of the present application;

[0022] Figure 4 is a flow chart of a power management method shown in an exemplary embodiment of the present application;

[0023] Figure 5 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0024] Figure 6 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0025] Figure 7 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0026] Figure 8 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0027] Fig. 9 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0028] Fig.10 is a flow chart of a power management method shown in another exemplary embodiment of the present application;

[0029] Fig.11 is a schematic diagram of a brief process of power management in an exemplary application scenario;

[0030] Fig.12 is a block diagram of a power management device shown in an exemplary embodiment of the present application;

[0031] Fig.13A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0035] The term "multiple" as used in this application refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0036] First of all, it should be noted that the introduction of the Ethernet DO IP (Diagnostic over IP) diagnostic network has brought revolutionary improvements to the diagnostic information reading and direct Ethernet flashing capabilities of SOC (System on Chip). DO IP is a diagnostic protocol based on the TCP / IP protocol, which allows ECU (electronic control unit) diagnosis, programming and configuration through the IP network. In the SOC diagnostic information reading function, the DO IP protocol ensures that the diagnostic data can be efficiently and accurately transmitted to the remote server or diagnostic tool through Ethernet. DO IP supports high-speed data transmission, so that diagnostic information can be transmitted to the diagnostic end in real time and completely. Compared with traditional CAN bus diagnosis, DO IP diagnosis has a higher data transmission rate and lower latency, thereby improving the accuracy and efficiency of diagnosis. Through the DO IP network, technicians can remotely access the diagnostic information of the SOC and perform fault diagnosis and analysis without having to go to the site in person. This remote access capability not only improves work efficiency, but also reduces maintenance costs. The SOC is directly connected to the flashing device or server via Ethernet, without the need to forward data packets through intermediate links such as MCU. This direct connection method significantly reduces the delay and error rate during the flashing process, and improves the efficiency and reliability of the flashing. Ethernet has the characteristics of high-speed transmission, which makes the flashing process of SOC faster. Compared with the traditional flashing method, Ethernet flashing can significantly shorten the flashing time and reduce production costs.

[0037] Figure 1 FIG. 1 is a schematic diagram of reading chip diagnostic information through an Ethernet diagnostic network (Diagnostic over IP, DO IP) shown in an exemplary embodiment of the present application, such as Figure 1 As shown in the figure, the fault information and detection information of the chip can be read through the DO IP diagnostic network and sent to the corresponding host computer according to the Ethernet switch, where the host computer includes production line electrical inspection equipment, diagnostic instrument, cloud, TBOX, etc., thereby realizing the direct Ethernet flashing capability of the chip. These functions significantly reduce the flashing time of the chip by reducing the data packet forwarding requirements of the Microcontroller Unit (MCU), thereby improving maintenance efficiency.

[0038] Figure 2 is a schematic diagram of the chip management system structure shown in an exemplary embodiment of the present application, such as Figure 2 As shown, the chip and the controller are connected through the GPIO (input and output port) port, and then the chip is connected to the Ethernet switch port 8, and the controller is connected to the Ethernet switch port 10. Then, according to the DO IP diagnosis, the switch must be powered on, and then the switch can be electrically connected to the chip, realizing the direct Ethernet flashing capability of the chip.

[0039] Figure 3 FIG. 1 is a schematic diagram showing an implementation environment of power management in an application process according to an exemplary embodiment of the present application. Figure 3 As shown, during the chip detection and verification process, the controller 110 can obtain the chip status information, and the status information includes the chip power management status. If the power management status indicates that the target management item of the chip is power-off management, a power control instruction can be generated based on the power-off management, and then the electrical connection between Ethernet and the chip can be disconnected according to the control instruction, and the power-on state between Ethernet and the controller can be maintained; if the power-off between Ethernet and the chip is completed, the power-off operation between Ethernet and the controller is controlled. In this way, leakage protection of the chip is achieved. Among them, Figure 3 The controller in the system may be a microcontroller unit (MCU).

[0040] SOC chips generally lack a general-purpose input / output (GPIO) leakage safety protection mechanism. In scenarios where the SOC needs to be powered off separately for maintenance or replacement, such as under high temperature conditions, if the SOC does not have GPIO leakage protection, the Ethernet switch or the GPIO pins connected to the MCU may leak electricity to the SOC, causing damage to the internal circuits of the SOC chip. Damage to the SOC not only increases maintenance costs, but may also cause unplanned downtime of the vehicle system, affecting the user experience and the normal operation of the vehicle.

[0041] The above-mentioned problems are generally applicable in the scenario of DO IP diagnosis of chips. Since SOC chips generally lack GPIO leakage safety protection mechanism, in order to solve these problems, the embodiments of the present application respectively propose a power management method, a power management device, an electronic device, a computer-readable storage medium and a computer program product, which will be described in detail below.

[0042] See also Figure 4 , Figure 4 is a flowchart of a power management method shown in an exemplary embodiment of the present application. The method can be applied to Figure 3 The implementation environment shown is specifically executed by the controller 110 in the implementation environment. It should be understood that the method can also be applied to other exemplary implementation environments and be specifically executed by devices in other implementation environments, and this embodiment does not limit the implementation environment to which the method is applicable.

[0043] like Figure 4As shown, in an exemplary embodiment, the power management method includes at least step S410 and step S440, which are described in detail as follows:

[0044] Step S410, obtaining chip status information, where the status information includes the power management status of the chip.

[0045] Specifically, in order to improve the remote diagnosis and analysis capabilities of the chip and optimize the chip flashing process, the chip diagnostic information reading function of the Ethernet DoIP diagnostic network (Diagnostic over IP, DoIP) was introduced, and the power management status of the chip can be determined through the DO IP network. The power management status includes the power on and off requirements of the chip.

[0046] It should be noted that DoIP is a diagnostic protocol based on the TCP / IP protocol, which uses Ethernet technology to achieve high-speed and stable data transmission. In the automotive field, DoIP technology has gradually been widely used, especially in new energy vehicles, where it has become an important diagnostic communication method. DoIP technology not only supports remote diagnosis and programming, but also enables efficient diagnostic communication between various electronic control units (ECUs) inside the vehicle. The DoIP network can monitor the power management status of the chip in real time, including the power-on and power-off requirements of the chip. This helps to promptly identify power management problems and take appropriate measures to resolve them. Power mode management: In order to better manage the various states of the network, automotive Ethernet introduces a diagnostic power mode. External test equipment can confirm whether reliable diagnostic testing of a certain ECU of the chip is allowed based on whether the current power mode is in diagnostic power mode.

[0047] Step S420: if the target management item of the power management status characterizing the chip is power-off management, a power control instruction is generated based on the power-off management.

[0048] Specifically, if the power management state of the chip indicates that the next target management item of the chip is power-off management, the chip needs to be powered off, but the DO IP diagnostic switch needs to remain powered. When the chip is powered off, the Ethernet switch associated with the chip still has power, which may burn out the chip. Therefore, the port connected to the Ethernet switch and the chip can be powered off, and then a power control instruction for the connected port can be generated. This control process can generate a power control instruction for the connected port of the Ethernet switch with the MCU to power off the port connected between the switch and the chip.

[0049] For example, when the power management status of the chip indicates that its next target management item is power-off management, it means that the chip needs to be powered off. When performing the chip power-off operation, special attention should be paid to the power status of the DO IP diagnostic switch, because the DO IP diagnostic switch needs to remain powered to maintain its function. If the Ethernet switch associated with the chip is still powered after the chip is powered off, the current may continue to flow through the switch to the powered-off chip, thereby damaging the chip.

[0050] To avoid this situation, the port connected to the chip can be powered off. In this way, even if the switch itself remains powered, the port connected to the chip will not provide current to the chip. In order to achieve the above operation, it is necessary to generate a power control instruction for the port connected to the Ethernet switch. This instruction can be generated by the MCU (microcontroller unit). The MCU sends a specific control signal or instruction to the Ethernet switch to turn off the power of the port connected to the chip.

[0051] Step S430: disconnect the electrical connection between the Ethernet and the chip based on the power control instruction, and keep the Ethernet and the controller powered on.

[0052] Specifically, the electrical connection between the Ethernet switch and the chip can be disconnected according to the power control instruction. For example, a specific control signal or instruction generated by the MCU is sent to the Ethernet switch to turn off the power of the port connected to the chip without affecting the normal power-on relationship between the Ethernet switch and the controller MCU.

[0053] Step S440: If the power-off between Ethernet and the chip is completed, the power-off operation between Ethernet and the controller is controlled.

[0054] Specifically, in some embodiments, if the chip diagnostic information reading function of the Ethernet DoIP diagnostic network (Diagnostic over IP, DoIP) is introduced, and the power management status of the chip can be determined through the DO IP network, after the chip diagnosis is completed and the electrical connection between Ethernet and the chip is disconnected, a specific power control signal or control instruction can be further sent to the Ethernet switch through the controller MCU to disconnect the electrical connection between the Ethernet switch and the controller MCU.

[0055] Exemplarily, ensure that the diagnosis of the chip has been thoroughly completed and that all necessary data has been collected and analyzed. Next, disconnect the electrical connection between Ethernet and the chip, which is usually achieved by turning off the power of the Ethernet switch port connected to the chip. After confirming that the chip is disconnected from Ethernet, the MCU can send a specific power control signal or instruction to the Ethernet switch. The purpose of this signal or instruction is to instruct the switch to turn off the power of a specific port connected to the MCU or the entire switch (if the entire switch is no longer needed). After receiving the power control signal from the MCU, the Ethernet switch will perform the corresponding operation to disconnect the electrical connection with the MCU. This may involve shutting down a port of the switch, putting the entire switch into low power mode, or completely powering off.

[0056] In this embodiment, when it is detected that the chip needs to be powered off, the port between the Ethernet and the chip is powered off first, thereby avoiding GPIO leakage, thereby solving the problem of chip burning due to leakage, and through sophisticated power management, it can ensure that the system responds quickly and switches to the correct power state when needed. This helps to reduce system crashes or data loss caused by power problems, thereby improving the overall stability and reliability of the system, and through reasonable power-off management, it can avoid unnecessary power fluctuations and overheating, thereby extending the service life of the chip and the entire system.

[0057] Further, based on the above embodiments, please refer to Figure 5 In one of the exemplary embodiments provided in the present application, the controller includes a register, and the specific implementation process of generating a power control instruction based on power-off management may also include step S510 and step S520, which are described in detail as follows:

[0058] Step S510, generating a power control register value corresponding to the register based on the power control instruction;

[0059] Step S520, writing the power control register value into the controller to disconnect the port between the Ethernet and the chip.

[0060] Specifically, the controller (MCU) contains multiple registers, which are used to store various status information, control parameters, etc. In this scenario, special attention is paid to registers related to power control. When the connection between Ethernet and the chip needs to be disconnected, the controller will receive a power control instruction. This instruction will be parsed and converted into one or more power control register values. These register values ​​represent the specific power control operations to be performed, such as shutting down the Ethernet switch port connected to the chip. Once the power control register values ​​are determined, they will be written to the corresponding registers inside the controller. This write operation will trigger the controller to execute the corresponding power control logic. According to the written power control register value, the controller will send a signal or instruction to the Ethernet switch, requiring it to shut down the port connected to the chip. After receiving this signal or instruction, the switch will perform the corresponding operation to disconnect the electrical connection with the chip.

[0061] In addition, in order to ensure the safety and reliability of the operation, for example, the integrity and authenticity of the instruction can be ensured through checksum, encryption and other measures. At the same time, it is also necessary to monitor the execution results of the operation to ensure that the port has been disconnected correctly.

[0062] In this embodiment, by directly operating the power control register, precise control of the power state can be achieved. This control method is more direct and efficient than traditional software-level control, and can respond to different power management requirements more flexibly. Directly operating registers through software-level power control instructions can simplify hardware design. Traditionally, additional hardware circuits may be required to implement power management functions. Now, through the coordination of software instructions and registers, similar power management effects can be achieved without increasing hardware complexity.

[0063] Further, based on the above embodiments, please refer to Figure 6 In one of the exemplary embodiments provided in the present application, the specific implementation process of the power management method may further include step S610 and step S620, which are described in detail as follows:

[0064] Step S610, generating a power off signal based on the power control register value;

[0065] Step S620: Control the port between the Ethernet and the chip to be disconnected based on the power disconnection signal, and control the port not to send synchronization data to the host computer.

[0066] Specifically, when the power control register values ​​are correctly written to the controller, these values ​​are interpreted as one or more power management instructions. Based on these instructions, the controller generates a power disconnect signal. This signal is an electrical signal or a digital signal used to indicate that the Ethernet switch port connected to the chip needs to be disconnected. The controller sends this power disconnect signal to the Ethernet switch through internal logic or interface circuits. After receiving this signal, the switch will perform corresponding hardware operations to disconnect the port connected to the chip, which may involve turning off the physical switch of the port, stopping data transmission, etc. At the same time as the port is disconnected, the controller also needs to ensure that the port no longer sends any synchronous data to the host computer. This can be achieved by setting the corresponding flag bit or state variable inside the controller to prevent any data from being transmitted from the disconnected port to the host computer. In addition, if the switch or system supports higher-level data flow control (such as flow control, error detection, etc.), it is also necessary to ensure that these mechanisms can operate correctly after the port is disconnected to prevent data loss or damage.

[0067] It should be noted that RGMII (Reduced Gigabit Media Independent Interface) is an interface standard for Gigabit Ethernet communication. It provides a transmission path for data, clock and control signals for transmitting data between MAC (Media Access Controller) and PHY (Physical Layer). PHY contains multiple registers to control its behavior and status. By writing specific register values, the behavior of PHY can be forced to be controlled, including the switching of link status. Software (such as driver or firmware) communicates with PHY through the MDIO (Management Data Input / Output) bus, which allows software to read and write registers of PHY. By writing specific register values, software can force the link status to be set to "disconnected". First, the address of the PHY register used to control the link status and the value to be written need to be determined. This information can usually be found in the specification or data manual of PHY. According to the determined register address and value, write the corresponding software code. The code should contain the logic of communicating with PHY through the MDIO bus and the operation of writing register values.

[0068] In this embodiment, when the port between the Ethernet and the chip is disconnected, it is ensured that the port does not send synchronization data to the host computer, which can effectively prevent data leakage or illegal access. The process of generating a power disconnection signal based on the power control register value is usually very fast, and the port disconnection and data transmission can be terminated in a short time.

[0069] Further, based on the above embodiments, please refer to Figure 7 In one of the exemplary embodiments provided in the present application, the specific implementation process of the above power management method may also include steps S710 to S730, which are described in detail as follows:

[0070] Step S710, determining the bit field of the clock signal corresponding to the port in the register;

[0071] Step S720, generating a clock signal control instruction for a clock signal based on the power control register value and the bit field;

[0072] Step S730, based on the clock signal control instruction, the data on the bit field is cleared to turn off the clock signal so that the clock signal does not send synchronous data to the host computer.

[0073] Specifically, first, you need to determine which register controls the clock signal associated with a specific port. This usually involves consulting a hardware manual or data sheet to find the register that controls the clock signal and its address. After determining the control register, you need to find the specific bit field in the register that controls the clock signal. A bit field usually refers to a group of consecutive bits in a register that together control a specific function or configuration. In this case, the bit field may be labeled as clock enable, clock select, or other labels related to the clock signal. In some cases, the power control register value may be used as an input or reference to generate a clock signal control instruction. This means that the state or value of the power control register may affect the specific content of the clock signal control instruction. Combining the power control register value and the bit field information, a specific clock signal control instruction can be generated. The control instruction is usually a binary value that will be written to the control register to change the value of the bit field. In this step, you may need to determine the value to be written in order to clear the clock signal enable bit (i.e., turn off the clock signal).

[0074] Exemplarily, by writing a specific register bit (such as 0x4A4100A4 bit2=0 in the example), the transmit clock signal can be turned off. Turning off the TXC clock signal means that the transmitter will not send data, because the transmission of data requires a clock signal to synchronize. Bit2=0 means that the second bit of the register is cleared. This means that the functions related to the RGMII TXC clock are turned off. Through the above steps, it can be ensured that the transmitter of the RGMII interface will not send data, so that no waveform is generated. This has been verified through actual testing, which is manifested as a low-level state on the relevant line.

[0075] In this embodiment, by turning off unnecessary clock signals, the dynamic power consumption of the chip can be reduced. Continuous clock signals may cause unnecessary wear or damage to the hardware. By dynamically turning off the clock signal, the service life of the hardware can be extended and the reliability of the system can be improved. By turning off the clock signal, the synchronous data can be prevented from being sent to the host computer, thereby protecting the security of the data.

[0076] Further, based on the above embodiments, please refer to Figure 8 In one of the exemplary embodiments provided in the present application, the specific implementation process of the above power management method may also include steps S810 to S830, which are described in detail as follows:

[0077] Step S810, if the chip is in a power-off state and receives a power-on detection request, then detect whether the Ethernet power supply is normal;

[0078] Step S820: If the Ethernet power supply is normal, clear the residual data between the Ethernet switch and the chip to restart the Ethernet;

[0079] Step S830, establishing an electrical connection between the restarted Ethernet and the chip.

[0080] Specifically, when the chip is in a power-off state (i.e., no power or power-off state), it will not perform any operations. Once the chip receives a power-on detection request (which is usually a signal sent by the power management system), it will start the initialization process. If the Ethernet power supply is normal (i.e., the power pin or signal is at the expected level), the chip will continue to perform subsequent operations. If the Ethernet power supply is normal, the chip will perform an operation to clear residual data. This usually involves clearing residual data in the communication buffer, status register or other related data structure between the Ethernet switch. The purpose of clearing residual data is to ensure that the Ethernet can start working in a clean state after restarting. After clearing the residual data, the chip will send a restart signal to the Ethernet switch (if the switch supports remote restart) or perform an internal restart process. The restart process may include reinitializing the Ethernet interface, resetting related registers, or performing other necessary operations. Once the Ethernet restart is completed, the chip will try to establish an electrical connection with the restarted Ethernet. This usually involves configuring the relevant physical layer interface (such as PHY) and the media access control layer (MAC) to establish a stable communication link. In this process, the chip may perform operations such as link layer negotiation, rate matching, and error detection. Once the electrical connection is established, the chip verifies that the connection to the Ethernet network is stable and valid. This may involve sending and receiving test packets, checking error rates and packet loss rates, etc.

[0081] In this embodiment, by detecting the power supply status of Ethernet at power-on, it can be ensured that Ethernet is in normal working state before restarting, thereby avoiding communication failures caused by abnormal power supply. Clearing residual data between the switch and the chip can prevent data conflicts or inconsistencies, ensure that Ethernet can work normally after restarting, and help improve the stability and reliability of the system.

[0082] Further, based on the above embodiments, please refer to Fig. 9 In one of the exemplary embodiments provided in the present application, the specific implementation method of the above power management method may further include step S910 and step S920, which are described in detail as follows:

[0083] Step S910, in the process of electrical connection between Ethernet and chip, obtaining the power-on status of the chip, the power-on status including the power-on voltage and the power-on current;

[0084] Step S920: If the power-on voltage reaches a preset voltage threshold or the power-on current reaches a preset current threshold, a power-off control instruction is generated between the Ethernet and the chip.

[0085] Specifically, in the process of establishing an electrical connection between Ethernet and the chip, the power-on voltage and power-on current of the chip need to be obtained in real time. This is usually achieved by connecting to the power management pin of the chip or a dedicated monitoring circuit. The monitoring circuit can be an integrated power management module that can measure and report voltage and current values. The actual values ​​of the power-on voltage and power-on current obtained are compared with the preset thresholds. If the actual value exceeds the preset voltage threshold or current threshold (depending on whether the threshold is set to the maximum value or the minimum value), it may indicate a power problem or chip abnormality. If the power-on voltage reaches the preset voltage threshold (usually the maximum value to avoid overvoltage damage) or the power-on current reaches the preset current threshold (which may be the maximum value to avoid overload or short circuit), the system needs to take protective measures. In this case, the decision logic will trigger the generation of a power-off control instruction. This instruction can be generated by the MCU (microcontroller unit), which sends a specific control signal or instruction to the Ethernet switch to turn off the port power connected to the chip. Then the power-off operation between the Ethernet switch and the chip is realized.

[0086] In this embodiment, by monitoring the power-on voltage and power-on current, overvoltage or overcurrent in the power supply process can be detected and prevented in time, thereby protecting the chip and Ethernet device from damage. Stable power supply is the basis for the normal operation of the device. By real-time monitoring of the power-on situation, it can be ensured that the power supply is in a stable state to supply power to the device, avoiding device failures caused by power fluctuations.

[0087] Further, based on the above embodiments, please refer to Fig.10In one of the exemplary embodiments provided in the present application, the specific implementation process of the above power management method may further include step S1010 and step S1020, which are described in detail as follows:

[0088] Step S1010, obtaining temperature information of the chip, where the temperature information includes the surface temperature of the chip;

[0089] Step S1020: If the surface temperature reaches a preset temperature threshold, the electrical connection between the Ethernet and the chip is disconnected, and the chip is controlled to perform power-off management.

[0090] Specifically, one or more temperature monitoring sensors are usually installed near the chip or integrated inside the chip. These sensors can measure and report the surface temperature of the chip in real time. If the surface temperature of the chip reaches the preset overheat protection threshold (usually the upper limit), it indicates that the chip may be experiencing overheating. If the surface temperature of the chip reaches the preset overheat protection threshold, the system needs to take immediate measures to protect the chip and other components connected to it. This may include disconnecting the electrical connection between the Ethernet and the chip to prevent further heat generation or data transmission errors. After disconnecting the Ethernet connection, the system needs to control the chip for power-off management, which may include turning off the power supply of the chip, putting the chip in low power mode or completely powering off, etc. The purpose of power-off management is to ensure that the chip will not be further damaged in the event of overheating and to prepare for system recovery.

[0091] In this embodiment, by monitoring the surface temperature of the chip, potential overheating problems can be discovered in time. When the temperature reaches the preset threshold, the Ethernet connection is disconnected in time and power is turned off, which can effectively prevent safety accidents such as equipment damage or fire caused by overheating. Overheating may cause abnormal operation of the chip, thereby affecting the stability of the entire system. Through temperature monitoring and timely response, it can ensure that the chip operates within an appropriate temperature range, thereby improving the stability and reliability of the entire system.

[0092] Fig.11It is a brief flowchart of power management in an exemplary application scenario. In the application scenario shown in 11, the status information of the chip is obtained, and the status information includes the power management status of the chip; if the power management status represents that the target management item of the chip is power-off management, a power control instruction is generated based on the power-off management; a power control register value corresponding to the register is generated based on the power control instruction; a power disconnection signal is generated based on the power control register value; the port between Ethernet and the chip is disconnected based on the power disconnection signal, and the port is controlled not to send synchronous data to the host computer. In addition, the bit field of the clock signal corresponding to the port in the register is determined; a clock signal control instruction of the clock signal is generated based on the power control register value and the bit field; the data on the bit field is cleared based on the clock signal control instruction to turn off the clock signal so that the clock signal does not send synchronous data to the host computer. For the detailed implementation process, please refer to the records in the aforementioned embodiments, which will not be repeated here.

[0093] Fig.12 is a block diagram of a power management device shown in an exemplary embodiment of the present application. The device can be applied to Figure 3 The implementation environment shown in the figure is specifically configured in the controller 310. The device can also be applied to other exemplary implementation environments and specifically configured in other devices. This embodiment does not limit the implementation environment to which the device is applied.

[0094] like Fig.12 As shown, the exemplary power management device includes: an acquisition module 1210, used to acquire the management status of the chip, the management status including the power management status of the chip; a generation module 1220, used to generate a power control instruction based on the power-off management if the power management status characterizes that the target management item of the chip is power-off management; a disconnection module 1230, used to disconnect the electrical connection between Ethernet and the chip based on the power control instruction, and keep the power-on state between Ethernet and the controller; a control module 1240, used to control the power-off operation between Ethernet and the controller if the power-off between Ethernet and the chip is completed.

[0095] According to one aspect of an embodiment of the present application, the above-mentioned generation module 1220 is also used to generate a power control register value corresponding to the register based on the power control instruction; and write the power control register value into the controller to disconnect the port between the Ethernet and the chip.

[0096] According to one aspect of an embodiment of the present application, the above-mentioned generation module 1220 is also used to generate a power disconnection signal based on the power control register value; control the port disconnection between Ethernet and the chip based on the power disconnection signal, and control the port not to send synchronization data to the host computer.

[0097] According to one aspect of an embodiment of the present application, the above-mentioned generation module 1220 is also used to determine the bit field of the clock signal corresponding to the port in the register; generate a clock signal control instruction for the clock signal based on the power control register value and the bit field; and clear the data on the bit field based on the clock signal control instruction to turn off the clock signal so that the clock signal does not send synchronous data to the host computer.

[0098] According to one aspect of an embodiment of the present application, the power management device also includes a detection module for detecting whether the Ethernet is powered normally if the chip is in a power-off state and receives a power-on detection request; if the Ethernet is powered normally, clearing the residual data between the Ethernet switch and the chip to restart the Ethernet; and establishing an electrical connection between the restarted Ethernet and the chip.

[0099] According to one aspect of an embodiment of the present application, the above-mentioned power management device also includes a power-on detection module, which is used to obtain the power-on status of the chip during the electrical connection between Ethernet and the chip, and the power-on status includes the power-on voltage and the power-on current; if the power-on voltage reaches a preset voltage threshold or the power-on current reaches a preset current threshold, a power-off control instruction is generated between Ethernet and the chip.

[0100] According to one aspect of an embodiment of the present application, the above-mentioned power management device also includes a temperature module for obtaining temperature information of the chip, the temperature information including the surface temperature of the chip; if the surface temperature reaches a preset temperature threshold, the electrical connection between Ethernet and the chip is disconnected, and the chip is controlled to perform power-off management.

[0101] It should be noted that the power management device provided in the above embodiment and the power management method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiment, and will not be repeated here. In practical applications, the power management device provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0102] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by one or more processors, the electronic device implements the power management method provided in the above-mentioned embodiments.

[0103] Fig.13 The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Fig.13The computer system 1300 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0104] like Fig.13 As shown, the computer system 1300 includes a central processing unit (CPU) 1301, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1302 or the program loaded from the storage part 1308 to the random access memory (RAM) 1303, such as executing the method described in the above embodiment. In the RAM 1303, various programs and data required for system operation are also stored. The CPU 1301, the ROM 1302 and the RAM 1303 are connected to each other through the bus 1304. The input / output (I / O) interface 1305 is also connected to the bus 1304.

[0105] The following components are connected to the I / O interface 1305: an input section 1306 including a keyboard, a mouse, etc.; an output section 1307 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1308 including a hard disk, etc.; and a communication section 1309 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1309 performs communication processing via a network such as the Internet. A drive 1310 is also connected to the I / O interface 1305 as needed. A removable medium 1311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1310 as needed so that a computer program read therefrom is installed into the storage section 1308 as needed.

[0106] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 1309, and / or installed from a removable medium 1311. When the computer program is executed by a central processing unit (CPU) 1301, various functions defined in the system of the present application are executed.

[0107] It should be noted that the computer-readable medium shown in the embodiment of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. This propagated data signal can take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0108] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0109] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0110] Another aspect of the present application further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the power management method as described above is implemented. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0111] Another aspect of the present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the power management method provided in each of the above embodiments.

[0112] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A power management method, characterized in that: Applied to a chip management system, the chip management system includes a chip, an Ethernet and a controller, the controller is used to control the connection between the Ethernet and the chip, and forward the management message of the chip to the corresponding host computer through the Ethernet, the method includes: Acquire status information of the chip, wherein the status information includes a power management status of the chip; If the power management state indicates that the target management item of the chip is power-off management, generating a power control instruction based on the power-off management; Disconnecting the electrical connection between the Ethernet and the chip based on the power control instruction, and maintaining the power-on state between the Ethernet and the controller; If the power-off between the Ethernet and the chip is completed, the power-off operation between the Ethernet and the controller is controlled.

2. The method according to claim 1, characterized in that The controller includes a register, and the generating of a power control instruction based on the power-off management includes: generating a power control register value corresponding to the register based on the power control instruction; The power control register value is written into the controller to disconnect the port between the Ethernet and the chip.

3. The method according to claim 2, characterized in that The method further comprises: generating a power off signal based on the power control register value; Based on the power disconnection signal, the port between the Ethernet and the chip is controlled to be disconnected, and the port is controlled not to send synchronization data to the host computer.

4. The method according to claim 3, characterized in that The controlling the port not to send synchronization data comprises: Determine a bit field of a clock signal corresponding to the port in the register; a clock signal control instruction for generating the clock signal based on the power control register value and the bit field; Based on the clock signal control instruction, the data on the bit field is cleared to turn off the clock signal so that the clock signal does not send synchronous data to the host computer.

5. The method according to claim 1, characterized in that The method further comprises: If the chip is in a power-off state and receives a power-on detection request, detecting whether the Ethernet power supply is normal; If the Ethernet power supply is normal, clearing the residual data between the Ethernet switch and the chip to restart the Ethernet; An electrical connection is established between the restarted Ethernet and the chip.

6. The method according to claim 5, characterized in that The method further comprises: During the electrical connection between the Ethernet and the chip, obtaining a power-on status of the chip, wherein the power-on status includes a power-on voltage and a power-on current; If the power-on voltage reaches a preset voltage threshold or the power-on current reaches a preset current threshold, a power-off control instruction is generated between the Ethernet and the chip.

7. The method according to claim 1, characterized in that The method further comprises: Acquiring temperature information of the chip, wherein the temperature information includes a surface temperature of the chip; If the surface temperature reaches a preset temperature threshold, the electrical connection between the Ethernet and the chip is disconnected, and the chip is controlled to perform power-off management.

8. A power management device, characterized in that: Applied to a chip management system, the chip management system includes a chip, an Ethernet and a controller, the controller is used to control the connection between the Ethernet and the chip, and forward the management message of the chip to the corresponding host computer through the Ethernet, the device includes: An acquisition module, used for acquiring the management state of the chip, wherein the management state includes the power management state of the chip; A generating module, configured to generate a power control instruction based on the power-off management if the power management state indicates that the target management item of the chip is power-off management; A disconnection module, configured to disconnect the electrical connection between the Ethernet and the chip based on the power control instruction, and maintain the power-on state between the Ethernet and the controller; The control module is used for controlling the power-off operation between the Ethernet and the controller if the power-off between the Ethernet and the chip is completed.

9. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the power management method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is enabled to execute the power management method according to any one of claims 1 to 7.

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