Memory management method and memory storage device

Abstract

The invention provides a memory management method and a memory storage device. The service life of the memory storage device can be prolonged. The memory management method is used for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory management method comprises the following steps: executing a detection operation on a plurality of entity units to obtain a plurality of detection results respectively corresponding to the plurality of entity units; generating an entity unit bitmap based on the plurality of detection results; according to the entity unit bitmap and a preset condition, a target entity unit is selected from the multiple entity units, and the preset condition is used for representing that the target entity unit comprises a first type of entity units and a second type of entity units; executing the target operation to replace the first-class entity unit or the second-class entity unit, and taking the replaced first-class entity unit or the replaced second-class entity unit as a standby entity unit; and updating the entity unit bitmap.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a memory storage device. Background Art

[0002] With the rapid evolution of flash memory technology, NAND flash memory has undergone a transformation from two-dimensional (2D) to three-dimensional (3D), and in terms of storage units, it has also gradually evolved from single-layer storage units (SLC) to three-layer (TLC) and even four-layer (QLC) storage units. This series of technological innovations has greatly improved the storage density of NAND flash memory and reduced the cost per unit capacity. However, as the thickness of the oxide layer inside the flash memory continues to decrease, the impact of the erase and write operation on the storage medium has become more significant, thus affecting the durability and reliability of the flash memory.

[0003] The memory storage device can perform a self-test operation to mark the physical cells with errors in the rewritable non-volatile memory module as bad physical cells within a certain number of program / erase cycles (PE cycles). The bad physical cells will no longer be used in subsequent data access operations.

[0004] How to optimize the management strategy of physical units to improve the accuracy of marking will not only help extend the service life of flash memory, but also further improve the overall performance and stability of the system, ensuring that users have a smoother and more reliable user experience. Summary of the invention

[0005] An exemplary embodiment of the present invention provides a memory management method and a memory storage device, which can fully utilize the storage space of the memory storage device to increase the service life of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of sub-physical units, and the memory management method includes: performing a detection operation on the plurality of physical units to obtain a plurality of detection results corresponding to the plurality of physical units respectively; generating a physical unit bitmap based on the plurality of detection results; selecting a target physical unit from the plurality of physical units according to the physical unit bitmap and a preset condition, wherein the preset condition is used to characterize that the target physical unit includes a first type of physical unit and a second type of physical unit; performing a target operation to replace the first type of physical unit or the second type of physical unit, and using the replaced first type of physical unit or the replaced second type of physical unit as a spare physical unit; and updating the physical unit bitmap.

[0007] In an exemplary embodiment of the present invention, the detection operation includes a first detection operation and a second detection operation, wherein the detection result corresponding to the first type of entity unit is used to characterize that the first detection operation is successful and the second detection operation is a failure, and the detection result corresponding to the second type of entity unit is used to characterize that the second detection operation is successful and the first detection operation is a failure.

[0008] In an exemplary embodiment of the present invention, the detection result corresponding to the third type of entity unit is used to indicate that the first detection operation and the second detection operation are both successful, and the detection result corresponding to the fourth type of entity unit is used to indicate that the first detection operation and the second detection operation are both failed.

[0009] In an exemplary embodiment of the present invention, the first detection operation is a single-level memory cell read detection operation, and the second detection operation is a triple-level memory cell read detection operation.

[0010] In an exemplary embodiment of the present invention, the step of generating the entity unit bitmap based on the multiple detection results includes: classifying each of the multiple sub-entity units in the multiple entity units based on the multiple detection results to obtain a classification result, wherein the classification result includes the first type of entity units, the second type of entity units, the third type of entity units and the fourth type of entity units; and generating the entity unit bitmap according to the classification result, wherein the entity unit bitmap is used to reflect that the multiple sub-entity units in the multiple entity units are respectively the first type of entity units, the second type of entity units, the third type of entity units or the fourth type of entity units.

[0011] In an exemplary embodiment of the present invention, the step of performing the target operation to replace the first type entity unit or the second type entity unit includes: replacing the first type entity unit or the second type entity unit in the target entity unit with the third type entity unit.

[0012] In an exemplary embodiment of the present invention, the memory management method further includes: replacing the fourth type of physical unit with the spare physical unit based on the physical unit bitmap.

[0013] In an exemplary embodiment of the present invention, the memory management method also includes: based on the physical unit bitmap, selecting a target write physical unit corresponding to the write mode of the write instruction, and writing the write data corresponding to the write instruction into the target write physical unit, wherein the target write physical unit is the first type of physical unit or the second type of physical unit; and after the target write physical unit is full, performing a read verification operation on the target write physical unit.

[0014] In an exemplary embodiment of the present invention, the memory management method further includes: based on the physical unit bitmap, setting a first read count threshold and a second read count threshold for the first type of physical units and the second type of physical units, respectively, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of physical units.

[0015] In an exemplary embodiment of the present invention, the memory management method further comprises: in an idle state, based on the physical cell bitmap, performing a read verification operation on the first type of physical cells storing data and the second type of physical cells storing data.

[0016] The exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical units. Each of the plurality of physical units includes a plurality of sub-physical units. The memory control circuit unit is used to perform a detection operation on the plurality of physical units to obtain a plurality of detection results corresponding to the plurality of physical units respectively. The memory control circuit unit is also used to generate a physical unit bitmap based on the plurality of detection results. The memory control circuit unit is also used to select a target physical unit from the plurality of physical units according to the physical unit bitmap and a preset condition, wherein the preset condition is used to characterize that the target physical unit includes a first type of physical unit and a second type of physical unit. The memory control circuit unit is also used to perform a target operation to replace the first type of physical unit or the second type of physical unit, and use the replaced first type of physical unit or the replaced second type of physical unit as a spare physical unit. The memory control circuit unit is also used to update the physical unit bitmap.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to classify each of the plurality of sub-entity units in the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein the classification result includes the first type of entity units, the second type of entity units, the third type of entity units, and the fourth type of entity units. The memory control circuit unit is further used to generate the entity unit bitmap according to the classification result, wherein the entity unit bitmap is used to reflect that the plurality of sub-entity units in the plurality of entity units are the first type of entity units, the second type of entity units, the third type of entity units, or the fourth type of entity units, respectively.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to replace the first-type physical unit or the second-type physical unit in the target physical unit with the third-type physical unit.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to replace the fourth type of physical cell with the spare physical cell based on the physical cell bitmap.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select a target write physical unit corresponding to a write mode of a write instruction based on the physical unit bitmap, and write the write data corresponding to the write instruction into the target write physical unit, wherein the target write physical unit is the first type of physical unit or the second type of physical unit. The memory control circuit unit is further configured to perform a read verification operation on the target write physical unit after the target write physical unit is fully written.

[0021] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to set a first read count threshold and a second read count threshold for the first type of physical unit and the second type of physical unit, respectively, based on the physical unit bitmap, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of physical unit.

[0022] In an exemplary embodiment of the present invention, in an idle state, the memory control circuit unit is further configured to perform a read verification operation on the first type of physical cells storing data and the second type of physical cells storing data based on the physical cell bitmap.

[0023] Based on the above, the present invention provides a memory management method and a memory storage device, which can fully utilize the storage space of the rewritable non-volatile memory module while maintaining the correctness of the data stored in the rewritable non-volatile memory module, so as to effectively improve the service life and performance of the memory storage device.

[0024] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a system and a storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention;

[0032] Figure 8 is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0033] Fig. 9 is a schematic diagram of the structure of a physical unit bitmap according to an exemplary embodiment of the present invention;

[0034] Fig.10 is a flow chart of a memory management method according to an exemplary embodiment of the present invention;

[0035] Fig.11 is a flow chart of a memory management method according to an exemplary embodiment of the present invention;

[0036] Fig.12 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0039] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0040] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0041] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0042] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0043] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0044] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the host system 11 is a vehicle-mounted system. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0045] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0047] Figure 4 is a block diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0049] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0050] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0051] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0052] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0053] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0054] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical unit is the smallest unit of erasure. That is, each physical unit contains the minimum number of storage cells that are erased together. For example, the physical unit is a physical block.

[0055] Figure 5 is a block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0056] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0057] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0059] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0060] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0061] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0062] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These command sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0063] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0064] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0065] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0066] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0067] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0068] Please refer to Figure 6 , the memory management circuit 51 can logically group the physical units 610(0)-610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. A physical unit refers to a virtual block (VB). For example, a virtual block may include multiple physical programming units. For example, a virtual block may include multiple physical erasing units. For example, a virtual block may include one or more physical units.

[0069] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0070] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0071] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in this physical unit contains valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in this physical unit does not contain any valid data.

[0072] The memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may perform a data access operation on the memory storage device 10 according to the information in the logical-to-physical mapping table.

[0073] In order to fully utilize the storage space of the memory storage device 10 and to extend the service life of the memory storage device 10, the present invention provides a memory management method. Generally speaking, on a production line, the memory storage device 10 can perform a self-test operation to mark the physical unit in which an error occurs in the rewritable non-volatile memory module 43 within a certain number of programming / erase cycles (PE cycles), and record the error physical unit in a bad block table, and no longer use the physical unit recorded in the bad block table in subsequent data access operations.

[0074] Among them, the physical units recorded in the bad block table may be, for example, bad physical units inherent in the memory storage device 10 when it leaves the factory (early bad blocks) and bad physical units generated during a self-test operation or when a subsequent data access operation fails (for example, a physical unit in which an erase operation fails and / or a write operation fails, or a physical unit in which a read verification operation fails) (later bad blocks).

[0075] The conventional self-test operation may be, for example, to perform an erase operation, a write operation, and a read detection operation on all physical cells in the rewritable non-volatile memory module 43 in sequence through the memory management circuit 51, wherein the read detection operation includes two kinds of read detection operations, for example, a single-level cell (SLC) read detection operation and an X-level cell (XLC) read detection operation, wherein X is an integer greater than 1 and may vary according to the specifications of the memory storage device 10. For example, the X-level cell read detection operation may be a second-level cell (MLC) read detection operation, a third-level cell (TLC) read detection operation, or a fourth-level cell (QLC) read detection operation. For example, the read detection operation may include a single-level cell read detection operation and a third-level cell read detection operation. If an error occurs in the single-level cell read detection operation and / or the third-level cell read detection operation in the read detection operation for a physical cell, the physical cell is determined to be a bad physical cell and is recorded in the bad block table.

[0076] However, if a physical cell only has an error in a single-level storage cell read detection operation in the read detection operation, but does not have an error in a three-level storage cell read detection operation, then this physical cell can be successfully accessed in the three-level storage cell (TLC) mode. Accordingly, the memory management method provided by the present invention can increase the storage space of the rewritable non-volatile memory module 43 by putting only a physical cell with an error in a read detection operation into subsequent data access operations during the self-test operation of the memory storage device 10, thereby improving the service life of the memory storage device 10.

[0077] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention; Figure 8 is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention; Fig. 9 is a schematic diagram of the structure of a physical unit bitmap according to an exemplary embodiment of the present invention. Figures 7 to 9 Specifically, Figure 7 The memory management method is associated with a self-test operation. In an exemplary embodiment, Figure 8 As shown, the rewritable non-volatile memory module 43 may, for example, include physical planes P0 and P1, wherein the physical planes P0 and P1 respectively include sub-physical units B(0)~B(N), wherein the multiple sub-physical units B(0)~B(N) in the physical planes P0 and P1 are respectively used to form multiple physical units V(0)~V(N).

[0078] In step S701, the memory management circuit 51 may perform an erase operation on a plurality of physical units V(0)-V(N). Specifically, the memory management circuit 51 may clear all data stored in the sub-physical units B(0)-B(N) in the physical planes P0 and P1.

[0079] In step S702, the memory management circuit 51 may continue to perform write operations on multiple physical units V(0)-V(N). Specifically, the memory management circuit 51 may write the test data of the self-test operation into the multiple physical units V(0)-V(N). In other words, the memory management circuit 51 may write the test data of the self-test operation into the sub-physical units B(0)-B(N) in the physical planes P0 and P1.

[0080] It should be noted that in step S701 (or step S702), if an erase operation (or write operation) fails on any sub-entity unit, the sub-entity unit is recorded as a fourth-category entity unit and is no longer used in subsequent data access operations.

[0081] In step S703, the memory management circuit 51 may perform a detection operation on the plurality of physical cells V(0)-V(N) to obtain a plurality of detection results respectively corresponding to the plurality of physical cells V(0)-V(N). In an exemplary embodiment, the detection operation includes a first detection operation and a second detection operation. The first detection operation may be, for example, a single-level cell (SLC) read detection operation, and the second detection operation may be, for example, a second-level cell (MLC) read detection operation, a third-level cell (TLC) read detection operation, or a fourth-level cell (QLC) read detection operation. Specifically, the memory management circuit 51 may perform an SLC read verification operation and a TLC read verification operation on the sub-physical cells B(0)-B(N) in the physical planes P0 and P1, respectively, to determine whether the test data of the self-test operation is correctly written into the sub-physical cells B(0)-B(N) in step S702, and generate a plurality of detection results respectively corresponding to the physical cells V(0)-V(N) according to the results of the SLC read verification operation and the TLC read verification operation.

[0082] Next, the memory management circuit 51 may generate a physical unit bitmap 91 based on the multiple detection results. Specifically, in step S704, the memory management circuit 51 may classify each of the sub-physical units B(0)-B(N) in the multiple physical units V(0)-V(N) based on the multiple detection results to obtain a classification result. Specifically, the memory management circuit 51 may classify the physical units B(0)-B(N) in the physical planes P0 and P1 respectively based on the multiple detection results generated in step S703 to obtain a classification result. In an exemplary embodiment, the classification result includes a first type of physical unit, a second type of physical unit, a third type of physical unit, and a fourth type of physical unit.

[0083] For example, the detection result corresponding to the first type of physical cell is used to indicate that the first detection operation (i.e., the SLC read verification operation) is successful and the second detection operation (i.e., the TLC read verification operation) is failed. In other words, the first type of physical cell can be successfully accessed in the SLC mode. For example, the detection result corresponding to the second type of physical cell is used to indicate that the second detection operation is successful and the first detection operation is failed. In other words, the second type of physical cell can be successfully accessed in the TLC mode.

[0084] For example, the detection result corresponding to the third type of physical cell (also called a good physical cell) is used to indicate that both the first detection operation and the second detection operation are successful. Accordingly, in both the single-level cell (SLC) mode and the triple-level cell (TLC) mode, the memory management circuit 51 can use the third type of physical cell to perform data access operations. For example, the detection result corresponding to the fourth type of physical cell (also called a bad physical cell) is used to indicate that both the first detection operation and the second detection operation are failed. Accordingly, in subsequent data access operations, the memory management circuit 51 no longer uses the fourth type of physical cell.

[0085] In addition, in step S705, the memory management circuit 51 may generate a physical unit bitmap 91 according to the classification result. Specifically, the physical unit bitmap 91 may be used to reflect that the sub-physical units B(0) to B(N) in the plurality of physical units V(0) to V(N) are first-class physical units, second-class physical units, third-class physical units, or fourth-class physical units, respectively.

[0086] like Fig. 9As shown, the sub-entity elements B(0), B(1), and B(3) in the physical plane P0 and the sub-entity element B(0) in the physical plane P1 are first-type entity elements. The sub-entity elements B(3) and B(N) in the physical plane P1 are second-type entity elements. The sub-entity elements B(2) and B(N) in the physical plane P0 and the sub-entity element B(2) in the physical plane P1 are third-type entity elements. The sub-entity element B(1) in the physical plane P1 is a fourth-type entity element.

[0087] Further, in step S706, the memory management circuit 51 may select a target physical unit from the plurality of physical units V(0)-(N) according to the physical unit bitmap 91 and the preset condition. In an exemplary embodiment, the preset condition is used to indicate that the target physical unit includes a first type of physical unit and a second type of physical unit. Specifically, Fig. 9 As shown, the sub-entity unit B(3) belonging to the physical plane P(0) is a first-type physical unit, and the sub-entity unit B(3) belonging to the physical plane P(1) is a second-type physical unit. Therefore, the memory management circuit 51 can select the physical unit V(3) as the target physical unit.

[0088] Next, the memory management circuit 51 may perform a target operation to replace the first-type physical unit or the second-type physical unit in the physical unit V(3), and use the replaced first-type physical unit or the replaced second-type physical unit as a spare physical unit. Specifically, in step S707, the memory management circuit 51 may replace the first-type physical unit or the second-type physical unit in the target physical unit (i.e., the physical unit V(3)) with a third-type physical unit, and use the replaced first-type physical unit or the replaced second-type physical unit as a spare physical unit. In an exemplary embodiment, Fig. 9 As shown, the memory management circuit 51 can replace the first type of entity unit in the entity unit V(3) (i.e., the sub-entity unit B(3) in the entity plane P0) with the third type of entity unit, and use the replaced sub-entity unit B(3) in the entity plane P0 as a spare entity unit to complete the target operation. In another embodiment, the memory management circuit 51 can also replace the second type of entity unit in the entity unit V(3) (i.e., the sub-entity unit B(3) in the entity plane P1) with the third type of entity unit, and use the replaced sub-entity unit B(3) in the entity plane P1 as a spare entity unit to complete the target operation.

[0089] On the other hand, in step S708, the memory management circuit 51 may replace the fourth type of physical unit with a spare physical unit based on the physical unit bitmap 91. Fig. 9As shown, the memory management circuit 51 can replace the sub-entity unit B(1) in the physical plane P0 with the sub-entity unit B(3) in the physical plane P0. In another embodiment, the memory management circuit 51 can also replace the sub-entity unit B(1) in the physical plane P0 with the sub-entity unit B(3) in the physical plane P1. Accordingly, the storage space of the memory storage device 10 can be increased.

[0090] Accordingly, in step S709, the memory management circuit 51 may update the physical unit bitmap 91. Specifically, the memory management circuit 51 may update the physical unit bitmap 91 according to the above-mentioned operation of replacing the first type of physical unit or the second type of physical unit (please refer to step S707) and / or the operation of replacing the fourth type of physical unit.

[0091] Finally, in step S710, the memory management circuit 51 may set a first read count threshold and a second read count threshold for the first type of physical cell and the second type of physical cell respectively based on the physical cell bitmap 91. Fig. 9 A first read count threshold is set for the first type of physical units B(0), B(1) of the physical plane P0 and the first type of physical units B(0), B(1) of the physical plane P1, and a second read count threshold is set for the second type of physical units B(3), B(N) of the physical plane P1. Specifically, the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of physical units. The first read count threshold may be, for example, equal to or not equal to the second read count threshold, and the present invention is not limited thereto. In this way, the frequency of performing read verification operations on the first type of physical units and the second type of physical units can be increased to maintain the performance of the memory storage device 10.

[0092] According to the above, the memory management method of the present invention can put only one sub-entity unit in which an error occurs in the read detection operation into the subsequent data access operation, so as to increase the storage space of the rewritable non-volatile memory module 43, thereby improving the service life of the memory storage device 10. In addition, the memory management method of the present invention can also set a lower read count threshold for the first type of entity unit and the second type of entity unit to increase the frequency of performing the read verification operation on the first type of entity unit and the second type of entity unit, so as to strengthen the protection for the first type of entity unit and the second type of entity unit, thereby maintaining the performance of the memory storage device 10.

[0093] In completion Figure 7 After the memory management method associated with the self-test operation is executed, Fig.10 A memory management method associated with a write operation and a read-verify operation is shown. Fig.10is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig.10 .

[0094] In step S1001 , the memory management circuit 51 may receive a write command from the host system 11 . Specifically, when data is to be written to the memory access device 10 , the user may send a write command to the memory storage device 10 via the host system 11 .

[0095] In step S1002, the memory management circuit 51 may select a target write physical unit corresponding to the write mode of the write command based on the physical unit bitmap 91, and write the write data corresponding to the write command into the target write physical unit. In an exemplary embodiment, the memory management circuit 51 may select one or more target write physical units corresponding to the write mode of the write command from the idle area 602 based on the physical unit bitmap 91 after receiving the write command.

[0096] In an exemplary embodiment, the write mode may be, for example, an operating mode in which the memory storage device 10 can operate, such as a single-level cell (SLC) mode, a second-level cell (MLC) mode, a third-level cell (TLC) mode, or a fourth-level cell (QLC) mode. Therefore, the target write physical cell may be, for example, a first-type physical cell that can be successfully accessed in the SLC mode or a second-type physical cell that can be successfully accessed in the MLC mode (or TLC mode, QLC mode).

[0097] For example, assuming that the write mode corresponding to the write instruction is the SLC mode, the memory management circuit 51 may select a target write physical cell corresponding to the SLC mode from the idle area 602 based on the physical cell bitmap 91. In an exemplary embodiment, the first type of physical cell of the physical cell bitmap 91 may be successfully accessed in the SLC mode, and the second type of physical cell may be successfully accessed in the TLC mode. The memory management circuit 51 may select the sub-physical cell B(0) of the physical plane P0 as the target write physical cell based on the physical cell bitmap 91, and write the write data corresponding to the write instruction into the target write physical cell based on the SLC mode.

[0098] In step S1003, the memory management circuit 51 may perform a read verification operation on the target write physical unit after the target write physical unit is full. Specifically, since the target write physical unit can only be successfully accessed in a single operation mode, the probability of error in the target write physical unit may be higher than that of the third type of physical unit. Therefore, after the target write physical unit is full, the memory management circuit 51 may perform a read verification operation on the target write physical unit to ensure that the data stored in the target write physical unit is correct, thereby maintaining the performance of the memory storage device 10.

[0099] In this way, the memory management method of the present invention can complete the write operation by managing the physical unit bitmap 91 to adopt a suitable target write physical unit, and after the target write physical unit is full, perform a read verification operation on the target write physical unit, thereby increasing the storage space of the memory storage device 10 while maintaining the performance of the memory storage device 10.

[0100] The memory management method of the present invention further improves the read verification operation of the memory storage device 10. Generally speaking, the conventional read verification operation is that the memory storage device 10 obtains the read count of each used physical unit with stored data at irregular intervals, and performs a read verification operation on the used physical units with a read count greater than a read count threshold, so as to ensure the correctness of the data stored in the rewritable non-volatile memory module 43.

[0101] On this basis, the memory management method of the present invention has made the following improvements: (1.) As mentioned above, a lower read count threshold is set for the first type physical unit and the second type physical unit; (2.) In the idle state, the read verification operation is directly performed on the first type physical unit and the second type physical unit. The specific implementation details are as follows: Fig.11 shown. Fig.11 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig.11 .

[0102] In step S1101, the memory management circuit 51 can determine whether the memory storage device 10 is in an idle state. If so, the process proceeds to step S1105; if not (ie, the memory storage device 10 is in an operating state), the process proceeds to step S1102.

[0103] In step S1102, the memory management circuit 51 may periodically obtain the number of reads of the sub-physical units storing data. In an exemplary embodiment, the memory management circuit 51 may periodically obtain the number of reads of the sub-physical units storing data from the rewritable non-volatile memory module 43, wherein the sub-physical units storing data may be, for example, one or more, and each sub-physical unit storing data may be, for example, a first-type physical unit, a second-type physical unit, or a third-type physical unit.

[0104] In step S1103, the memory management circuit 51 can determine whether the number of reads of the sub-entity unit with stored data is greater than the read number threshold. In an exemplary embodiment, each sub-entity unit in the rewritable non-volatile memory module 43 may, for example, have a read number threshold. For example, if the sub-entity unit with stored data is a third-type entity unit, the memory management circuit 51 can determine whether the number of reads of this third-type entity unit is greater than its read number threshold. If so, enter step S1104; if not, do not perform the read verification operation on this third-type entity unit for the time being, that is, end the read verification operation for this third-type entity unit. Fig.11 Memory management method.

[0105] In addition, it should be noted that, as mentioned above, after completing Figure 7 After the memory management method associated with the self-test operation is implemented, the memory management circuit 51 can set a first read count threshold and a second read count threshold for the first type of physical unit and the second type of physical unit, respectively, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of physical unit.

[0106] Therefore, in an exemplary embodiment, if the sub-physical unit storing data is a first-type physical unit, the memory management circuit 51 can use a lower read count threshold (i.e., the first read count threshold) as a basis for judging whether the read count of the first-type physical unit is greater than the first read count threshold. If so, the process proceeds to step S1104; if not, the read verification operation is not performed on the first-type physical unit.

[0107] Similarly, if the sub-entity unit storing data is a second-type entity unit, the memory management circuit 51 may also use a lower read count threshold (i.e., the second read count threshold) as a basis for judging whether the read count of the second-type entity unit is greater than the second read count threshold. If so, the process proceeds to step S1104; if not, the read verification operation is not performed on the second-type entity unit.

[0108] Next, in step S1104, the memory management circuit 51 may perform a read verification operation. Specifically, the memory management circuit 51 may perform a read verification operation on the sub-entity units with stored data whose read times are greater than the read times threshold to confirm whether the data stored therein is correct, so as to ensure the correctness of the data stored in the rewritable non-volatile memory module 43.

[0109] On the other hand, when the memory storage device 10 is in an idle state, in step S1105 , the memory management circuit 51 may perform a read verification operation on the first type of physical cells storing data and the second type of physical cells storing data based on the physical cell bitmap 91 .

[0110] Specifically, in an idle state, the memory management circuit 51 can query the first type of physical units and the second type of physical units in the rewritable non-volatile memory module 43 based on the physical unit bit map 91, and perform a read verification operation on the first type of physical units storing data and / or the second type of physical units storing data in the rewritable non-volatile memory module 43 to confirm the correctness of the data stored therein.

[0111] According to the above, since the first-class physical units and the second-class physical units can only be successfully accessed in a single operation mode, the probability of errors in the first-class physical units and the second-class physical units may be higher than that in the third-class physical units. Therefore, the memory management method of the present invention can improve the protection of the data stored in the first-class physical units and the second-class physical units by (1.) setting a lower read count threshold for the first-class physical units and the second-class physical units; and (2.) performing a read verification operation directly on the first-class physical units with stored data and the second-class physical units with stored data in an idle state, so as to ensure the correctness of the data stored in the rewritable non-volatile memory module 43.

[0112] Fig.12 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig.12 . In step S1201, a detection operation is performed on multiple entity units V(0)~V(N) to obtain multiple detection results corresponding to the multiple entity units V(0)~V(N) respectively. In step S1202, a entity unit bitmap 91 is generated from the multiple detection results. In step S1203, a target entity unit is selected from the multiple entity units V(0)~V(N) according to the entity unit bitmap 91 and a preset condition, wherein the preset condition is used to characterize that the target entity unit includes a first type of entity unit and a second type of entity unit. In step S1204, a target operation is performed to replace the first type of entity unit or the second type of entity unit, and the replaced first type of entity unit or the replaced second type of entity unit is used as a spare entity unit. In step S1205, the entity unit bitmap is updated.

[0113] However, Fig.12 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.12 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.12 The method can be used in combination with the above embodiments or can be used alone, and the present invention is not limited thereto.

[0114] In summary, the memory management method and memory storage device proposed in the exemplary embodiments of the present invention can fully utilize the storage space of the rewritable non-volatile memory module while maintaining the correctness of the data stored in the rewritable non-volatile memory module, thereby effectively improving the service life and performance of the memory storage device.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity units, wherein each of the plurality of entity units comprises a plurality of sub-entity units, and the memory management method comprises: Performing a detection operation on the plurality of entity units to obtain a plurality of detection results respectively corresponding to the plurality of entity units; generating a physical unit bitmap based on the plurality of detection results; Selecting a target entity unit from the plurality of entity units according to the entity unit bitmap and a preset condition, wherein the preset condition is used to indicate that the target entity unit includes a first type of entity unit and a second type of entity unit; performing a target operation to replace the first-type entity unit or the second-type entity unit, and using the replaced first-type entity unit or the replaced second-type entity unit as a spare entity unit; and The entity unit bitmap is updated.

2. The method according to claim 1, wherein: The detection operation includes a first detection operation and a second detection operation, wherein the detection result corresponding to the first type of entity unit is used to characterize that the first detection operation is successful and the second detection operation is a failure, and the detection result corresponding to the second type of entity unit is used to characterize that the second detection operation is successful and the first detection operation is a failure.

3. The memory management method according to claim 2, wherein: The detection result corresponding to the third type of entity unit is used to indicate that the first detection operation and the second detection operation are both successful, and the detection result corresponding to the fourth type of entity unit is used to indicate that the first detection operation and the second detection operation are both failed.

4. The memory management method according to claim 2, wherein: The first detection operation is a single-level memory cell read detection operation, and the second detection operation is a triple-level memory cell read detection operation.

5. The method according to claim 1, wherein the step of generating the entity unit bitmap based on the plurality of detection results comprises: Classifying each of the plurality of sub-entity units in the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein the classification result includes the first type of entity units, the second type of entity units, the third type of entity units, and the fourth type of entity units; and The entity unit bitmap is generated according to the classification result, wherein the entity unit bitmap is used to reflect that the multiple sub-entity units among the multiple entity units are respectively the first type of entity units, the second type of entity units, the third type of entity units or the fourth type of entity units.

6. The memory management method according to claim 5, wherein the step of executing the target operation to replace the first type entity unit or the second type entity unit comprises: The first type of entity elements or the second type of entity elements in the target entity elements are replaced with the third type of entity elements.

7. The memory management method according to claim 5, further comprising: Based on the entity unit bitmap, the fourth type of entity unit is replaced by the spare entity unit.

8. The memory management method according to claim 1, further comprising: Based on the entity unit bitmap, selecting a target write entity unit corresponding to the write mode of the write instruction, and writing the write data corresponding to the write instruction into the target write entity unit, wherein the target write entity unit is the first type entity unit or the second type entity unit; and After the target writing entity unit is fully written, a read verification operation is performed on the target writing entity unit.

9. The memory management method according to claim 1, further comprising: Based on the entity unit bitmap, a first read count threshold and a second read count threshold are set for the first type of entity units and the second type of entity units, respectively. The first reading number threshold and the second reading number threshold are both lower than the reading number threshold of the third type of physical unit.

10. The memory management method according to claim 1, further comprising: In an idle state, based on the physical cell bitmap, a read verification operation is performed on the first-type physical cells storing data and the second-type physical cells storing data.

11. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein each of the plurality of physical units comprises a plurality of sub-physical units; and A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Performing a detection operation on the plurality of entity units to obtain a plurality of detection results respectively corresponding to the plurality of entity units, generating a solid unit bitmap based on the plurality of detection results, A target entity unit is selected from the plurality of entity units according to the entity unit bitmap and a preset condition, wherein the preset condition is used to indicate that the target entity unit includes a first type entity unit and a second type entity unit, performing a target operation to replace the first-type entity unit or the second-type entity unit, and using the replaced first-type entity unit or the replaced second-type entity unit as a spare entity unit, and The entity unit bitmap is updated.

12. The memory storage device according to claim 11, wherein: The detection operation includes a first detection operation and a second detection operation, wherein the detection result corresponding to the first type of entity unit is used to characterize that the first detection operation is successful and the second detection operation is a failure, and the detection result corresponding to the second type of entity unit is used to characterize that the second detection operation is successful and the first detection operation is a failure.

13. The memory storage device of claim 12, wherein: The detection result corresponding to the third type of entity unit is used to indicate that the first detection operation and the second detection operation are both successful, and the detection result corresponding to the fourth type of entity unit is used to indicate that the first detection operation and the second detection operation are both failed.

14. The memory storage device of claim 12, wherein: The first detection operation is a single-level memory cell read detection operation, and the second detection operation is a triple-level memory cell read detection operation.

15. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to classify each of the plurality of sub-entity units in the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein: The classification result includes the first type of entity unit, the second type of entity unit, the third type of entity unit and the fourth type of entity unit, and The memory control circuit unit is also used to generate the entity unit bitmap according to the classification result, wherein the entity unit bitmap is used to reflect that the multiple sub-entity units among the multiple entity units are respectively the first type of entity units, the second type of entity units, the third type of entity units or the fourth type of entity units. 16 . The memory storage device according to claim 15 , wherein the memory control circuit unit is further configured to replace the first-type physical unit or the second-type physical unit in the target physical unit with the third-type physical unit. 17 . The memory storage device according to claim 15 , wherein the memory control circuit unit is further configured to replace the fourth type physical unit with the spare physical unit based on the physical unit bitmap.

18. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to select a target write physical unit corresponding to a write mode of a write instruction based on the physical unit bitmap, and write the write data corresponding to the write instruction into the target write physical unit, wherein: The target writing entity unit is the first type entity unit or the second type entity unit, and The memory control circuit unit is further configured to perform a read verification operation on the target writing physical unit after the target writing physical unit is fully written.

19. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to set a first read count threshold and a second read count threshold for the first type of physical unit and the second type of physical unit, respectively, based on the physical unit bitmap, wherein: The first reading number threshold and the second reading number threshold are both lower than the reading number threshold of the third type of physical unit.

20. The memory storage device of claim 11, wherein: In an idle state, the memory control circuit unit is further configured to perform a read verification operation on the first type of physical cells storing data and the second type of physical cells storing data based on the physical cell bitmap.

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