Instruction execution method and device and storage medium

Abstract

The invention provides an instruction execution method and device and a storage medium, and the method comprises the steps: receiving an SFU instruction, and determining all processing units with the processing precision greater than or equal to the target precision from an SFU module based on the target precision corresponding to the SFU instruction, and taking the processing units as all target processing units; based on the data processing efficiency of each target processing unit, dividing target data corresponding to the SFU instruction into to-be-processed sub-data of each target processing unit, so that the maximum value of time consumed by each target processing unit to process the sub-data is lower than the time consumed by the processing unit with the processing precision as the target precision to process the target data; and controlling each target processing unit to process the sub-data respectively. According to the method, the device and the storage medium provided by the invention, computing resources in the SFU module are fully utilized, the sub-data are allocated to each target processing unit to realize parallel processing of the sub-data, and the execution efficiency of the SFU instruction is improved.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence chip technology, and in particular to an instruction execution method, device and storage medium. Background Art

[0002] In the design of artificial intelligence chips, the Special Function Unit (SFU) is the core component for performing various mathematical operations (such as reciprocal, square root, trigonometric functions, etc.). Its performance optimization is directly related to the computing efficiency and energy consumption of the entire chip.

[0003] In order to cope with computing tasks with different precision requirements, artificial intelligence chips usually integrate processing units of different precision in the SFU module, so that SFU instructions with different precision requirements can be assigned to processing units of corresponding precision for execution.

[0004] Although this processing method can meet the processing requirements of different precision scenarios, during the execution of SFU instructions for a single precision, the processing units of other precisions are all idle, and the computing resources of the SFU module are not fully utilized, which affects the execution efficiency of the SFU instructions. Summary of the invention

[0005] The present invention provides an instruction execution method, device and storage medium, which are used to solve the defect of low execution efficiency of SFU instructions in related technologies.

[0006] The present invention provides an instruction execution method, comprising the following steps.

[0007] Receive a special function unit SFU instruction, and based on the target precision corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing precision is greater than or equal to the target precision as each target processing unit; Based on the data processing efficiency of each target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; Control each target processing unit to process the sub-data respectively.

[0008] According to an instruction execution method provided by the present invention, each target processing unit includes a first target processing unit having a processing accuracy equal to the target accuracy, and a second target processing unit having a processing accuracy greater than the target accuracy; The controlling each target processing unit to process the sub-data respectively comprises: controlling each first target processing unit to process the sub-data respectively, and,

[0009] The second target processing units are controlled to truncate the sub-data and process the truncated sub-data respectively.

[0010] According to an instruction execution method provided by the present invention, the bit length of the truncated sub-data is the data bit length corresponding to the target precision.

[0011] According to an instruction execution method provided by the present invention, the difference between the first time consumption and the second time consumption is less than or equal to a preset threshold; The first time consumption is the maximum value of the time consumption of each first target processing unit to process the sub-data respectively, and the second time consumption is the maximum value of the time consumption of each second target processing unit to truncate and process the sub-data respectively.

[0012] According to an instruction execution method provided by the present invention, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit based on the data processing efficiency of each target processing unit, including: Based on the data processing efficiency of each first target processing unit, and the data truncation efficiency and data processing efficiency of each second target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit.

[0013] According to an instruction execution method provided by the present invention, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit based on the data processing efficiency of each first target processing unit and the data truncation efficiency and data processing efficiency of each second target processing unit, including: Based on the data volume constraint and the time consumption constraint, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit; The data volume constraint is that the sum of the data volumes of the sub-data to be processed by each target processing unit is equal to the data volume of the target data, and the time consumption constraint is that the time consumption of each target processing unit for processing the sub-data of the sub-data is lower than the time consumption of a processing unit with the processing accuracy of the target accuracy for processing the target data; The sub-data time consumption of the first target processing unit is determined based on the data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the first target processing unit, and the sub-data time consumption of the second target processing unit is determined based on the data truncation efficiency, data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the second target processing unit.

[0014] According to an instruction execution method provided by the present invention, each processing unit includes a fast processing unit and a high-precision processing unit; Based on the target accuracy corresponding to the SFU instruction, determining from the SFU module each processing unit whose processing accuracy is greater than or equal to the target accuracy as each target processing unit, includes: When the target precision corresponding to the SFU instruction is the fast processing precision, the fast processing unit and the high-precision processing unit are used as the target processing units.

[0015] According to an instruction execution method provided by the present invention, based on the target accuracy corresponding to the SFU instruction, each processing unit having a processing accuracy greater than or equal to the target accuracy is determined from the SFU module as each target processing unit, and further includes: When the target precision corresponding to the SFU instruction is high precision, the high precision processing unit is used as the target processing unit.

[0016] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any one of the instruction execution methods described above is implemented.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the instruction execution method described in any one of the above is implemented.

[0018] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned instruction execution methods.

[0019] The instruction execution method, device and storage medium provided by the present invention take each processing unit with a processing accuracy greater than or equal to the target accuracy as each target processing unit, and divide the target data of the SFU instruction into sub-data based on the data processing efficiency of each target processing unit and distribute them to each target processing unit, control each target processing unit to process the sub-data to realize the execution of the SFU instruction, wherein each processing unit with a processing accuracy greater than or equal to the target accuracy is taken as each target processing unit, so that the computing resources in the SFU module can be fully utilized, and on this basis, sub-data are allocated to each target processing unit to realize parallel processing of the sub-data, so that the execution efficiency of the SFU instruction can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a structural diagram of an SFU module in the related art.

[0022] Figure 2 It is a flowchart of the instruction execution method provided by the present invention.

[0023] Figure 3 It is a structural schematic diagram of the instruction execution device provided by the present invention.

[0024] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] With the rapid development of artificial intelligence technology, the demand for computing performance is growing, especially in the fields of deep learning, image processing, natural language processing, etc., efficient mathematical computing capabilities have become a key factor in promoting technological progress. In the design of artificial intelligence chips, the special function unit SFU is the core component for performing various mathematical operations (such as reciprocal, square root, trigonometric functions, etc.), and its performance optimization is directly related to the computing efficiency and energy consumption of the entire chip.

[0027] In order to cope with computing tasks with different precision requirements, artificial intelligence chips usually integrate processing units of different precision in the SFU module, so that SFU instructions with different precision requirements are assigned to processing units of corresponding precision for execution.

[0028] For example, Figure 1 It is a structural diagram of the SFU module in the related technology, such as Figure 1 As shown in the figure, in some artificial intelligence chips, two types of processing units with different precisions can be integrated in the SFU module, namely, high-precision processing units and fast processing units. Among them, the high-precision processing unit has low efficiency but high calculation result precision, while the fast processing unit has high efficiency but low calculation result precision. When executing high-precision SFU instructions, the high-precision processing unit in the SFU module can be used for calculation; when executing fast SFU (Fast SFU) instructions, the fast processing unit can be used for calculation.

[0029] Although the above processing method can meet the processing requirements of different precision scenarios, during the execution of the SFU instruction for a single precision, the processing units of the other precisions are all idle. For example, the fast SFU instruction is only executed on the fast processing unit, and the high-precision processing unit is idle at this time. The computing resources of the SFU module are not fully utilized, which affects the execution efficiency of the SFU instruction.

[0030] In view of the above problems, an embodiment of the present invention provides an instruction execution method. The method can be applied to artificial intelligence chips, where the artificial intelligence chips can be GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit), which is not specifically limited in the embodiment of the present invention.

[0031] Figure 2 is a flow chart of the instruction execution method provided by the present invention, such as Figure 2 As shown, the method includes: Step 210, receiving a special function unit SFU instruction, and based on the target accuracy corresponding to the SFU instruction, determining from the SFU module each processing unit whose processing accuracy is greater than or equal to the target accuracy as each target processing unit.

[0032] Here, the SFU instruction is the instruction to be executed, which can be sent by the host to the device. Among them, the device can be an artificial intelligence chip, and a device can include at least one SFU module, and the SFU module can be used to execute the SFU instruction. The host can be a central processing unit or computer connected to the device, such as a CPU (Central Processing Unit), a microprocessor, etc., and both the host and the device can receive, process and respond to information and requests from each other. Furthermore, the host can send the SFU instruction to the artificial intelligence chip as a device, and accordingly, the artificial intelligence chip can receive the SFU instruction to be executed. Specifically, the artificial intelligence chip reads the SFU instruction at the host, and then the module on the artificial intelligence chip decodes the read SFU instruction, and sends the decoded SFU instruction to the SFU module for execution.

[0033] It is understandable that the SFU instruction carries the processing accuracy requirement for executing the instruction, that is, the target accuracy, which is one of the multiple processing accuracy options available to the SFU module. For example, when there are two types of processing units with different accuracy, namely, high-precision processing units and fast processing units, in the SFU module, the target accuracy corresponding to the SFU instruction can be any one of the two types of different accuracy.

[0034] After determining the target precision corresponding to the SFU instruction, the processing unit with a processing precision greater than or equal to the target precision can be selected from the processing units with various processing precisions contained in the SFU module as the target processing unit. The target processing unit obtained here is the processing unit used to execute the SFU instruction. It can be understood that, unlike the related art that only selects the processing unit with a processing precision equal to the target precision as the target processing unit, in the embodiment of the present invention, with respect to the determination of the target processing unit, not only the processing unit with a processing precision equal to the target precision is selected as the target processing unit, but also the processing unit with a processing precision greater than the target precision is selected as the target processing unit. In this way, in the method provided in the embodiment of the present invention, the number of target processing units used to execute the SFU instruction obviously exceeds the number of target processing units used to execute the SFU instruction in the related art, so that when executing the SFU instruction, the computing resources of the SFU module can be fully utilized.

[0035] Step 220, based on the data processing efficiency of each target processing unit, divide the target data corresponding to the SFU instruction into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data respectively is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data.

[0036] Step 230, controlling each target processing unit to process the sub-data respectively.

[0037] Specifically, after determining the target processing unit for executing the SFU instruction, the data to be processed corresponding to the SFU instruction can be allocated to each target processing unit. The data to be processed here is specified by the SFU instruction, and can be obtained from the memory of the artificial intelligence chip, or can be read from an external memory, which is not specifically limited in the embodiment of the present invention.

[0038] In an embodiment of the present invention, the data to be processed corresponding to the SFU instruction is recorded as target data, and based on the data processing efficiency of each target processing unit, the target data is divided into multiple sub-data and distributed to each target processing unit, thereby obtaining the sub-data to be processed of each target processing unit.

[0039] Here, the data processing efficiency of the target processing unit is the time consumed by the target processing unit to process one unit of data, or the amount of data that the target processing unit can process in one unit of time. For example, a fast processing unit needs N clock cycles to process one data, and a high-precision processing unit needs 2N clock cycles to process one data. It can be understood that, generally, the higher the processing precision of a processing unit, the lower the data processing efficiency of the processing unit.

[0040] Based on the data processing efficiency of each target processing unit, the target data is divided into sub-data and allocated to each target processing unit. The purpose is to allocate the sub-data so that when the allocated target processing units process the sub-data in parallel to implement the SFU instruction, the processing time of the target processing unit with the longest processing time is less than the total time for all processing units with the target processing accuracy to process the target data.

[0041] Among them, the processing time of the target processing unit with the longest processing time, that is, the maximum value of the time consumed by each target processing unit to process the sub-data respectively, that is, after determining the target processing unit based on step 210 and allocating the sub-data of the target data to each target processing unit in step 220, the overall time consumed by controlling each target processing unit to process the sub-data in parallel can be understood as the time consumed by the instruction execution method provided by the embodiment of the present invention to execute the SFU instruction. The total time consumed by all processing units with the processing accuracy of the target accuracy to process the target data is the time consumed by the instruction execution method provided by the relevant technology to execute the SFU instruction.

[0042] After the sub-data are allocated, each target processing unit can be controlled to process the allocated sub-data in parallel, thereby completing the execution of the SFU instruction.

[0043] By dividing the target data into sub-data and allocating them to each target processing unit based on the data processing efficiency of each target processing unit, and then controlling each target processing unit to process its allocated sub-data in parallel, it is possible to ensure that the time consumption of the SFU instruction executed thereby is lower than the time consumption of data processing by the processing unit whose processing accuracy is the target accuracy in the related technology, thereby ensuring that the execution efficiency of the SFU instruction is improved.

[0044] The method provided by the embodiment of the present invention takes each processing unit with a processing accuracy greater than or equal to the target accuracy as each target processing unit, and divides the target data of the SFU instruction into sub-data based on the data processing efficiency of each target processing unit and distributes them to each target processing unit, and controls each target processing unit to process the sub-data to realize the execution of the SFU instruction, wherein each processing unit with a processing accuracy greater than or equal to the target accuracy is taken as each target processing unit, so that the computing resources in the SFU module can be fully utilized, and on this basis, sub-data are allocated to each target processing unit to realize parallel processing of the sub-data, so that the execution efficiency of the SFU instruction can be improved.

[0045] Based on the above embodiment, each target processing unit includes a first target processing unit having a processing accuracy equal to the target accuracy, and a second target processing unit having a processing accuracy greater than the target accuracy.

[0046] Specifically, for the case where the target precision corresponding to the SFU instruction is less than the maximum precision that the SFU module can handle, that is, there is a processing unit in the SFU module whose precision is greater than the target precision, the target processing unit determined from the SFU module may include two parts, one part is a processing unit whose processing precision is equal to the target precision, recorded here as the first target processing unit, and the other part is a processing unit whose processing precision is greater than the target precision, recorded here as the second target processing unit.

[0047] It can be understood that, in the related art, the first target processing unit is used to execute the SFU instruction, while in the present application, the first target processing unit and the second target processing unit are used to execute the SFU instruction.

[0048] Accordingly, in step 230, controlling each target processing unit to process the sub-data respectively includes: controlling each first target processing unit to process the sub-data respectively, and,

[0049] The second target processing units are controlled to truncate the sub-data and process the truncated sub-data respectively.

[0050] Specifically, considering that the processing accuracy of the second target processing unit itself is higher than that of the first target processing unit, in order to ensure that the accuracy of the result obtained by processing the sub-data based on the first target processing unit is consistent with the accuracy of the result obtained by processing the sub-data based on the second target processing unit, the bit length of the sub-data actually processed at the first target processing unit needs to be consistent with the bit length of the sub-data actually processed at the second target processing unit.

[0051] Since the processing accuracy of the first target processing unit itself is the target accuracy, the first target processing unit can be directly controlled to process the sub-data. However, the processing accuracy of the second target processing unit itself is greater than the target accuracy, so it is necessary to first control the second target processing unit to perform a truncation operation on the sub-data so that the bit length of the truncated sub-data is consistent with the bit length of the sub-data actually processed by the first target processing unit, and then control the second target processing unit to process the truncated sub-data, thereby ensuring that the accuracy of the results obtained by the processing units with different accuracies are consistent.

[0052] Based on any of the above embodiments, the bit length of the truncated sub-data is the data bit length corresponding to the target accuracy.

[0053] Specifically, different precisions correspond to different data bit lengths. It is understandable that the higher the precision, the longer the corresponding data bit length, and correspondingly, the lower the precision, the shorter the corresponding data bit length.

[0054] For the second target processing unit having a higher processing accuracy relative to the target accuracy, in order to make the accuracy of the result obtained by the second target processing unit for processing the sub-data consistent with the target accuracy, that is, consistent with the accuracy of the result obtained by the first target processing unit for processing the sub-data, before controlling the second target processing unit to process the sub-data, the sub-data can be truncated, and after the sub-data is truncated, the bit length of the truncated sub-data is equal to the data bit length corresponding to the target accuracy, that is, the bit length of the truncated sub-data is equal to the bit length of the sub-data actually processed by the first target processing unit.

[0055] The method provided by the embodiment of the present invention controls the precision of the results obtained by sub-data processed by target processing units with different processing precisions to be the target precision through truncation operation, thereby ensuring the reliability of SFU instruction execution.

[0056] Based on any of the above embodiments, the difference between the first time consumption and the second time consumption is less than or equal to a preset threshold; The first time consumption is the maximum value of the time consumption of each first target processing unit to process the sub-data respectively, and the second time consumption is the maximum value of the time consumption of each second target processing unit to truncate and process the sub-data respectively.

[0057] Specifically, in the process of controlling the first target processing unit to process the sub-data respectively, the maximum time consumed by all the first target processing units to process the sub-data respectively is recorded as the first time consumption. In the process of controlling the second target processing unit to truncate the sub-data first and then process the truncated sub-data, the maximum time consumed by the second target processing unit to truncate the sub-data respectively and process the truncated sub-data is recorded as the second time consumption.

[0058] It can be understood that the first time consumption and the second time consumption are respectively for the first target processing unit and the second target processing unit, and the first time consumption is the time consumption of the first target processing unit to process the sub-data, and the second time consumption is the time consumption of the second target processing unit to truncate and process the sub-data.

[0059] When the first target processing unit and the second target processing unit are executed in parallel, the execution time of the SFU instruction is the maximum value of the first time consumption and the second time consumption.

[0060] In order to minimize the processing time of the SFU instruction, the first time consumption and the second time consumption can be estimated when the target data is divided into sub-data to be processed by each target processing unit, and the difference between the first time consumption and the second time consumption can be constrained to be less than or equal to a preset threshold, where the preset threshold is a pre-set time difference threshold.

[0061] The difference between the first time consumption and the second time consumption is constrained to be less than or equal to a preset threshold value, so that the first time consumption and the second time consumption are as close as possible, thereby making the difference between the first time consumption and the second time consumption as small as possible, that is, after the sub-data processing of one type of target processing unit is completed, the time waiting for the sub-data processing of another type of target processing unit to be completed is as short as possible, thereby making the idle state of the target processing unit as small as possible during the execution of the SFU instruction, thereby ensuring that the computing resources of the SFU module during the execution of the SFU instruction are fully utilized, thereby improving the execution efficiency of the SFU instruction.

[0062] Based on any of the above embodiments, in step 220, dividing the target data corresponding to the SFU instruction into sub-data to be processed by each target processing unit based on the data processing efficiency of each target processing unit includes: Based on the data processing efficiency of each first target processing unit, and the data truncation efficiency and data processing efficiency of each second target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit.

[0063] Specifically, in order to ensure that the accuracy of the result obtained by processing the sub-data based on the first target processing unit is consistent with the accuracy of the result obtained by processing the sub-data based on the second target processing unit, before the second target processing unit processes the assigned sub-data, it is also necessary to control the second target processing unit to perform a truncation operation on the assigned sub-data, so that the bit length of the sub-data actually processed by the second target processing unit can be consistent with the bit length of the sub-data processed by the first target unit.

[0064] Since the second target processing unit not only needs to process the sub-data, but also needs to truncate the sub-data before that, and the truncation operation itself will consume time. Therefore, when dividing and allocating the sub-data for the target data corresponding to the SFU instruction, it is necessary to refer not only to the data processing efficiency of the first target processing unit and the second target processing unit, but also to the data truncation efficiency of the second target processing unit.

[0065] Here, the data truncation efficiency of the second target processing unit refers to the time consumed by the second target processing unit to perform a truncation operation on one unit of data, or the amount of data that can be truncated by the second target processing unit within one unit of time.

[0066] Therefore, based on the data processing efficiency of each first target processing unit, as well as the data truncation efficiency and data processing efficiency of each second target processing unit, the target data can be divided into sub-data and allocated to each target processing unit. The purpose is to allocate sub-data so that when each allocated target processing unit processes each sub-data in parallel to implement the SFU instruction, the processing time of the target processing unit with the longest processing time is less than the total time taken by all the first target processing units to process the target data.

[0067] Furthermore, the target data is divided into sub-data and allocated to each target processing unit. Its purpose can also be to allocate the sub-data so that when the allocated target processing units process the sub-data in parallel to implement the SFU instruction, the processing time of the target processing unit that takes the longest time is minimized, that is, the execution time of the SFU instruction is minimized.

[0068] Based on any of the above embodiments, in step 220, the target data corresponding to the SFU instruction is divided into sub-data to be processed of each target processing unit based on the data processing efficiency of each first target processing unit, and the data truncation efficiency and data processing efficiency of each second target processing unit, including: Based on the data volume constraint and the time consumption constraint, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit; The data volume constraint is that the sum of the data volumes of the sub-data to be processed by each target processing unit is equal to the data volume of the target data, and the time consumption constraint is that the time consumption of each target processing unit for processing the sub-data of the sub-data is lower than the time consumption of a processing unit with the processing accuracy of the target accuracy for processing the target data; The sub-data time consumption of the first target processing unit is determined based on the data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the first target processing unit, and the sub-data time consumption of the second target processing unit is determined based on the data truncation efficiency, data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the second target processing unit.

[0069] Specifically, the target data can be divided under the dual constraints of data volume constraint and time consumption constraint. Specifically, the data volume of the sub-data allocated to each target processing unit can be calculated under the data volume constraint and time consumption constraint, and then the target data can be divided based on the calculated data volume.

[0070] Here, the data volume constraint means that the sum of the data volumes of the sub-data to be processed by each target processing unit is equal to the data volume of the target data. Based on the data volume constraint, it can be ensured that all the data in the target data can be allocated to the target processing unit for processing. Assume that the data volume of the target data is K, the number of target processing units is M, and the data volume of the sub-data to be processed by each target processing unit is , then the data volume constraint can be expressed as:

[0071] The time consumption constraint refers to the time consumption of each target processing unit for processing the sub-data, that is, the sub-data time consumption, which is lower than the time consumption of the processing unit with the processing accuracy of the target accuracy for processing the target data. Based on the time consumption constraint, it can be ensured that the time consumption of dividing the target data into each target processing unit for processing is lower than the processing time consumption of the solution provided by the related technology. Assume that the sub-data time consumption of each processing unit is , then the time consumption constraint can be expressed as:

[0072] in, It indicates the time taken by the processing unit with target accuracy to process all target data. The data processing efficiency of the processing unit with the target accuracy, that is, the number of clock cycles required to process a batch of data; The amount of parallel processing data of the processing unit of the target accuracy, that is, the amount of data that can be processed simultaneously. Rounds up for integer division.

[0073] Here, since the first target processing unit only needs to perform data processing operations when processing sub-data, while the second target processing unit not only needs to perform data processing operations but also needs to perform truncation operations when processing sub-data, the calculation method of the sub-data time consumption of the first target processing unit is different from the calculation method of the sub-data time consumption of the second target processing unit.

[0074] For the case where the i-th processing unit is the first target processing unit, the sub-data time consumption The calculation can be expressed as the following formula:

[0075] In the formula, and are the data processing efficiency and the amount of sub-data of the i-th processing unit, respectively. is the amount of parallel processing data of the i-th processing unit, that is, the amount of data that can be processed simultaneously.

[0076] For the case where the i-th processing unit is the second target processing unit, the sub-data time consumption The calculation can be expressed as the following formula:

[0077] In the formula, and are the data processing efficiency and the amount of sub-data of the i-th processing unit, respectively. is the amount of parallel processing data of the i-th processing unit, that is, the amount of data that can be processed simultaneously. is the data truncation efficiency of the i-th processing unit, that is, the number of clock cycles required to truncate a batch of data.

[0078] Based on the data volume constraints and time consumption constraints, at least one set of The value of can be based on a set of The value of is used to allocate the sub-data to be processed to each target processing unit.

[0079] Based on any of the above embodiments, each processing unit includes a fast processing unit and a high-precision processing unit.

[0080] Specifically, see Figure 1 The structure of the SFU module shown in the figure, the SFU module can include two types of processing units, namely, a fast processing unit and a high-precision processing unit. Among them, the high-precision processing unit has low efficiency but high calculation result accuracy, and the fast processing unit has high efficiency but low calculation result accuracy. That is, in the SFU module, the high-precision processing unit is a processing unit with higher processing accuracy than the fast processing unit.

[0081] Accordingly, in step 210, based on the target accuracy corresponding to the SFU instruction, each processing unit having a processing accuracy greater than or equal to the target accuracy is determined from the SFU module as each target processing unit, including: When the target precision corresponding to the SFU instruction is the fast processing precision, the fast processing unit and the high-precision processing unit are used as the target processing units.

[0082] Specifically, when the target precision corresponding to the SFU instruction is the fast processing precision, that is, when the SFU instruction itself is a fast SFU instruction, in the SFU module, the fast processing unit is a processing unit whose processing precision is equal to the target precision, and the high-precision processing unit is a processing unit whose processing precision is greater than the target precision. Therefore, both the fast processing unit and the high-precision processing unit can be used as target processing units to execute the SFU instruction.

[0083] In this case, the fast processing unit can be regarded as the first target processing unit, and the high-precision processing unit can be regarded as the second target processing unit.

[0084] Assume that the target data corresponding to the SFU instruction is 16 data sent by the execution unit EU to the SFU module, and the fast processing unit and the high-precision processing unit can process 4 data at a time.

[0085] In the related art, only the fast processing unit is used as the target processing unit to execute the SFU instruction. The fast processing unit needs to divide the 16 data into 4 batches and process them successively. Assuming that the fast processing unit takes N clock cycles to process the data each time, a total of 4N clock cycles are required to complete the execution of the SFU instruction.

[0086] In the embodiment of the present invention, both the fast processing unit and the high-precision processing unit can perform data processing to execute the SFU instruction. Assume that the fast processing unit takes N clock cycles to process data each time, the high-precision processing unit takes 1 clock cycle to truncate data each time, and the time taken to process data each time is 2N clock cycles, that is, the time taken for the high-precision processing unit to truncate and process data each time is 2N+1 clock cycles. Referring to the 4 data that can be processed by the fast processing unit and the high-precision processing unit each time, the fast processing unit takes N clock cycles to process data each time, and the high-precision processing unit takes 2N+1 clock cycles to truncate and process data each time. The 16 data can be divided into two parts, one part has a total of 12 data, which are allocated to the fast processing unit for processing in three batches, with a total time of 3N clock cycles, and the other part has a total of 4 data, which are allocated to the high-precision processing unit for processing in one batch, with a total time of 2N+1 clock cycles. Since the fast processing unit and the high-precision processing unit can perform data processing in parallel, it takes 3N clock cycles to process 16 data to realize the execution of the SFU instruction. Compared with the 4N clock cycles in the related technology, the execution efficiency of the SFU instruction is improved by 33.3%.

[0087] Based on any of the above embodiments, in step 210, based on the target accuracy corresponding to the SFU instruction, determining from the SFU module each processing unit whose processing accuracy is greater than or equal to the target accuracy as each target processing unit, further includes: When the target precision corresponding to the SFU instruction is high precision, the high precision processing unit is used as the target processing unit.

[0088] Specifically, when the target precision corresponding to the SFU instruction is high precision, that is, when the SFU instruction is a high-precision SFU instruction, the fast processing unit is a processing unit whose processing precision is lower than the target precision, and the fast processing unit does not meet the processing precision required by the SFU instruction, and therefore cannot be used to execute the SFU instruction; the high-precision processing unit is a processing unit whose processing precision is equal to the target precision, and there is no processing unit in the SFU module whose processing precision is higher than that of the high-precision processing unit. Therefore, only the high-precision processing unit is used as the target processing unit to execute the SFU instruction.

[0089] The instruction execution device provided by the present invention is described below. The instruction execution device described below and the instruction execution method described above can be referenced to each other.

[0090] Figure 3 Schematic diagram of the structure of the instruction execution device provided by the present invention. Figure 3 As shown, the device comprises: The unit determination module 310 is used to receive a special function unit SFU instruction, and based on the target accuracy corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing accuracy is greater than or equal to the target accuracy as each target processing unit; The data allocation module 320 divides the target data corresponding to the SFU instruction into sub-data to be processed by each target processing unit based on the data processing efficiency of each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; The data processing module 330 is used to control each target processing unit to process the sub-data respectively.

[0091] The device provided by the embodiment of the present invention uses each processing unit with a processing accuracy greater than or equal to the target accuracy as each target processing unit, and divides the target data of the SFU instruction into sub-data based on the data processing efficiency of each target processing unit and distributes them to each target processing unit, and controls each target processing unit to process the sub-data to realize the execution of the SFU instruction, wherein each processing unit with a processing accuracy greater than or equal to the target accuracy is used as each target processing unit, so that the computing resources in the SFU module can be fully utilized, and on this basis, sub-data are allocated to each target processing unit to realize parallel processing of the sub-data, so that the execution efficiency of the SFU instruction can be improved.

[0092] Based on any of the above embodiments, each target processing unit includes a first target processing unit having a processing accuracy equal to the target accuracy, and a second target processing unit having a processing accuracy greater than the target accuracy; The data processing module is specifically used for: controlling each first target processing unit to process the sub-data respectively, and,

[0093] The second target processing units are controlled to truncate the sub-data and process the truncated sub-data respectively.

[0094] Based on any of the above embodiments, the bit length of the truncated sub-data is the data bit length corresponding to the target accuracy.

[0095] Based on any of the above embodiments, the difference between the first time consumption and the second time consumption is less than or equal to a preset threshold; The first time consumption is the maximum value of the time consumption of each first target processing unit to process the sub-data respectively, and the second time consumption is the maximum value of the time consumption of each second target processing unit to truncate and process the sub-data respectively.

[0096] Based on any of the above embodiments, the data allocation module is specifically used for: Based on the data processing efficiency of each first target processing unit, and the data truncation efficiency and data processing efficiency of each second target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit.

[0097] Based on any of the above embodiments, the data allocation module is specifically used for: Based on the data volume constraint and the time consumption constraint, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit; The data volume constraint is that the sum of the data volumes of the sub-data to be processed by each target processing unit is equal to the data volume of the target data, and the time consumption constraint is that the time consumption of each target processing unit for processing the sub-data of the sub-data is lower than the time consumption of a processing unit with the processing accuracy of the target accuracy for processing the target data; The sub-data time consumption of the first target processing unit is determined based on the data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the first target processing unit, and the sub-data time consumption of the second target processing unit is determined based on the data truncation efficiency, data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the second target processing unit.

[0098] Based on any of the above embodiments, each processing unit includes a fast processing unit and a high-precision processing unit; The unit determination module is specifically used for: When the target precision corresponding to the SFU instruction is the fast processing precision, the fast processing unit and the high-precision processing unit are used as the target processing units.

[0099] Based on any of the above embodiments, the unit determination module is further used for: When the target precision corresponding to the SFU instruction is high precision, the high precision processing unit is used as the target processing unit.

[0100] Figure 4 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 4 As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute the instruction execution method, which includes: Receive a special function unit SFU instruction, and based on the target precision corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing precision is greater than or equal to the target precision as each target processing unit; Based on the data processing efficiency of each target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; Control each target processing unit to process the sub-data respectively.

[0101] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0102] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program may be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer can execute the instruction execution method provided by the above methods, the method comprising: Receive a special function unit SFU instruction, and based on the target precision corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing precision is greater than or equal to the target precision as each target processing unit; Based on the data processing efficiency of each target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; Control each target processing unit to process the sub-data respectively.

[0103] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the instruction execution method provided by the above methods is implemented, and the method includes: Receive a special function unit SFU instruction, and based on the target precision corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing precision is greater than or equal to the target precision as each target processing unit; Based on the data processing efficiency of each target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; Control each target processing unit to process the sub-data respectively.

[0104] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for executing an instruction, characterized in that: include: Receive a special function unit SFU instruction, and based on the target precision corresponding to the SFU instruction, determine from the SFU module each processing unit whose processing precision is greater than or equal to the target precision as each target processing unit; Based on the data processing efficiency of each target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit, so that the maximum time consumed by each target processing unit to process the sub-data is lower than the time consumed by a processing unit with a processing accuracy of the target accuracy to process the target data; Control each target processing unit to process the sub-data respectively.

2. The instruction execution method according to claim 1, characterized in that: Each target processing unit includes a first target processing unit having a processing accuracy equal to the target accuracy, and a second target processing unit having a processing accuracy greater than the target accuracy; The controlling each target processing unit to process the sub-data respectively comprises: controlling each first target processing unit to process the sub-data respectively, and, The second target processing units are controlled to truncate the sub-data and process the truncated sub-data respectively.

3. The instruction execution method according to claim 2, characterized in that: The bit length of the truncated sub-data is the data bit length corresponding to the target accuracy.

4. The instruction execution method according to claim 2, characterized in that: The difference between the first time consumption and the second time consumption is less than or equal to a preset threshold; The first time consumption is the maximum value of the time consumption of each first target processing unit to process the sub-data respectively, and the second time consumption is the maximum value of the time consumption of each second target processing unit to truncate and process the sub-data respectively.

5. The instruction execution method according to claim 2, characterized in that: The method of dividing the target data corresponding to the SFU instruction into sub-data to be processed by each target processing unit based on the data processing efficiency of each target processing unit includes: Based on the data processing efficiency of each first target processing unit, and the data truncation efficiency and data processing efficiency of each second target processing unit, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit.

6. The instruction execution method according to claim 5, characterized in that: The method of dividing the target data corresponding to the SFU instruction into sub-data to be processed of each target processing unit based on the data processing efficiency of each first target processing unit and the data truncation efficiency and data processing efficiency of each second target processing unit includes: Based on the data volume constraint and the time consumption constraint, the target data corresponding to the SFU instruction is divided into sub-data to be processed by each target processing unit; The data volume constraint is that the sum of the data volumes of the sub-data to be processed by each target processing unit is equal to the data volume of the target data, and the time consumption constraint is that the time consumption of each target processing unit for processing the sub-data of the sub-data is lower than the time consumption of a processing unit with the processing accuracy of the target accuracy for processing the target data; The sub-data time consumption of the first target processing unit is determined based on the data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the first target processing unit, and the sub-data time consumption of the second target processing unit is determined based on the data truncation efficiency, data processing efficiency, the amount of parallel processing data and the amount of sub-data to be processed by the second target processing unit.

7. The instruction execution method according to any one of claims 1 to 6, characterized in that: Each processing unit includes a fast processing unit and a high-precision processing unit; Based on the target accuracy corresponding to the SFU instruction, determining from the SFU module each processing unit whose processing accuracy is greater than or equal to the target accuracy as each target processing unit, includes: When the target precision corresponding to the SFU instruction is the fast processing precision, the fast processing unit and the high-precision processing unit are used as the target processing units.

8. The instruction execution method according to claim 7, characterized in that: Based on the target accuracy corresponding to the SFU instruction, each processing unit having a processing accuracy greater than or equal to the target accuracy is determined from the SFU module as each target processing unit, and further includes: When the target precision corresponding to the SFU instruction is high precision, the high precision processing unit is used as the target processing unit.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the instruction execution method according to any one of claims 1 to 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the instruction execution method according to any one of claims 1 to 8 is implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the instruction execution method according to any one of claims 1 to 8 is implemented.

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