Equipment interconnection system, data processing method, device and equipment, medium and product

Abstract

The invention discloses a device interconnection system, a data processing method, device and equipment, a medium and a product, and relates to the technical field of data processing.The device interconnection system comprises a processor and a plurality of computing devices, the processor is connected with a processor memory, and the computing devices are connected with computing device memories. The processor is connected with the plurality of computing devices through a bus conforming to a preset protocol; the computing device comprises a target port, different computing devices are directly connected through the target port, and data are directly transmitted between different computing devices through the target port; a processor memory and a plurality of computing device memories are addressed in a unified addressing mode, and when the computing device memories are accessed, address mapping is carried out between the unified addressing and internal address spaces of the computing devices through the corresponding computing devices. The data transmission efficiency between different computing devices is improved, and the address access mode and the data transmission mode are simplified.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a device interconnection system, a data processing method, an apparatus and equipment, a medium and a product. Background Art

[0002] For the device interconnection system in the related technology, the processor and multiple computing devices are connected through a bus that complies with the preset protocol, such as PCIe (Peripheral Component Interconnect Express). Whether it is data transmission between the processor and the computing device, or data transmission between different computing devices, it must be carried out through the bus, resulting in greater transmission pressure on the bus and lower data transmission efficiency between different computing devices.

[0003] Therefore, how to improve the data transmission efficiency between different computing devices in a device interconnection system is a technical problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the present application is to provide a data processing method, apparatus and device, storage medium and computer program product, which improve the data transmission efficiency between different computing devices in a device interconnection system.

[0005] To achieve the above-mentioned purpose, the present application provides a device interconnection system, including a processor and multiple computing devices, wherein the processor is connected to a processor memory, the computing devices are connected to a computing device memory, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0006] The computing device comprises a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port;

[0007] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0008] The computing device includes a first target port and a second target port, the computing device receives data sent by other computing devices through the first target port, and the computing device sends data to other computing devices through the second target port.

[0009] The processor includes a processor core, a port module, and a first memory controller that are interconnected, the processor is connected to the processor memory through the first memory controller, and the port module includes a plurality of first ports that comply with a preset protocol;

[0010] The computing device comprises a second port conforming to a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller, the address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller, and the computing device is connected to the computing device memory through the second memory controller;

[0011] The processor is connected to second ports of different computing devices respectively through the plurality of first ports.

[0012] The processor further includes a unified addressing management module, and the unified addressing management module is used to uniformly address the processor memory and the memories of the plurality of computing devices;

[0013] The computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

[0014] The memory decoder in the computing device is specifically used for:

[0015] When the processor accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device;

[0016] When a computing unit of the current computing device accesses a computing device memory of the current computing device, converting the unified addressing into an address on an internal bus of the device;

[0017] When a computing unit of the current computing device accesses the processor memory, no address translation is performed;

[0018] When a computing unit of a current computing device accesses a computing device memory of another computing device, no address translation is performed;

[0019] When a computing unit of another computing device accesses the computing device memory of the current computing device, the unified addressing is converted into an address on the internal bus of the device.

[0020] Wherein, the computing device is a field programmable gate array.

[0021] The i-1th computing device is connected to the ith computing device, 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0022] The computing device includes a first target port and a second target port, the second target port of the i-1th computing device is connected to the first target port of the i-th computing device, and the i-1th computing device sends data to the i-th computing device through the second target port of the i-1th computing device and the first target port of the i-th computing device.

[0023] Wherein, the processor is used to: write input data into the processor memory;

[0024] The first computing device is used to: obtain input data from the processor memory through a bus that complies with a preset protocol, perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in its corresponding computing device memory;

[0025] The i-th computing device is used to: obtain the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculation of the hidden layer corresponding to itself on the obtained data to obtain the result data, and store it in the computing device memory corresponding to itself;

[0026] The Nth computing device writes the result data obtained by the calculation as output data into the processor memory via a bus that complies with a preset protocol.

[0027] To achieve the above-mentioned purpose, the present application provides a data processing method, which is applied to a computing device in a device interconnection system, wherein the device interconnection system includes a processor and multiple computing devices, wherein the processor is connected to a processor memory, and the computing device is connected to a computing device memory, wherein the processor and the multiple computing devices are connected via a bus conforming to a preset protocol, wherein the computing device includes a target port, and the i-1th computing device is connected to the i-th computing device via the target port, 1<i≤N, and N is the number of computing devices included in the device interconnection system;

[0028] The method comprises:

[0029] The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores the result data in its corresponding computing device memory;

[0030] The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of the corresponding hidden layer on the obtained data to obtain the result data, and stores it in the corresponding computing device memory;

[0031] The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0032] Wherein, the processor memory and the multiple computing device memories are addressed in a unified addressing manner;

[0033] The method further comprises:

[0034] Obtaining an address mapping table; wherein the address mapping table includes a correspondence between a starting source address and a starting destination address in different usage scenarios;

[0035] Matching a corresponding target usage scenario in the address mapping table according to a target starting source address of a data access request;

[0036] According to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, the target starting destination address corresponding to the target starting source address is determined.

[0037] Wherein, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table includes:

[0038] The target start source address is converted into an address on the internal bus of the device as the target start destination address.

[0039] Wherein, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, then according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, determining the target starting destination address corresponding to the target starting source address includes:

[0040] The target start source address is converted into an address on the internal bus of the device as the target start destination address.

[0041] Wherein, if the target usage scenario is that a computing unit of the current computing device accesses the processor memory, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0042] The target starting source address is directly used as the target starting destination address.

[0043] Wherein, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, then according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, determining the target starting destination address corresponding to the target starting source address includes:

[0044] The target starting source address is directly used as the target starting destination address.

[0045] Wherein, if the target usage scenario is that a computing unit of another computing device accesses a computing device memory of the current computing device, then according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, determining the target starting destination address corresponding to the target starting source address includes:

[0046] The target start source address is converted into an address on the internal bus of the device as the target start destination address.

[0047] To achieve the above-mentioned purpose, the present application provides a data processing device, which is applied to a computing device in a device interconnection system, wherein the device interconnection system includes a processor and multiple computing devices, wherein the processor is connected to a processor memory, and the computing device is connected to a computing device memory, wherein the processor and the multiple computing devices are connected via a bus conforming to a preset protocol, wherein the computing device includes a target port, and the i-1th computing device is connected to the i-th computing device via the target port, 1<i≤N, and N is the number of computing devices included in the device interconnection system;

[0048] An acquisition unit, configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or to acquire result data calculated by other computing devices from other computing devices via the target port;

[0049] A computing unit, used to perform calculations of the hidden layer corresponding to itself on the acquired data to obtain result data, and store the result data in the memory of the computing device corresponding to itself;

[0050] The output unit is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0051] To achieve the above objectives, the present application provides an electronic device, including:

[0052] Memory for storing computer programs;

[0053] A processor is used to implement the steps of the above-mentioned data processing method when executing the computer program.

[0054] To achieve the above objectives, the present application provides a non-volatile storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above data processing method are implemented.

[0055] To achieve the above objectives, the present application provides a computer program product, including a computer program, which implements the steps of the above data processing method when executed by a processor.

[0056] It can be seen from the above scheme that a device interconnection system provided by the present application includes a processor and multiple computing devices, the processor is connected to a processor memory, the computing device is connected to a computing device memory, and the processor and the multiple computing devices are connected through a bus that complies with a preset protocol; the computing device includes a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port; the processor memory and the multiple computing device memories are addressed in a unified addressing manner, and when the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0057] The present application adds a target port on the computing device, and different computing devices are directly connected through the target port. Different computing devices transmit data directly through the target port, without passing through a bus that complies with a preset protocol and connects the processor, which reduces the transmission pressure of the bus and improves the data transmission efficiency between different computing devices. In addition, the present application uses a unified addressing method to address the processor memory and the computing device memory, and the computing device performs address mapping between the unified addressing and the internal address space of the computing device, which simplifies the address access method and data transmission method. The present application also discloses a data processing method, a device, an electronic device, a non-volatile storage medium, and a computer program product, which can also achieve the above-mentioned technical effects.

[0058] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific implementation methods, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0060] Figure 1 It is an architecture diagram of a device interconnection system in the related art;

[0061] Figure 2 A schematic diagram of a computing process of a device interconnection system in an application scenario in the related technology;

[0062] Figure 3 A schematic diagram of the connection between a processor and a single computing device in a device interconnection system in the related art;

[0063] Figure 4 A flowchart of the overall operation of the device interconnection system in the related technology;

[0064] Figure 5 is an architecture diagram of a device interconnection system according to an exemplary embodiment;

[0065] Figure 6 The figure is a schematic diagram showing a connection between a single computing device and a processor according to an exemplary embodiment;

[0066] Figure 7 is an architecture diagram of another device interconnection system according to an exemplary embodiment;

[0067] Figure 8 An architecture diagram of a device interconnection system in an application scenario provided by this application;

[0068] Fig. 9 is a calculation flow chart of a calculation unit according to an exemplary embodiment;

[0069] Fig.10 is a schematic diagram showing another connection between a single computing device and a processor according to an exemplary embodiment;

[0070] Fig.11 The present invention is an overall flow chart showing the operation of a device interconnection system according to an exemplary embodiment;

[0071] Fig.12 is a flow chart of a data processing method according to an exemplary embodiment;

[0072] Fig.13 is a structural diagram of a data processing device according to an exemplary embodiment;

[0073] Fig.14 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0075] In the related art, the architecture diagram of the device interconnection system is as follows Figure 1 As shown, the processor is connected to the processor memory, and the processor and multiple computing devices are connected through a bus that conforms to the preset protocol. The preset protocol can be the PCIe protocol, that is, multiple computing devices are respectively inserted into the PCIe slots of the host. The processor is responsible for starting the AI ​​computing program and for scheduling different computing devices for calculation. The processor will put the source data to be calculated on the host memory and then notify the computing device to read it. The computing device reads the source data through the bus that conforms to the preset protocol, and after calculation, writes the calculation results to the processor memory or other computing devices through the bus that conforms to the preset protocol.

[0076] In actual computing scenarios, computing work is performed by computing devices, and various data are stored in the processor memory or the internal memory of the computing device. Within the same host, data is transferred between various devices and memory through a bus that complies with the preset protocol (such as the PCIe bus). Figure 2 A calculation process in an application scenario is shown, including the following steps:

[0077] ①The processor writes the input data to the processor memory.

[0078] ② Computing device 1 reads input data from the processor memory through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) of hidden layer 1, and obtains the result data of hidden layer 1.

[0079] ③ Computing device 2 reads the data of hidden layer 1 from computing device 1 through a bus that conforms to a preset protocol, performs operations (convolution, pooling, etc.) on hidden layer 2, and obtains result data of hidden layer 2.

[0080] ④ The computing device 3 reads the data of the hidden layer 2 from the computing device 2 through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) on the hidden layer 3, and obtains the result data of the hidden layer 3.

[0081] ⑤ The computing device 4 reads the data of the hidden layer 3 from the computing device 3 through a bus that complies with the preset protocol, performs the final operation, and obtains the final result data.

[0082] ⑥ The computing device 4 writes the result data to the processor memory via a bus that complies with the preset protocol.

[0083] In the above scheme, the computational workload is distributed to multiple computing devices, and pipeline operations can be performed. For example, the processor can continuously provide new input data. While computing device 1 is performing hidden layer 1 operations on the current batch of data, computing device 2 is performing hidden layer 2 operations on the previous batch of data. Similarly, at a certain point in time, Figure 2 The computing scenario in the example can calculate four batches of data at the same time, making full use of the computing power of the computing device.

[0084] However, the above solution will encounter a problem when it is executed: almost every step of data transmission (except step ①) requires the use of the bus of the preset protocol. As the entire process is streamlined, four computing devices may apply to use the bus of the preset protocol at the same time. At this time, the bus of the preset protocol becomes the bottleneck of the entire system. For example, a computing device may need to wait for the data transmission of the other three computing devices to complete before it can start working, which greatly reduces the computing speed of the entire system.

[0085] Take the connection between a processor and a single computing device as an example, Figure 3 As shown, computing devices generally provide at least two Bars (base address registers) for the processor to access itself. One is the VRAM (Video Random Access Memory) Bar. After the processor maps the address to this Bar, it can directly read and write the contents of the memory on the computing device through address access, which can be referred to as the computing device memory. The computing device memory includes a page table. The other is the register Bar. After the processor maps the address to this Bar, it can use it to read and write various configurations in the computing device and operate various functions, such as initiating data transmission, reading interrupt status, restarting the device, etc.

[0086] There are multiple functional modules inside the computing device. The artificial intelligence (AI) computing unit is responsible for performing specific AI calculations, the communication component (MailBox) is responsible for assisting other modules to communicate with the processor, the MCU (Micro Controller Unit) is responsible for restarting and power management, the DMA (Direct Memory Access) data transmission module is responsible for accessing the processor memory through DMA, and the address translation unit is responsible for helping other modules to access the computing device memory or processor memory after converting virtual addresses to physical addresses. The computing device also includes an interrupt management module and a module for assisting the processor to access VRAM.

[0087] The processor includes virtual memory space, mapped video random access memory, and mapped registers. The software running on the processor can be divided into three parts. KMD (Kernel Mode Driver) has the highest system authority, among which the Linux DRM driver is responsible for memory management, the computing device driver is responsible for initialization work such as Bar mapping and firmware loading, and the IOCTL driver is responsible for assisting UMD (User Mode Driver) in address conversion, allocating VRAM address segments for various functions, creating pages for computing devices, etc. and writing them to VRAM to assist the computing unit and MCU in the computing device to access VRAM or host memory. KMD is also responsible for handling error interrupts, etc. UMD is the middle layer, and the runtime library is responsible for providing API (Application Programming Interface) and device management to the application. The computing module is responsible for device management, creating data streams (queues), deploying computing models, initiating operations, etc. The address mapping module maps memory to the computing device. The application is at the top layer and directly calls the API provided by the ordinary Glibc dynamic library and UMD to perform the computing tasks required by the user, which can include AI computing applications.

[0088] Figure 4The simple workflow of the relevant technical solution is shown, including system startup, initialization process and calculation process. The initialization process includes: loading KMD, KMD performs basic initialization on the computing device, such as mapping Bar, loading firmware, etc., starting the application, calling the Devicelnit (device initialization), SetDevice (setting device), CreateEngine (creating engine), CreateContext (creating context), StreamCreate (creating stream), DeployNetwork (deploying network) and other interfaces provided by UMD, and allocating buffers for storing source data and result data in the processor memory and VRAM. The calculation process includes: writing source data to the processor memory, initiating calculation, that is, writing registers to notify the computing device to read source data from the processor memory to VRAM, and calculating, waiting for the computing device to complete the calculation, and writing the result from VRAM to the result data bufer (cache) of the processor memory, judging whether the calculation is completed, if so, exit, if not, return to the step of writing source data to the processor memory. It can be seen that each initialization process consumes a long time, but the number of executions is limited, so it has almost no effect on the overall computing performance. The time consumed by each calculation process has a great impact on the overall computing performance because it is generally executed many times.

[0089] In the above-mentioned device interconnection system, whether it is data transmission between the processor and the computing device, or data transmission between different computing devices, it must be carried out through a bus that complies with the preset protocol, resulting in greater transmission pressure on the bus and lower data transmission efficiency between different computing devices.

[0090] Therefore, the present application adds a target port on the computing device, and different computing devices are directly connected through the target port. Data is directly transmitted between different computing devices through the target port without passing through a bus that complies with a preset protocol and connects the processor, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between different computing devices.

[0091] This embodiment discloses a device interconnection system, such as Figure 5 As shown, it includes a processor and multiple computing devices, the processor is connected to a processor memory, the computing devices are connected to a computing device memory, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0092] The computing device comprises a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port;

[0093] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0094] The computing device in this embodiment may be a GPU (Graphics Processing Unit). Preferably, the computing device may be an FPGA (Field-Programmable Gate Array). Compared with a GPU, the implementation of an FPGA is more flexible. The processor and multiple computing devices are connected via a bus that complies with a preset protocol. The bus that complies with the preset protocol may be a PCIe bus. The processor is connected to the processor memory, and each computing device is connected to its own computing device memory. The processor memory and computing device memory in this embodiment may be DDR (Double Data Rate Synchronous Dynamic Random-Access Memory).

[0095] In this embodiment, a new target port is added to the computing device, and the target ports of different computing devices are directly connected via a SUB (Super United Bus, a customized consistent interconnect bus). Different computing devices can directly transmit data through the target port via the SUB bus without passing through a bus that complies with a preset protocol and is connected to the processor, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between different computing devices.

[0096] As a preferred implementation, the computing device includes a first target port and a second target port, the computing device receives data sent by other computing devices through the first target port, and the computing device sends data to other computing devices through the second target port.

[0097] In a specific implementation, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is used to receive data, and the second target port is used to send data, thereby achieving port isolation between receiving data and sending data, and enabling simultaneous reception and sending of data, further improving the data transmission efficiency between different computing devices.

[0098] As a feasible implementation mode, the processor includes a processor core, a port module, and a first memory controller that are interconnected. The processor is connected to the processor memory through the first memory controller. The port module includes multiple first ports that comply with a preset protocol. The computing device includes a second port that complies with a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller. The address translation unit connects the computing unit, the second port, the target port, and the second memory controller. The computing device is connected to the computing device memory through the second memory controller. The processor is connected to second ports of different computing devices through multiple first ports.

[0099] In a specific implementation, for a single computing device, the connection method between it and the processor is as follows: Figure 6 As shown. The processor includes a processor core, a port module, and a first memory controller, which are interconnected. The port module includes multiple first ports that comply with a preset protocol, which are used to connect multiple different computing devices respectively. The first memory controller is connected to the processor memory to realize reading and writing of data in the processor memory. The computing device includes a second port that complies with the preset protocol, a target port, a computing unit, and a second memory controller. The second port is connected to the corresponding first port in the processor to perform data transmission with the processor, and the target port is connected to other computing devices to perform data transmission with other computing devices. The address conversion unit connects the computing unit, the second port, the target port, and the second memory controller. The address conversion unit is used to realize the conversion between the virtual address and the physical address, and the computing unit is used to perform data calculation using the received data. The second memory controller can be connected to other components through an internal bus interface, and the second memory controller is connected to the computing device memory to realize reading and writing of data in the computing device memory.

[0100] It is understandable that the processor memory and the computing device memory belong to different internal buses, and their addresses are independent of each other, and can be said to belong to different address spaces. However, during the calculation process, the data stored in these memories must be transferred to each other. In order to simplify data transmission, this embodiment adopts global unified addressing, that is, the data stored in the processor memory and the data stored in the computing device memory are allocated non-overlapping addresses in the same address space, which simplifies address access and data transmission when writing processor applications and computing units of computing devices and configuring programs running in address translation units.

[0101] As a preferred embodiment, the processor also includes a unified addressing management module, which is used to uniformly address the processor memory and multiple computing device memories; the computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

[0102] In a specific implementation, a memory decoder is added inside the computing device, between the address translation unit and the internal bus interface. Its main function is to perform address mapping between the processor address space and the computing device address space, as well as between the address spaces of different computing devices. At the same time, an address mapping table is added to the computing device memory, including the correspondence between the starting source address and the starting destination address in different usage scenarios. The memory decoder performs address mapping based on the address mapping table. In the processor, a unified addressing management module is added to the user mode driver, which calls the interface provided by the memory decoder configuration driver, generates an address mapping table, and configures the address of the address mapping table to the memory decoder.

[0103] As a feasible implementation mode, the memory decoder in the computing device is specifically used for: when the processor accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device; when the computing unit of the current computing device accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device; when the computing unit of the current computing device accesses the computing device memory of the processor, no address conversion is performed; when the computing unit of the current computing device accesses the computing device memory of other computing devices, no address conversion is performed; when the computing units of other computing devices access the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device.

[0104] In specific implementations, the memory decoder is responsible for handling address translation between address spaces and determining the access port in the following usage scenarios:

[0105] ① When the processor accesses the memory of the computing device, it converts the unified addressing into the address on the internal bus of the device and accesses the internal bus interface of the device.

[0106] ② When the computing unit of the current computing device accesses the computing device memory of the current computing device, the unified addressing is converted into an address on the internal bus of the device, and the internal bus interface of the device is accessed.

[0107] ③ When the computing unit of the current computing device accesses the processor memory, it does not perform any address conversion and accesses the port that complies with the preset protocol.

[0108] ④ When the computing unit of the current computing device accesses the computing device memory of other computing devices, no address conversion is performed and the target port is accessed.

[0109] ⑤ When the computing unit of other computing devices (through the SUB bus) accesses the computing device memory of the current computing device, the unified address is converted into the address on the internal bus of the device and the internal bus interface of the device is accessed.

[0110] The processor software writes the address mapping method into the address mapping table, and then configures the address of the address mapping table itself to the computing device by writing registers. After the computing device obtains the address of the address mapping table, it reads the content in the address mapping table and performs address conversion, access port selection, and other configurations (such as whether to enable cache) based on the starting and destination addresses in the table entries. It should be noted that the number of table entries is not necessarily the same as the number of usage scenarios, and there can be multiple table entries for the same usage scenario. The source addresses of all table entries cannot overlap, so the source address can be used to index the table entries.

[0111] For example, the address mapping table is shown in Table 1:

[0112] Table 1

[0113]

[0114] It should be noted that not all addresses need to add an entry in Table 1. The base address plus offset method can be used. For example, there is an entry in the address mapping table, the starting source address is 0x00010000, the address length is 0x00001000, and the starting destination address is 0. When the address accessed is 0x00010800, it will be hit by the above entry because it belongs to the range of 0x00010000 to 0x00011000. The offset of its address relative to the starting source address is 0x800, so the destination address is the starting destination address (0) plus 0x800.

[0115] It can be seen that the unified addressing of the memory decoder plus the address mapping table can simplify the memory management method, making it easier for software engineers to make the processor program and the program running in the computing unit of the computing device work together when writing the two, thereby reducing the possibility of problems.

[0116] The embodiment of the present application adds a target port to the computing device, and different computing devices are directly connected through the target port. Different computing devices transmit data directly through the target port, without passing through the bus that complies with the preset protocol connected to the processor, which reduces the transmission pressure of the bus and improves the data transmission efficiency between different computing devices. In addition, the embodiment of the present application uses a unified addressing method to address the processor memory and the computing device memory, and the computing device performs address mapping between the unified addressing and the internal address space of the computing device, which simplifies the address access method and data transmission method.

[0117] This embodiment discloses a device interconnection system, such as Figure 7 As shown, it includes a processor and multiple computing devices, the processor is connected to a processor memory, the computing devices are connected to a computing device memory, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0118] The computing device includes a target port, and the i-1th computing device is connected to the ith computing device through the target port, 1<i≤N, N is the number of computing devices included in the device interconnection system;

[0119] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0120] In this embodiment, multiple computing devices are connected in series through the target port. For a single computing device, it only needs to receive data sent by one other computing device and only needs to send data to one other computing device, which reduces the amount of data transmitted between different computing devices, reduces the transmission pressure of the SUB bus between the target ports, and further improves the data transmission efficiency between computing devices.

[0121] As a preferred embodiment, the computing device includes a first target port and a second target port, the second target port of the i-1th computing device is connected to the first target port of the i-th computing device, and the i-1th computing device sends data to the i-th computing device through the second target port of the i-1th computing device and the first target port of the i-th computing device.

[0122] In a specific implementation, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is used to receive data, and the second target port is used to send data, thereby achieving port isolation between receiving data and sending data, and enabling simultaneous reception and sending of data, further improving the data transmission efficiency between different computing devices.

[0123] An application scenario of this embodiment is described below. Figure 8 As shown, target port 1 of computing device 1 is connected to target port 0 of computing device 2, target port 1 of computing device 2 is connected to target port 0 of computing device 3, target port 1 of computing device 3 is connected to target port 0 of computing device 4, and target port 0 of computing device 1 and target port 1 of computing device 4 are left vacant.

[0124] As a feasible implementation mode, the processor is used to write input data into the processor memory; the first computing device is used to obtain input data from the processor memory via a bus that complies with a preset protocol, perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and store the result data in its own corresponding computing device memory; the i-th computing device is used to obtain result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device via the target port, perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and store the result data in its own corresponding computing device memory; wherein the N-th computing device writes the calculated result data as output data into the processor memory via a bus that complies with the preset protocol.

[0125] The coordinated calculation process of each computing device is as follows:

[0126] ①The processor writes the input data to the processor memory.

[0127] ② Computing device 1 reads input data from the processor memory through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) of hidden layer 1, and obtains the result data of hidden layer 1.

[0128] ③ Computing device 2 reads the data of hidden layer 1 from computing device 1 through the SUB bus, performs operations (convolution, pooling, etc.) on hidden layer 2, and obtains the result data of hidden layer 2.

[0129] ④ The computing device 3 reads the data of the hidden layer 2 from the computing device 2 via the SUB bus, performs operations (convolution, pooling, etc.) on the hidden layer 3, and obtains the result data of the hidden layer 3.

[0130] ⑤ The computing device 4 reads the data of the hidden layer 3 from the computing device 3 via the SUB bus, performs the final operation, and obtains the final result data.

[0131] ⑥ The computing device 4 writes the result data to the processor memory via a bus that complies with the preset protocol.

[0132] The calculation process of the calculation unit in each computing device is as follows Fig. 9As shown in the figure, the circles represent data, and the arrows represent the relationship between the data and the calculation process. The original data is first stored in the input layer, and after calculations in multiple hidden layers, the final calculation results are placed in the output layer. The hidden layer can be any one or a combination of convolutional layers, pooling layers, fully connected layers, or other calculation methods.

[0133] Take the connection between a processor and a single computing device as an example, Fig.10 As shown, computing devices generally provide at least two Bars (base address registers) for the processor to access itself. One is the VRAM (Video Random Access Memory) Bar. After the processor maps the address to this Bar, it can directly read and write the contents of the memory on the computing device through address access, which can be referred to as the computing device memory. The computing device memory includes a page table and an address mapping table. The other is the register Bar. After the processor maps the address to this Bar, it can use it to read and write various configurations in the computing device and operate various functions, such as initiating data transmission, reading interrupt status, restarting the device, etc.

[0134] There are multiple functional modules inside the computing device. Among them, the artificial intelligence (AI) computing unit is responsible for performing specific AI calculations, the communication component (MailBox) is responsible for assisting other modules to communicate with the processor, the MCU (Micro Controller Unit) is responsible for restarting and power management, etc., the DMA (Direct Memory Access) data transmission module is responsible for accessing the processor memory through DMA, and the address conversion unit is responsible for helping other modules to access the computing device memory or processor memory after converting the virtual address to the physical address. The computing device also includes an interrupt management module and a module for assisting the processor to access VRAM. The computing device also includes a memory decoder and a control module for the target port. The memory decoder is used to map addresses between the processor address space and the computing device address space, and between the address spaces of different computing devices. The control module of the target port is used to control the target port to transmit data between different computing devices.

[0135] The processor includes virtual memory space, mapped video random access memory, and mapped registers. The software running on the processor can be divided into three parts. KMD has the highest system authority, among which the Linux DRM driver is responsible for memory management, the computing device driver is responsible for initialization work such as Bar mapping and firmware loading, and the IOCTL driver is responsible for assisting UMD in address conversion, allocating VRAM address segments for various functions, creating pages for computing devices, etc. and writing them to VRAM to assist the computing unit and MCU in the computing device to access VRAM or host memory. The memory decoder configuration driver is responsible for assisting UMD in configuring the memory decoder and related address mapping tables. KMD is also responsible for handling error interrupts, etc. UMD is the middle layer, and the runtime library is responsible for providing APIs and device management to applications. The computing module is responsible for device management, creating data streams (queues), deploying computing models, initiating operations, etc. The address mapping module maps memory to computing devices. The unified addressing management module is responsible for calling the interface provided by the memory decoder configuration driver, generating an address mapping table, and configuring the address of the address mapping table to the memory decoder. The application is at the top layer and directly calls the API provided by the ordinary Glibc dynamic library and UMD to perform the computing tasks required by the user, which can include AI computing applications.

[0136] The overall flow chart of the equipment interconnection system operation is as follows: Fig.11 As shown, it includes system startup, initialization process and calculation process. The initialization process includes: loading KMD, KMD performs basic initialization on the computing device, such as mapping Bar, loading firmware, etc., starting the application, calling the Devicelnit (device initialization), SetDevice (setting device), CreateEngine (creating engine), CreateContext (creating context), StreamCreate (creating stream), DeployNetwork (deploying network) and other interfaces provided by UMD, allocating buffers for storing source data and result data in the processor memory and computing device memory, creating addresses, and writing registers to configure the computing device. The calculation process includes: writing source data to the processor memory, initiating calculations for all computing devices in turn, that is, writing registers to notify the computing device to read source data from the processor memory or other computing device memory to the computing device, and calculating, waiting for the computing device to complete the calculation, and writing the result from its own computing device memory to the result data bufer (cache) of the computing device memory or processor memory of other computing devices, judging whether the calculation is completed, if so, exit, if not, return to the step of writing source data to the processor memory.

[0137] It can be seen that in this embodiment, each computing device implements a stream-line computing task through multiple computing devices connected in series via the target port, and data transmission between adjacent computing devices does not need to pass through a bus that connects the processor and complies with a preset protocol, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between adjacent computing devices.

[0138] An embodiment of the present application discloses a data processing method, which is applied to a computing device in a device interconnection system. The device interconnection system includes a processor and multiple computing devices. The processor is connected to a processor memory, and the computing device is connected to a computing device memory. The processor and the multiple computing devices are connected via a bus that complies with a preset protocol. The computing device includes a target port, and the i-1th computing device is connected to the i-th computing device via the target port, 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0139] See also Fig.12 , a flowchart of a data processing method according to an exemplary embodiment is shown, as Fig.12 As shown, including:

[0140] S101: The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations of its own corresponding hidden layer on the obtained data to obtain result data, and stores the result data in its own corresponding computing device memory;

[0141] S102: The i-th computing device obtains result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of the corresponding hidden layer on the obtained data to obtain result data, and stores the result data in the computing device memory corresponding to the i-1-th computing device;

[0142] S103: The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0143] In a specific implementation, the first computing device obtains input data from the processor memory through a bus that complies with a preset protocol, uses the computing unit therein to perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores it in the memory of the computing device corresponding to itself. The hidden layer of the computing unit can be any one or a combination of several of the convolutional layer, pooling layer, fully connected layer or other computing methods. The first computing device sends the calculated result data to the first target port of the second computing device through its second target port, and the second computing device uses the computing unit therein to perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores it in the memory of the computing device corresponding to itself. And so on, until the Nth computing device calculates the result data, and writes it as output data to the processor memory through a bus that complies with a preset protocol.

[0144] It can be seen that in this embodiment, each computing device implements a stream-line computing task through multiple computing devices connected in series via the target port, and data transmission between adjacent computing devices does not need to pass through a bus that connects the processor and complies with a preset protocol, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between adjacent computing devices.

[0145] On the basis of the above embodiments, as a preferred implementation mode, the processor memory and the multiple computing device memories are addressed in a unified addressing manner; the method also includes: obtaining an address mapping table; wherein the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios; matching the corresponding target usage scenario in the address mapping table according to the target starting source address of the data access request; determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table.

[0146] In the specific implementation, global unified addressing is adopted, that is, non-overlapping addresses are allocated to the data stored in the processor memory and the data stored in the computing device memory in the same address space. When writing the processor application and the computing unit of the computing device and configuring the program running in the address translation unit, address access and data transfer will become simple. The processor software writes the address mapping method into the address mapping table, including the correspondence between the starting source address and the starting destination address in different usage scenarios, and then configures the address of the address mapping table itself to the computing device by writing a register. After the computing device obtains the address of the address mapping table, it reads the content in the address mapping table, and performs address translation, access port selection and other configurations (such as whether to enable cache) according to the starting destination address in the table entry.

[0147] As a feasible implementation method, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0148] In a specific implementation, when the processor accesses the memory of the computing device, the unified address is converted into an address on the internal bus of the device, and the internal bus interface of the device is accessed. This usage scenario can be applied to the step of "the first computing device obtains input data from the processor memory through a bus that complies with a preset protocol".

[0149] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0150] In a specific implementation, when the computing unit of the current computing device accesses the computing device memory of the current computing device, the unified address is converted into an address on the internal bus of the device, and the internal bus interface of the device is accessed. This usage scenario can be applied to the step of "the computing device stores the calculation result in its corresponding computing device memory".

[0151] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: directly using the target starting source address as the target starting destination address.

[0152] In a specific implementation, when the computing unit of the current computing device accesses the processor memory, no address conversion is performed and the port that complies with the preset protocol is accessed. This usage scenario can be applied to the step of "the Nth computing device writes the result data obtained by the calculation as output data to the processor memory through the bus that complies with the preset protocol".

[0153] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: directly using the target starting source address as the target starting destination address.

[0154] In a specific implementation, when the computing unit of the current computing device accesses the computing device memory of another computing device, no address conversion is performed and the target port is accessed. This usage scenario can be applied to the step of "the i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port".

[0155] As a feasible implementation method, if the target usage scenario is that the computing unit of other computing devices accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0156] In a specific implementation, when the computing unit of another computing device accesses the computing device memory of the current computing device (through the SUB bus), the unified address is converted into an address on the internal bus of the device, and the internal bus interface of the device is accessed. This usage scenario can be applied to the step of "the i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port".

[0157] It can be seen that the unified addressing of the memory decoder plus the address mapping table can simplify the memory management method, making it easier for software engineers to make the processor program and the program running in the computing unit of the computing device work together when writing the two, thereby reducing the possibility of problems.

[0158] A data processing device provided in an embodiment of the present application is introduced below. The data processing device described below and the data processing method described above can refer to each other. The data processing device provided in this embodiment is applied to a computing device in a device interconnection system, wherein the device interconnection system includes a processor and multiple computing devices, wherein the processor is connected to a processor memory, wherein the computing device is connected to a computing device memory, wherein the processor and the multiple computing devices are connected via a bus that complies with a preset protocol, wherein the computing device includes a target port, wherein the i-1th computing device is connected to the ith computing device via the target port, wherein 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0159] See also Fig.13 , a structural diagram of a data processing device according to an exemplary embodiment, such as Fig.13 As shown, including:

[0160] The acquisition unit 100 is used to acquire input data from the processor memory through a bus that complies with a preset protocol, or to acquire result data calculated by other computing devices from other computing devices through the target port;

[0161] The computing unit 200 is used to perform calculations of the hidden layer corresponding to the acquired data to obtain result data, and store the result data in the memory of the computing device corresponding to the computing unit;

[0162] The output unit 300 is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0163] It can be seen that in this embodiment, each computing device implements a stream-line computing task through multiple computing devices connected in series via the target port, and data transmission between adjacent computing devices does not need to pass through a bus that connects the processor and complies with a preset protocol, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between adjacent computing devices.

[0164] Based on the above embodiment, as a preferred implementation, the processor memory and the multiple computing device memories are addressed in a unified addressing manner;

[0165] The device also includes:

[0166] An address mapping unit is used to obtain an address mapping table; wherein the address mapping table includes the correspondence between the starting source address and the starting destination address in different usage scenarios; the corresponding target usage scenario is matched in the address mapping table according to the target starting source address of the data access request; and the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address in the target usage scenario in the address mapping table.

[0167] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0168] On the basis of the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0169] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, the address mapping unit is specifically used to: directly use the target starting source address as the target starting destination address.

[0170] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, the address mapping unit is specifically used to: directly use the target starting source address as the target starting destination address.

[0171] On the basis of the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of other computing devices accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0172] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0173] Based on the hardware implementation of the above program module, and in order to implement the method of the embodiment of the present application, the embodiment of the present application also provides an electronic device, Fig.14 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Fig.14As shown, the electronic equipment includes:

[0174] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0175] The processor 2 is connected to the communication interface 1 to realize information exchange with other devices and is used to execute the data processing method provided by one or more technical solutions when running a computer program. The computer program is stored in the memory 3.

[0176] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig.14 Various buses are labeled as bus system 4 .

[0177] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0178] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0179] The method disclosed in the above embodiment of the present application can be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 2 or the instruction in the form of software. The above processor 2 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 3, and the processor 2 reads the program in the memory 3 and completes the steps of the above method in combination with its hardware.

[0180] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented, which will not be repeated here for the sake of brevity.

[0181] In an exemplary embodiment, the embodiment of the present application further provides a non-volatile storage medium storing a computer program, which can be executed by the processor 2 to complete the steps of the aforementioned method.

[0182] In an exemplary embodiment, the present application also provides a computer program product, including a computer program, which is executed by the processor 2 to complete the steps of the aforementioned method.

[0183] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to computer program instructions, and the aforementioned computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps of the above-mentioned method embodiment. Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product, which is stored in a non-volatile storage medium and includes a number of instructions for an electronic device (which can be a personal computer, a server, a network device, etc.) to execute all or part of the methods described in each embodiment of the present application.

[0184] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A device interconnection system, characterized in that: It includes a processor and a plurality of computing devices, wherein the processor is connected to a processor memory, the computing devices are connected to a computing device memory, and the processor and the plurality of computing devices are connected via a bus conforming to a preset protocol; The computing device comprises a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port; The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

2. The device interconnection system according to claim 1, characterized in that: The computing device comprises a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port, and the computing device sends data to other computing devices through the second target port.

3. The device interconnection system according to claim 1, characterized in that: The processor includes a processor core, a port module, and a first memory controller connected to each other, the processor is connected to the processor memory through the first memory controller, and the port module includes a plurality of first ports that comply with a preset protocol; The computing device comprises a second port conforming to a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller, the address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller, and the computing device is connected to the computing device memory through the second memory controller; The processor is connected to second ports of different computing devices respectively through the plurality of first ports.

4. The device interconnection system according to claim 3, characterized in that: The processor further includes a unified addressing management module, and the unified addressing management module is used to uniformly address the processor memory and the memories of the plurality of computing devices; The computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

5. The device interconnection system according to claim 4, characterized in that: The memory decoder in the computing device is specifically used for: When the processor accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device; When a computing unit of the current computing device accesses a computing device memory of the current computing device, converting the unified addressing into an address on an internal bus of the device; When a computing unit of the current computing device accesses the processor memory, no address translation is performed; When a computing unit of a current computing device accesses a computing device memory of another computing device, no address translation is performed; When a computing unit of another computing device accesses the computing device memory of the current computing device, the unified addressing is converted into an address on the internal bus of the device.

6. The device interconnection system according to claim 1, characterized in that: The computing device is a field programmable gate array.

7. The device interconnection system according to claim 1, characterized in that: The i-1th computing device is connected to the ith computing device, 1<i≤N, and N is the number of computing devices included in the device interconnection system.

8. The device interconnection system according to claim 7, characterized in that: The computing device includes a first target port and a second target port, the second target port of the i-1th computing device is connected to the first target port of the i-th computing device, and the i-1th computing device sends data to the i-th computing device through the second target port of the i-1th computing device and the first target port of the i-th computing device.

9. The device interconnection system according to claim 7, characterized in that: The processor is used to: write input data into the processor memory; The first computing device is used to: obtain input data from the processor memory through a bus that complies with a preset protocol, perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in its corresponding computing device memory; The i-th computing device is used to: obtain the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculation of the hidden layer corresponding to itself on the obtained data to obtain the result data, and store it in the computing device memory corresponding to itself; The Nth computing device writes the result data obtained by the calculation as output data into the processor memory via a bus that complies with a preset protocol.

10. A data processing method, characterized in that: A computing device applied to a device interconnection system, the device interconnection system comprising a processor and a plurality of computing devices, the processor being connected to a processor memory, the computing device being connected to a computing device memory, the processor and the plurality of computing devices being connected via a bus conforming to a preset protocol, the computing device comprising a target port, the i-1th computing device being connected to the ith computing device via the target port, 1<i≤N, N being the number of computing devices included in the device interconnection system; The method comprises: The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores the result data in its corresponding computing device memory; The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of the corresponding hidden layer on the obtained data to obtain the result data, and stores it in the corresponding computing device memory; The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

11. The data processing method according to claim 10, characterized in that: The processor memory and the multiple computing device memories are addressed in a unified addressing manner; The method further comprises: Obtaining an address mapping table; wherein the address mapping table includes a correspondence between a starting source address and a starting destination address in different usage scenarios; Matching a corresponding target usage scenario in the address mapping table according to a target starting source address of a data access request; According to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, the target starting destination address corresponding to the target starting source address is determined.

12. The data processing method according to claim 11, characterized in that: If the target usage scenario is that the processor accesses the computing device memory of the current computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes: The target start source address is converted into an address on the internal bus of the device as the target start destination address.

13. The data processing method according to claim 11, characterized in that: If the target usage scenario is that a computing unit of the current computing device accesses a computing device memory of the current computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target start source address is converted into an address on the internal bus of the device as the target start destination address.

14. The data processing method according to claim 11, characterized in that: If the target usage scenario is that a computing unit of the current computing device accesses the processor memory, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is directly used as the target starting destination address.

15. The data processing method according to claim 11, characterized in that: If the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is directly used as the target starting destination address.

16. The data processing method according to claim 11, characterized in that: If the target usage scenario is that a computing unit of another computing device accesses a computing device memory of the current computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target start source address is converted into an address on the internal bus of the device as the target start destination address.

17. A data processing device, characterized in that: A computing device applied to a device interconnection system, the device interconnection system comprising a processor and a plurality of computing devices, the processor being connected to a processor memory, the computing device being connected to a computing device memory, the processor and the plurality of computing devices being connected via a bus conforming to a preset protocol, the computing device comprising a target port, the i-1th computing device being connected to the ith computing device via the target port, 1<i≤N, N being the number of computing devices included in the device interconnection system; An acquisition unit, configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or to acquire result data calculated by other computing devices from other computing devices via the target port; A computing unit, used to perform calculations of the hidden layer corresponding to the acquired data to obtain result data, and store the result data in the memory of the computing device corresponding to the computing unit; The output unit is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data processing method according to any one of claims 10 to 16 when executing the computer program.

19. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed, the steps of the data processing method according to any one of claims 10 to 16 are implemented.

20. A computer program product, characterized in that The invention comprises a computer program, which implements the steps of the data processing method according to any one of claims 10 to 16 when being executed.

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