Data transmission method and device of network-on-chip, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a data transmission method and device of a network-on-chip, electronic equipment and a storage medium, and the method comprises the steps that after a first computing node generates first data, identification information is added to the first data, and second data is obtained; the first computing node sends the second data to the second computing node; and the second computing node sorts the second data from the at least one first computing node according to the identification information, and continues to execute the computing task according to the sorted second data. According to the embodiment of the invention, the second data can be obtained after the first data generated by the plurality of computing nodes at the same time are identified, and all the second data can be sent to the network-on-chip at the same time for transmission; the identification information is used for indicating the use sequence of the first data in the subsequent calculation, so that the design complexity and the time overhead of the calculation unit are reduced, the utilization rate of the calculation unit is improved, and the overall calculation efficiency of the network-on-chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of network-on-chip technology, and in particular to a data transmission method, device, electronic device and storage medium of a network-on-chip. Background Art

[0002] When a computing unit performs parallel computing, it will cause data traffic to shrink on the on-chip network. The computing unit needs to receive output data from multiple other computing units. When multiple data arrive out of order, additional components and time are required to reorganize the data, which increases the complexity of the system and reduces the utilization of the computing unit. Summary of the invention

[0003] The embodiments of the present invention provide a data transmission method, device, electronic device and storage medium of an on-chip network, which can solve the problem in the related art that the computational complexity of the on-chip network is high, resulting in reduced utilization of computing units.

[0004] On the one hand, an embodiment of the present invention discloses a data transmission method of a network on chip, which is applied to the network on chip, wherein the network on chip includes a first computing node and a second computing node; the method includes: After generating the first data, the first computing node adds identification information to the first data to obtain second data; the identification information is used to indicate the order in which the first data is used in subsequent computing; The first computing node sends the second data to the second computing node; The second computing node sorts the second data from at least one first computing node according to the identification information, and continues to execute the computing task according to the sorted second data.

[0005] Optionally, the second computing node sorts the second data from the at least one first computing node according to the identification information, and continues to perform the computing task according to the sorted second data, including: The second computing node, in the corresponding target routing node, sorts the second data according to the identification information, and stores the sorted second data in a reordering buffer corresponding to the second computing node; The second computing node reads the second data from the reordering buffer and continues to execute computing tasks based on the second data.

[0006] Optionally, after generating the first data, the first computing node adds identification information to the first data to obtain the second data, including: The first computing node determines identification information corresponding to each first data according to a usage order of the first data in the second computing node; The first computing node adds the identification information to the first data to obtain second data.

[0007] Optionally, after generating the first data, the first computing node adds identification information to the first data, and after obtaining the second data, the method further includes: Determining a target multicast domain to which the second computing node belongs; According to the target multicast domain to which the second computing node belongs, a multicast control field is added to the second data to obtain target data; the multicast control field includes a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node in the target multicast domain; Determining a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm; transmitting the target data to the target multicast domain based on the first routing path; Determining a second routing path within the target multicast domain according to the intra-domain mask field; The target data is sent to a target routing node corresponding to the second computing node based on the second routing path, so that the target routing node reorders the target data.

[0008] Optionally, determining the first routing path outside the target multicast domain according to the multicast control field and the routing algorithm includes: Determining a target multicast domain and a second computing node of the first message based on the multicast control field; Determine a first routing node between the source sending node and the target multicast domain according to a positional relationship between the source sending node of the first message and the target multicast domain; A first routing path outside the target multicast domain is determined according to the first routing node and the routing algorithm.

[0009] Optionally, after the first computing node generates the first data, and before the first computing node adds identification information to the first data and obtains the second data, the method further includes: Splitting the computing task into at least two subtasks; Determine the data transmission requirements between the subtasks, the memory access requirements and the external interface access requirements corresponding to each subtask according to the processing stage to which the subtasks belong and the dependencies between the subtasks; Determining an offloading strategy corresponding to the subtask based on the data transmission requirement, the memory access requirement, and the external interface access requirement; Based on the offloading strategy, the at least two subtasks are offloaded to at least two computing nodes.

[0010] On the other hand, an embodiment of the present invention discloses a data transmission device of a network on chip, which is applied to the network on chip, and the device includes: an obtaining module, configured to add identification information to the first data after the first computing node generates the first data, so as to obtain second data; the identification information is used to indicate the order in which the first data is used in subsequent calculations; A sending module, configured for the first computing node to send the second data to the second computing node; A sorting module is used for the second computing node to sort the second data from at least one first computing node according to the identification information, and continue to execute the computing task according to the sorted second data.

[0011] Optionally, the sorting module includes: A sorting submodule, configured for the second computing node to sort the second data in the corresponding target routing node according to the identification information, and store the sorted second data in a reordering buffer corresponding to the second computing node; The second computing node reads the second data from the reordering buffer and continues to execute computing tasks based on the second data.

[0012] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned on-chip network data transmission method.

[0013] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned data transmission method of the on-chip network.

[0014] The embodiments of the present invention include the following advantages: The embodiment of the present invention provides a data transmission method of a network on chip, which is applied to the network on chip, and the network on chip includes a first computing node and a second computing node; after generating the first data, the first computing node adds identification information to the first data to obtain the second data; the identification information is used to indicate the order of use of the first data in subsequent calculations; the first computing node sends the second data to the second computing node; the second computing node sorts the second data from at least one first computing node according to the identification information, and continues to perform the computing task according to the sorted second data. The embodiment of the present invention can obtain the second data after identifying the first data generated by multiple computing nodes at the same time, and all the second data can be sent to the network on chip for transmission at the same time; the identification information is used to indicate the order of use of the first data in subsequent calculations, which reduces the design complexity and time overhead of the computing unit, improves the utilization rate of the computing unit, and is conducive to improving the overall computing efficiency of the network on chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0016] Figure 1 It is a flowchart of a data transmission method embodiment of a network on chip of the present invention; Figure 2 It is a structural frame of a network on chip of the present invention. Figure 1 ; Figure 3 It is a structural frame of a network on chip of the present invention. Figure 2 ; Figure 4 It is a structural block diagram of an embodiment of a data transmission device of a network on chip of the present invention; Figure 5 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0019] Method Embodiment Reference Figure 1 , shows a flowchart of a data transmission method of a network on chip embodiment of the present invention, the method may specifically include the following steps: Step 101: After generating first data, the first computing node adds identification information to the first data to obtain second data; the identification information is used to indicate the order in which the first data is used in subsequent computing; Step 102: The first computing node sends the second data to the second computing node; Step 103: The second computing node sorts the second data from at least one first computing node according to the identification information, and continues to execute the computing task according to the sorted second data.

[0020] The data transmission method of a network on chip provided by an embodiment of the present invention is applied to a network on chip, and the network on chip includes a first computing node and a second computing node.

[0021] It should be noted that, in the embodiment of the present invention, the first computing node may be any computing unit on the acceleration chip, which is not limited in the embodiment of the present invention.

[0022] In the embodiment of the present invention, the first data may be data on different computing nodes, that is, data without adding identification information.

[0023] Exemplarily, in an embodiment of the present invention, different computing nodes may include different CUs (Compute Units), namely, CU0, CU1, CU8, and CU9. The data on the CU0 node may include (data) Data0, the data on the CU1 node may be Data1, the data on the CU8 node may be Date8, and the data on the CU9 node may be Data9, which is not limited in the embodiment of the present invention.

[0024] In the embodiment of the present invention, the identification information can be used to sort the data in the data packet.

[0025] Exemplarily, in an embodiment of the present invention, the second data may include adding ID (Identifier, identification information) to Data0, Data1, Date8, and Data9, that is, obtaining Data0 (ID0), Data1 (ID1), Data8 (ID2), and Data9 (ID3), which is not limited in the embodiment of the present invention.

[0026] In the embodiment of the present invention, the second data may include data obtained after adding identification information to the first data.

[0027] In an embodiment of the present invention, the process of sorting the second data may include sorting according to the order of the identification information as required, which may include sorting from high to low, or from low to high, etc., which is not limited in the embodiment of the present invention.

[0028] In the embodiment of the present invention, the sorting result may be a sorting result from high to low, or a sorting result from low to high, which is not limited in the embodiment of the present invention.

[0029] Illustratively, in an embodiment of the present invention, after sorting the second data, the sorting results that may be obtained are Data9 (ID3), Data8 (ID2), Data1 (ID1), Data0 (ID0), or Data0 (ID0), Data1 (ID1), Data8 (ID3), Data9 (ID3), etc., which are not limited in the embodiment of the present invention.

[0030] In the embodiment of the present invention, the second computing node may be a node that performs calculations on the sorted data. The computing node may perform calculations such as summing or averaging, which is not limited in the embodiment of the present invention.

[0031] In the embodiment of the present invention, the execution of the computing task may include but is not limited to a sum computing task, or an average computing task, etc., which is not limited in the embodiment of the present invention.

[0032] In an embodiment of the present invention, after generating the first data, the first computing node adds identification information to the first data to obtain the second data; the identification information is used to indicate the order in which the first data is used in subsequent calculations; the first computing node sends the second data to the second computing node; the second computing node sorts the second data from at least one first computing node according to the identification information, and continues to perform the computing task based on the sorted second data. The embodiment of the present invention can obtain the second data after identifying the first data generated simultaneously by multiple computing nodes, and all the second data can be simultaneously sent to the on-chip network for transmission; the identification information is used to indicate the order in which the first data is used in subsequent calculations, which reduces the design complexity and time overhead of the computing unit, improves the utilization rate of the computing unit, and is conducive to improving the overall computing efficiency of the on-chip network.

[0033] In the embodiment of the present invention, in the process of the second computing node sorting the second data from at least one first computing node according to the identification information and continuing to perform the computing task according to the sorted second data, the method may specifically include the following steps: Step 1031: The second computing node sorts the second data according to the identification information in the corresponding target routing node, and stores the sorted second data in a reordering buffer corresponding to the second computing node.

[0034] In the embodiment of the present invention, the target routing node can select a data transmission path according to a specific routing protocol and routing strategy to complete data reception and forwarding.

[0035] In the embodiment of the present invention, the second computing node is mainly responsible for receiving data, transmitting data and temporarily caching data in the corresponding target routing node.

[0036] In the embodiment of the present invention, the sorted second data may include but is not limited to being obtained by sorting from low to high, or being obtained by sorting from high to low, which is not limited in the embodiment of the present invention.

[0037] In an embodiment of the present invention, a reorder buffer (ROB) corresponding to the second computing node is used to complete instructions out of sequence but reorder the results before making them visible to the architecture state, which is a mechanism in computer architecture for optimizing instruction execution efficiency.

[0038] Exemplarily, in an embodiment of the present invention, the working principle is that when an instruction is decoded, the next sequential entry is reserved in the ROB. When the instruction is completed, the result is written to the ROB entry. When the instruction is completed earliest in the ROB without exception, its result is moved to the register file or memory.

[0039] Exemplarily, in the embodiment of the present invention, the advantage is that the ROB can eliminate erroneous dependencies, support precise exception handling, and optimize the instruction execution order to improve performance.

[0040] In the embodiment of the present invention, in the process of sending the second data to the second computing node according to the sorting result, the method may specifically include the following steps: Step 1032: The second computing node reads the second data from the reordering buffer, and continues to execute the computing task based on the second data.

[0041] In an embodiment of the present invention, the second computing node sorts the second data according to the identification information in the corresponding target routing node, and stores the sorted second data in a reordering buffer corresponding to the second computing node. Then, the second computing node reads the second data from the reordering buffer and continues to execute the computing task based on the second data.

[0042] In the embodiment of the present invention, after the first computing node generates the first data, the first computing node adds identification information to the first data to obtain the second data. The method may specifically include the following steps: Step 1011: The first computing node determines identification information corresponding to each first data according to the usage order of the first data in the second computing node.

[0043] In the embodiment of the present invention, when adding identification information to the first data to obtain the second data, the first computing node determines the identification information corresponding to each first data according to the usage order of the first data in the second computing node.

[0044] In the embodiment of the present invention, the usage order of the first data in the second computing node may be from high to low or from low to high, etc., which is not limited in the embodiment of the present application.

[0045] Exemplarily, in an embodiment of the present invention, the identification information corresponding to each first data may include Data0 (ID0), Data1 (ID1), Data8 (ID2), Data9 (ID3), or Data9 (ID0), Data8 (ID1), Data1 (ID2), Data0 (ID3), etc., which is not limited in the embodiments of the present application.

[0046] Step 1012: The first computing node adds identification information to the first data to obtain second data.

[0047] In the embodiment of the present invention, after the first computing node determines the identification information corresponding to each first data according to the usage order of the first data in the second computing node, the first computing node adds the identification information to the first data to obtain the second data.

[0048] Exemplarily, in an embodiment of the present invention, the second data may include adding identification information (ID0) to the data Data0 on the CU0 node to obtain the second data Data0 (ID0), or adding identification information (ID1) to the data Data1 on the CU1 node to obtain the second data, the data on the CU8 node may be Date8, and the data on the CU9 node may be Data9, that is, the second data may include Data0 (ID0), Data1 (ID1), Data8 (ID2), and Data9 (ID3), which is not limited in the embodiments of the present application.

[0049] In the embodiment of the present invention, after the first computing node generates the first data, it adds identification information to the first data, and after obtaining the second data, the method may specifically include the following steps: Step 104: Determine the target multicast domain to which the second computing node belongs.

[0050] In the embodiment of the present invention, after adding identification information to the first data and obtaining the second data, the network on chip may also determine the target multicast domain to which the second computing node belongs.

[0051] In the embodiment of the present invention, the target multicast domain is used to indicate a target computing area for multicast transmission, which is not limited in the embodiment of the present invention.

[0052] Step 105: According to the target multicast domain to which the second computing node belongs, add a multicast control field to the second data to obtain the target data; the multicast control field includes a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node in the target multicast domain.

[0053] In an embodiment of the present invention, after determining the target multicast domain to which the second computing node belongs, the on-chip network can also add a multicast control field to the second data according to the target multicast domain to which the second computing node belongs to obtain the target data; the multicast control field includes a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node within the target multicast domain.

[0054] In the embodiment of the present invention, the multicast control field may include a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node in the target multicast domain.

[0055] In the embodiment of the present invention, the target data may be obtained by adding a multicast control field to the second data.

[0056] In the embodiment of the present invention, the multicast domain indication field is used to indicate the target multicast domain, that is, to determine the area for multicast transmission, which is not limited in the embodiment of the present invention.

[0057] In the embodiment of the present invention, the intra-domain mask field includes a subnet mask used to distinguish a network address part and a host address part in an IP (Internet Protocol), which is not limited in the embodiment of the present invention.

[0058] In the embodiment of the present invention, the second computing node in the target multicast domain may be a computing node in the multicast domain. The number of the computing nodes may include one or more, which is not limited in the embodiment of the present invention.

[0059] Step 106: Determine a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm.

[0060] In an embodiment of the present invention, after adding a multicast control field to the second data according to the target multicast domain to which the second computing node belongs and obtaining the target data, the on-chip network can also determine a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm.

[0061] In the embodiment of the present invention, the core function of the routing algorithm is to determine the transmission path of the data packet in the network. When the data packet is transmitted in the network, the router will forward the data packet to the next node according to the best path calculated by the routing algorithm until the data packet reaches the destination node.

[0062] Exemplarily, in an embodiment of the present invention, common routing algorithm types may include but are not limited to distance vector algorithm, link state algorithm, path vector algorithm, etc. Routing algorithms can be classified according to their adaptability and non-adaptability, which is not limited in the embodiment of the present invention.

[0063] In the embodiment of the present invention, the first routing path outside the target multicast domain may be a path composed of routing nodes involved in calculation outside the target multicast domain, which is not limited in the embodiment of the present invention.

[0064] Step 107: Transmit the target data to the target multicast domain based on the first routing path.

[0065] In the embodiment of the present invention, after determining a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm, the on-chip network may also transmit the target data to the target multicast domain based on the first routing path.

[0066] In the embodiment of the present invention, the on-chip network may transmit the target data to the target multicast domain according to the first routing path, and then perform multicast transmission on the target multicast domain.

[0067] Step 108: Determine a second routing path within the target multicast domain according to the intra-domain mask field.

[0068] In the embodiment of the present invention, after transmitting the target data to the target multicast domain based on the first routing path, the on-chip network may further determine a second routing path within the target multicast domain according to the intra-domain mask field.

[0069] In the embodiment of the present invention, the second routing path within the target multicast domain may be a routing path composed of routing nodes within the target multicast domain, which is not limited in the embodiment of the present invention.

[0070] Step S109: Send the target data to the target routing node corresponding to the second computing node based on the second routing path, so that the target routing node can reorder the target data.

[0071] In an embodiment of the present invention, after determining the second routing path within the target multicast domain according to the intra-domain mask field, the on-chip network can also send the target data to the target routing node corresponding to the second computing node based on the second routing path, so that the target routing node can reorder the target data.

[0072] In the embodiment of the present invention, reordering the target data may be a process of ordering the target data according to identification information of the target data, which is not limited in the embodiment of the present invention.

[0073] In an embodiment of the present invention, in the process of determining a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm, the method may specifically include the following steps: Step 1061: Determine the target multicast domain and the second computing node of the first message based on the multicast control field.

[0074] In an embodiment of the present invention, in the process of determining a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm, the on-chip network can also determine the target multicast domain and the second computing node of the first message based on the multicast control field.

[0075] In the embodiment of the present invention, the target multicast domain of the first message may indicate the multicast area where the first message is located, for subsequent multicast transmission.

[0076] In the embodiment of the present invention, the target node of the first message may be used to process the first message, which is not limited in the embodiment of the present invention.

[0077] Step 1062: Determine a first routing node between the source sending node and the target multicast domain according to the position relationship between the source sending node and the target multicast domain of the first message.

[0078] In an embodiment of the present invention, after determining the target multicast domain and the second computing node of the first message based on the multicast control field, the on-chip network can also determine the first routing node between the source sending node and the target multicast domain based on the positional relationship between the source sending node of the first message and the target multicast domain.

[0079] In the embodiment of the present invention, the source sending node of the first message may be a node that sends the first message, which is not limited in the embodiment of the present invention.

[0080] Exemplarily, in an embodiment of the present invention, if the positional relationship between the source sending node and the target multicast domain is considered, the spatial position of the source sending node and the target multicast domain needs to be included in the calculation input, and the optimal routing node is the node with the least number of hops for this multicast message; if the positional relationship between the source sending node and the target multicast domain is not considered, it is only necessary to select the shortest path to reach any node in the multicast domain according to the routing protocol, and the remaining routing paths are calculated by the routers in the multicast domain.

[0081] In the embodiment of the present invention, the first routing node between the source sending node and the target multicast domain refers to all computing nodes passed through in the process of sending the first message to the target node, that is, the first routing node, which is not limited in the embodiment of the present invention.

[0082] Step 1063: Determine a first routing path outside the target multicast domain according to the first routing node and the routing algorithm.

[0083] In an embodiment of the present invention, after determining the first routing node between the source sending node and the target multicast domain based on the positional relationship between the source sending node of the first message and the target multicast domain, the on-chip network can also determine a first routing path outside the target multicast domain based on the first routing node and the routing algorithm.

[0084] In the embodiment of the present invention, the first routing node may include all routing nodes between the source sending node and the target node, which is not limited in the embodiment of the present invention.

[0085] In the embodiment of the present invention, after the first computing node generates the first data, the first computing node adds identification information to the first data, and before obtaining the second data, the method may specifically include the following steps: Step S110: split the computing task into at least two subtasks.

[0086] In the embodiment of the present invention, after the first computing node generates the first data, it adds identification information to the first data, and before obtaining the second data, the on-chip network may split the computing task into at least two subtasks.

[0087] In the embodiment of the present invention, the computing task may include but is not limited to a summing or averaging computing task, which is not limited in the embodiment of the present invention.

[0088] In an embodiment of the present invention, at least two subtasks may be obtained by dividing or abstracting the computing task into an input layer, several intermediate layers, an output layer, etc., or may be obtained by dividing the computing task into finer granularity subtasks, which are not limited in the embodiment of the present invention.

[0089] Step S111: According to the processing stage to which the subtasks belong and the dependency relationship between the subtasks, determine the data transmission requirements between the subtasks, the memory access requirements and the external interface access requirements corresponding to each subtask.

[0090] In an embodiment of the present invention, after splitting the computing task into at least two subtasks, the on-chip network can also determine the data transmission requirements between the subtasks, the memory access requirements corresponding to each subtask, and the external interface access requirements based on the processing stage to which the subtasks belong and the dependencies between the subtasks.

[0091] In the embodiment of the present invention, the processing stage to which the subtask belongs may include but is not limited to an input stage, or an output stage, etc., which is not limited in the embodiment of the present invention.

[0092] For example, in an embodiment of the present invention, when the inference task Task can be divided into multiple (task) Operations, that is, OP0-OP15, a total of 16 operations, each operation depends on the calculation results of the first two levels (OP0 only depends on the input, and OP1 only depends on the result of OP0), a single chip can run at most 8 of the 16 OPs at the same time. If two chips are available, these 16 operations can be completely performed in parallel, and the operations performed by each CU do not need to change at all. This is static unloading. However, in the case of only one chip, these 16 OPs need to be unloaded to the CU of the chip in a time-sharing manner. Then, according to the stage of T, there may be simultaneous running of OP0-OP7, OP8-OP15 and intermediate situations on the chip (such as OP0 can completely release resources, then the instructions of OP8 can be unloaded to the CU to wait for its data dependency, and the data generated by OP0 to be used for subsequent OPs can be stored at the CU or written back to the memory), until a complete T is completed, that is, semi-static unloading.

[0093] Exemplarily, the dependency relationship between the subtasks may include the case where the computing task T can be divided into tasks OP0-OP15, totaling 16 operations, and each operation depends on the calculation results of the previous two levels (OP0 only depends on the input, and OP1 only depends on the result of OP0), which is not limited in the embodiments of the present invention.

[0094] In the embodiment of the present invention, the transmission path corresponding to each subtask may include a transmission path passing through the least number of computing nodes, which is not limited in the embodiment of the present invention.

[0095] In an embodiment of the present invention, the memory access path corresponding to each subtask may include a mapping and conversion process from a logical address (or virtual address) to a physical address when a CPU (Central Processing Unit) or other processor accesses the memory.

[0096] Step S112: Determine the offloading strategy corresponding to the subtask based on the data transmission requirement, the memory access requirement and the external interface access requirement.

[0097] In an embodiment of the present invention, after determining the data transmission requirements between subtasks, the memory access requirements and the external interface access requirements corresponding to each subtask according to the processing stage to which the subtasks belong and the dependencies between the subtasks, the on-chip network can also determine the unloading strategy corresponding to the subtask based on the data transmission requirements, memory access requirements and external interface access requirements.

[0098] In the embodiment of the present invention, the offloading strategy corresponding to the subtask may include determining based on the node with the least hops of the multicast message, or determining based on the shortest path selected by the routing protocol to reach any node in the multicast domain, which is not limited in the embodiment of the present invention.

[0099] Step S113: based on the offloading strategy, offload at least two subtasks to at least two computing nodes.

[0100] In an embodiment of the present invention, after determining the offloading strategy corresponding to the subtask based on data transmission requirements, memory access requirements and external interface access requirements, the on-chip network can also offload at least two subtasks to at least two computing nodes based on the offloading strategy.

[0101] In the embodiment of the present invention, the at least two computing nodes may include a computing node determined according to a node with the least hop count of the multicast message or a computing node determined according to a shortest path, which is not limited in the embodiment of the present invention.

[0102] Reference Figure 2 , showing a composition structure frame of a network on chip of the present invention Figure 1 , which may include the following: The on-chip network includes PCIe (Peripheral Component Interconnect Express), MC (Memory Controller) and CU, which are not limited in the embodiments of the present invention.

[0103] Exemplarily, in an embodiment of the present invention, different computing nodes may include CU0, CU1, CU8, and CU9. The data on the CU0 node (computing unit) may be Data0, the data on the CU1 node may be Data1, the data on the CU8 node may be Date8, and the data on the CU9 node may be Data9, which is not limited in the embodiment of the present invention.

[0104] Exemplarily, in an embodiment of the present invention, the second data may include adding identification information to Data0, Data1, Date8, and Data9, namely obtaining Data0 (ID0), Data1 (ID1), Data8 (ID2), and Data9 (ID3), which is not limited in the embodiment of the present invention.

[0105] Illustratively, in an embodiment of the present invention, after sorting the second data, the sorting results that may be obtained are Data9 (ID3), Data8 (ID2), Data1 (ID1), Data0 (ID0), or Data0 (ID0), Data1 (ID1), Data8 (ID3), Data9 (ID3), etc., which are not limited in the embodiment of the present invention.

[0106] When a data packet consisting of multiple groups of data is transmitted to the router of the target computing unit, all sub-data packets waiting for the data required by the computing unit in the ROB (ReOrder Buffer) of the router are ready and sorted. After being adjusted into data that can be directly operated by the computing unit, they are sent to the target computing unit in sequence and notified.

[0107] Reference Figure 3 , showing a composition structure frame of a network on chip of the present invention Figure 2 , the on-chip network can include the following: Access devices and routers, access devices include processor cores and cache.

[0108] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0109] Therefore, the on-chip network aims to solve the communication problem within the multi-core processor. The on-chip network is an integrated circuit on a network-based communication subsystem. The on-chip network is a packet switching network based on routers between on-chip systems. The on-chip network technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The processor cores use a message communication mechanism, and use routers and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by bus interconnection in related technologies.

[0110] When a computing unit performs parallel computing, it will cause data traffic to shrink on the on-chip network, increase system complexity, reduce the utilization of the computing unit, and increase the delay in the output of the computing results.

[0111] When a computing task that requires the simultaneous use of multiple computing units to complete collaboratively is offloaded to a deep learning acceleration chip, several computing units responsible for the upstream subtasks of the computing task, based on the slicing and scheduling of the task by the deep learning software stack, at the calculation results obtained by them or at the on-chip network entry router, based on the subsequent participation of the data generated by the computing unit in the calculation, uniquely identify the data expected to arrive at the same computing unit in the entire computing task, and at the previous hop of the computing unit receiving the data, the link layer switch that natively supports the reordering function organizes and reorders the data, thereby reducing the design complexity and time overhead of the storage management unit in the computing unit and improving the utilization rate of the execution components in the computing unit.

[0112] For a computing unit in the acceleration chip, the operands of a certain calculation may be composed of the calculation results from multiple upstream computing units. Due to the uncertainty of the load of different links in the on-chip network, the order of arrival of these data is random, and they need to be organized into a fixed data format before calculation. In this scheme, when the data packet consisting of the above multiple groups of data is transmitted to the router of the target computing unit, all sub-data packets waiting for the data required by the computing unit in the buffer of the router are ready and sorted, and after being adjusted into data that can be directly operated by the computing unit, they are sent to the target computing unit in sequence and notified.

[0113] By designing a link layer message structure that supports reordering and adding corresponding functions in the on-chip network router, the reordering task of part of the many-to-one traffic in the same task can be offloaded to the link layer instead of submitting it to the data application layer. This can reduce the time required for the computing unit to operate on data, improve the utilization rate of the computing unit execution unit and reduce inference latency.

[0114] The router buffer may have insufficient capacity. A further solution is to bind the data storage and management functions to the router and completely offload the data management of the computing unit to the on-chip network, in exchange for greater flexibility at a certain performance cost.

[0115] By utilizing the reordering buffer at the egress of the service port of the on-chip network router of the deep learning chip, different data packets from multiple computing units are organized into the data structure required by the computing units at the link layer.

[0116] In summary, an embodiment of the present invention provides a data transmission method for a network on chip, which is applied to a network on chip. The network on chip includes a first computing node and a second computing node. The network on chip can first obtain the first data corresponding to at least one computing node; at least one computing node is used to collaboratively perform computing tasks; then add identification information to the first data to obtain the second data; the identification information is used to indicate the order in which the first data is used in subsequent calculations; so that the second data can be sorted according to the identification information; the second data is sent to the second computing node according to the sorting result, so that the second computing node continues to perform the computing task according to the second data. The embodiment of the present invention can obtain the second data after identifying the first data generated simultaneously by multiple computing nodes, and all the second data can be sent to the network on chip for transmission at the same time; the identification information is used to indicate the order in which the first data is used in subsequent calculations, which reduces the design complexity and time overhead of the computing unit, improves the utilization rate of the computing unit, and is conducive to improving the overall computing efficiency of the network on chip.

[0117] Device Embodiment Reference Figure 4 , shows a structural block diagram of a data transmission device of a network on chip of the present invention, the device is applied to the network on chip, and the device may specifically include: The obtaining module 401 is used for the first computing node to add identification information to the first data after generating the first data to obtain the second data; the identification information is used to indicate the order of using the first data in subsequent calculations; A sending module 402, configured for the first computing node to send the second data to the second computing node; The sorting module 403 is used for the second computing node to sort the second data from at least one first computing node according to the identification information, and continue to execute the computing task according to the sorted second data.

[0118] Optionally, the sorting module includes: A sorting submodule, configured for the second computing node to sort the second data in the corresponding target routing node according to the identification information, and store the sorted second data in a reordering buffer corresponding to the second computing node; A reading module is used for the second computing node to read the second data from the reordering buffer and continue to execute the computing task based on the second data.

[0119] Optionally, after generating the first data, the first computing node adds identification information to the first data to obtain the second data, including: A determination module, configured for the first computing node to determine identification information corresponding to each first data according to the order in which the first data are used in the second computing node; The obtaining module is used for the first computing node to add the identification information to the first data to obtain second data.

[0120] Optionally, after generating the first data, the first computing node adds identification information to the first data, and after obtaining the second data, the method further includes: A determination submodule, used to determine a target multicast domain to which the second computing node belongs; The obtaining submodule is used to add a multicast control field to the second data according to the target multicast domain to which the second computing node belongs, so as to obtain the target data; the multicast control field includes a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node in the target multicast domain; The determination submodule is further configured to determine a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm; a transmission submodule, configured to transmit the target data to the target multicast domain based on the first routing path; The determination submodule is further configured to determine a second routing path within the target multicast domain according to the intra-domain mask field; The second sending submodule is used to send the target data to the target routing node corresponding to the second computing node based on the second routing path, so that the target routing node can reorder the target data.

[0121] Optionally, determining the first routing path outside the target multicast domain according to the multicast control field and the routing algorithm includes: The first determination submodule is used to determine the target multicast domain and the second computing node of the first message based on the multicast control field; determine the first routing node between the source sending node and the target multicast domain according to the positional relationship between the source sending node of the first message and the target multicast domain; and determine the first routing path outside the target multicast domain according to the first routing node and the routing algorithm.

[0122] Optionally, after generating the first data, the first computing node adds identification information to the first data, and before obtaining the second data, the method further includes: A splitting module, used for splitting the computing task into at least two subtasks; The second determination submodule is used to determine the data transmission requirements between the subtasks, the memory access requirements and the external interface access requirements corresponding to each subtask according to the processing stage to which the subtasks belong and the dependency relationship between the subtasks; and determine the unloading strategy corresponding to the subtask based on the data transmission requirements, the memory access requirements and the external interface access requirements; An offloading module is used to offload the at least two subtasks to at least two computing nodes based on the offloading strategy.

[0123] In summary, an embodiment of the present invention provides a data transmission method of an on-chip network, which is applied to an on-chip network, and the on-chip network includes a first computing node and a second computing node; after the first computing node generates the first data, the on-chip network can add identification information to the first data to obtain the second data; the identification information is used to indicate the order of use of the first data in subsequent calculations; the first computing node sends the second data to the second computing node; the second computing node sorts the second data from at least one first computing node according to the identification information, and continues to perform the computing task according to the sorted second data. The embodiment of the present invention can add an identification to the first data, and after the data arrives at the computing unit, it is organized and sorted according to the identification, which reduces the design complexity and time overhead of the computing unit, improves the utilization rate of the computing unit, and is conducive to improving the overall computing efficiency of the on-chip network.

[0124] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0125] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0126] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0127] Reference Figure 5 , is a structural block diagram of an electronic device for data transmission in a network on chip provided by an embodiment of the present invention. Figure 5As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data transmission method of the on-chip network of the aforementioned embodiment.

[0128] The processor may be a CPU, a general processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0129] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0130] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0131] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1The data transmission method of the on-chip network is shown.

[0132] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0133] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0136] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0137] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0138] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0139] The above is a detailed introduction to the data transmission method, device, electronic device and storage medium of a network on chip provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data transmission method for a network on chip, characterized in that: Applied to a network on chip, the network on chip includes a first computing node and a second computing node; the method includes: After generating the first data, the first computing node adds identification information to the first data to obtain second data; the identification information is used to indicate the order in which the first data is used in subsequent computing; The first computing node sends the second data to the second computing node; The second computing node sorts the second data from at least one first computing node according to the identification information, and continues to execute the computing task according to the sorted second data.

2. The method according to claim 1, characterized in that The second computing node sorts the second data from the at least one first computing node according to the identification information, and continues to perform the computing task according to the sorted second data, including: The second computing node, in the corresponding target routing node, sorts the second data according to the identification information, and stores the sorted second data in a reordering buffer corresponding to the second computing node; The second computing node reads the second data from the reordering buffer and continues to execute computing tasks based on the second data.

3. The method according to claim 1, characterized in that After generating the first data, the first computing node adds identification information to the first data to obtain second data, including: The first computing node determines identification information corresponding to each first data according to a usage order of the first data in the second computing node; The first computing node adds the identification information to the first data to obtain second data.

4. The method according to claim 1, characterized in that: After the first computing node generates the first data, adding identification information to the first data, and obtaining the second data, the method further includes: Determining a target multicast domain to which the second computing node belongs; According to the target multicast domain to which the second computing node belongs, a multicast control field is added to the second data to obtain target data; the multicast control field includes a multicast domain indication field and an intra-domain mask field, the multicast domain indication field is used to indicate the target multicast domain, and the intra-domain mask field is used to indicate the second computing node in the target multicast domain; Determining a first routing path outside the target multicast domain according to the multicast control field and the routing algorithm; transmitting the target data to the target multicast domain based on the first routing path; Determining a second routing path within the target multicast domain according to the intra-domain mask field; The target data is sent to a target routing node corresponding to the second computing node based on the second routing path, so that the target routing node reorders the target data.

5. The method according to claim 4, characterized in that The determining, according to the multicast control field and the routing algorithm, a first routing path outside the target multicast domain comprises: Determining a target multicast domain and a second computing node of the first message based on the multicast control field; Determine a first routing node between the source sending node and the target multicast domain according to a positional relationship between the source sending node of the first message and the target multicast domain; A first routing path outside the target multicast domain is determined according to the first routing node and the routing algorithm.

6. The method according to claim 1, characterized in that After the first computing node generates the first data, the method further includes adding identification information to the first data and before obtaining the second data: Splitting the computing task into at least two subtasks; Determine the data transmission requirements between the subtasks, the memory access requirements and the external interface access requirements corresponding to each subtask according to the processing stage to which the subtasks belong and the dependencies between the subtasks; Determining an offloading strategy corresponding to the subtask based on the data transmission requirement, the memory access requirement, and the external interface access requirement; Based on the offloading strategy, the at least two subtasks are offloaded to at least two computing nodes.

7. A data transmission device for a network on chip, characterized in that: Applied to a network on chip, the device comprises: an obtaining module, configured to add identification information to the first data after the first computing node generates the first data, so as to obtain second data; the identification information is used to indicate the order in which the first data is used in subsequent calculations; A sending module, configured for the first computing node to send the second data to the second computing node; A sorting module is used for the second computing node to sort the second data from at least one first computing node according to the identification information, and continue to execute the computing task according to the sorted second data.

8. The device according to claim 7, characterized in that The sorting module comprises: A sorting submodule, configured for the second computing node to sort the second data in the corresponding target routing node according to the identification information, and store the sorted second data in a reordering buffer corresponding to the second computing node; A reading module is used for the second computing node to read the second data from the reordering buffer and continue to execute the computing task based on the second data.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data transmission method of the on-chip network as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the data transmission method of the on-chip network as claimed in any one of claims 1 to 6.

Images