Extensible modular signal conversion board

Abstract

The invention discloses an extensible modular signal conversion board, and relates to the technical field of integrated circuits. Comprising a control signal interface module, a signal source interface module, a power supply module, a backlight driving circuit, a display screen interface module, a display signal conversion circuit, a USB-HUB circuit, a USB logic circuit and a network-to-USB adapter circuit. Driving of display screens with different sizes and interfaces and rapid matching use with different mainboards are achieved, the signal conversion board can be flexibly matched with various display devices and mainboards through integration of the modules, displays with different display interfaces can be rapidly driven, meanwhile, the hardware development time and the product research and development cycle are shortened, and the cost is reduced. And the development efficiency and the market adaptability of the product are improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to an expandable modular signal conversion board. Background Art

[0002] In today's electronic product market, there are incompatibilities between the data transmission interfaces of various devices such as monitors, TVs, mobile phones, watches, and various display screens, each of which follows different standards and specifications. This incompatibility is mainly manifested in the mechanical and electrical properties of the interface, resulting in the inability to smoothly transmit display signals from one sending end to different display devices, causing many inconveniences for users when replacing or switching display screens.

[0003] Consumer electronics such as mobile phones and tablets usually use MIPI interfaces, while commercial displays and automotive products prefer LVDS interfaces. These two interfaces have significant differences in physical structure and electrical characteristics, making it difficult for them to connect directly to each other. This interface incompatibility not only increases the complexity of the product development process, but also forces developers to redesign the motherboard and add additional bridge display signal modules when designing new products if they need to use CPUs or displays with different interface types. This not only increases the complexity of the design, but also may lead to design errors and rework. In addition, in order to solve the interface incompatibility problem, developers need to invest extra time to design and test new motherboards and signal conversion modules, which prolongs the time from concept to market and affects the market response speed of the product. At the same time, redesigning the motherboard and adding new signal conversion modules not only increases the material cost, but also increases the labor cost of R&D and testing. If there are problems in the design, it may also lead to additional rework and correction costs. Interface incompatibility also limits the design flexibility of the product, forcing developers to consider interface compatibility issues when designing new products, which may limit product innovation and diversity. For end users, interface incompatibility means that they may need additional adapters or converters when using different devices, which not only increases the complexity of use but also affects the user experience. Summary of the invention

[0004] The purpose of the present invention is to provide an expandable modular signal conversion board to drive display screens of different sizes and interfaces, which can be used in conjunction with different mainboards to quickly drive displays with different display interfaces.

[0005] The purpose of the present invention can be achieved through the following technical solutions: The present application provides an expandable modular signal conversion board, including a control signal interface module, a signal source (MIPI) interface module, a power module, a backlight driving circuit, a display interface module, a display signal conversion circuit, a USB-HUB circuit, a USB logic circuit, and a network to USB adapter circuit; The control signal interface module is used to receive signals from a host or other control devices; The signal source interface module is used to receive the MIPI signal from the signal source; The power module provides power to the conversion board; The backlight driving circuit is responsible for controlling the backlight of the display screen; The display screen interface module outputs the converted signal to the target display screen; The display signal conversion circuit converts the MIPI signal into other display interface standards; The USB-HUB circuit is used to expand the USB interface, allowing the conversion board to connect multiple USB devices; The USB logic circuit is used to process USB data transmission and protocol conversion; The network-to-USB adapter circuit converts network signals into USB signals, communicates with the conversion board through the USB interface of the network-connected device, and includes a network interface card and data processing logic.

[0006] Furthermore, the backlight driving circuit includes a chip U15, a first pin of the chip U15 is connected to a feedback terminal FB1, a thirteenth pin of the chip U15 is connected to a feedback terminal FB2, a fourteenth pin of the chip U15 is connected to a feedback terminal FB3, a sixteenth pin of the chip U15 is connected to a feedback terminal FB4, a seventh pin of the chip U15 is connected to a junction of a resistor R26 and a fourth pin of the chip U4 through a resistor R22, a sixth pin of the chip U15 is connected to a junction of a resistor R26, a third pin of the chip U4, a second pin of the chip U4, a first pin of the chip U4 and a resistor R17 through a resistor R25, the resistor R17 is also connected to ground, and an eighth pin of the chip U15 is connected to a ground. The capacitor C70 is connected to the ground, and the capacitor C70 is also connected to VCC. The fifteenth pin and the seventeenth pin of the chip U15 are both connected to the ground. The fifth pin, the seventh pin, the sixth pin and the eighth pin of the chip U4 are mutually connected at the intersection of the diode D11, the diode D6 and one end of the inductor L3. The intersection of the diode D6 and the other end of the inductor L3 is connected to the intersection of the resistor R20, the capacitor C72, the capacitor C71, the capacitor C50 and one end of the capacitor C83. One end of the capacitor C83 is also connected to LCD_LED. The intersection of the capacitor C72, the capacitor C71, the capacitor C50 and the other end of the capacitor C83 is connected to the ground. The third pin of the chip U4 is connected to the intersection of the resistor R20 and the resistor R21. The resistor R21 is also connected to the ground, the ninth pin of the chip U15 is connected to the intersection of the resistor R27 and the capacitor C22, the resistor R27 is also connected to the intersection of the inductor L3, the capacitor C40, the capacitor C23, the capacitor C28, the capacitor C91 and 24V, the capacitor C28 and the capacitor C91 are both connected to the ground, the capacitor C40 and the capacitor C23 are also connected to the ground, the tenth pin of the chip U15 is also connected to the intersection of the resistor R43, the resistor R19 and one end of the capacitor C11, the other end of the resistor R19 and the capacitor C11 intersects with the ground, the other end of the resistor R43 is connected to VCC, and the fifth pin of the chip U15 is also connected to the intersection of the resistor R119 and one end of the resistor R120 , the other end of the resistor R119 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to the junction of one end of the resistor R117 and 3V3, the other end of the resistor R117 is connected to the junction of the base of the transistor Q3 and the resistor R118, the resistor R118 is also connected to the collector of the transistor Q2, the emitter of the transistor Q2 is connected to the ground, the base of the transistor Q2 is connected to GPIO_LCD_EN, the twelfth pin of the chip U15 is connected to the junction of the resistor R56 and BL_PWM, the second pin of the chip U15 is connected to the ground through the resistor R42, the eleventh pin of the chip U15 is connected to the capacitor C1 through the resistor R38, and the capacitor C1 is also connected to the ground,The fourth pin of the chip U15 is connected to the ground through a resistor R39.

[0007] Further, the feedback terminal FB1 is also connected to the intersection of the sixth pin of the connector J6, the test point TP22 and the protection diode VR6, the feedback terminal FB4 is also connected to the intersection of the fifth pin of the connector J6, the test point TP21 and the protection diode VR2, the feedback terminal FB3 is also connected to the intersection of the second pin of the connector J6, the test point TP19 and the protection diode VR7, the feedback terminal FB2 is also connected to the intersection of the first pin of the connector J6, the test point TP18 and the protection diode VR5, the LCD_LED is also connected to the intersection of the second pin of the connector J6, the third pin of the connector J6 and the test point TP20, and the seventh pin of the connector J6 and the eighth pin of the connector J6 are connected to the ground; The BL_PWM is connected at the connection between the resistor R1509 and the resistor R1517, the resistor R1517 is also connected to the collector of the transistor Q1502, the emitter of the transistor Q1502 is connected to the intersection of one end of the resistor R1529 and 3V3, the other end of the resistor R1529 is connected to the intersection of the base of the transistor Q1502 and the resistor R1530, the resistor R1530 is also connected to the collector of the transistor Q1501, the emitter of the transistor Q1501 is connected to the ground, and the base of the transistor Q1501 is connected to DISP_PWM.

[0008] Further, the display signal conversion circuit includes a chip U17, a first pin of the chip U17 is connected to the intersection of VDD, the fifteenth pin of the chip U17 and the thirty-fifth pin of the chip U17, a twelfth pin of the chip U17 is connected to the intersection of VCC18_RX and the sixty-fourth pin of the chip U17, a thirteenth pin of the chip U17 is connected to the intersection of the resistor R90, the capacitor C93 and the first pin of the chip U18, the capacitor C93 is also connected to the ground, a second pin of the chip U18 and a fourth pin of the chip U18 are connected to the ground, and a third pin of the chip U18 is connected to the intersection of the capacitor C124, the resistor R90 and the fourteenth pin of the chip U17 , the twenty-fourth pin of the chip U17 is connected to the thirty-seventh pin of the chip U17 and to VCCIO, the twenty-fifth pin of the chip U17 is connected to DP3_TXB, the twenty-sixth pin of the chip U17 is connected to DN3_TXB, the twenty-seventh pin of the chip U17 is connected to CLKP_TXB, the twenty-eighth pin of the chip U17 is connected to CLKN_TXB, the twenty-ninth pin of the chip U17 is connected to DP2_TXB, the 30th pin of the chip U17 is connected to DN2_TXB, the thirty-first pin of the chip U17 is connected to DP1_TXB, and the thirty-second pin of the chip U17 is connected to DN1_TXB, The thirty-third pin of the chip U17 is connected to DN0_TXB, the thirty-fourth pin of the chip U17 is connected to DP0_TXB, the thirty-sixth pin of the chip U17 is connected to VCC18_TX, the thirty-seventh pin of the chip U17 is connected to VCCIO, the thirty-eighth pin of the chip U17 is connected to DP3_TXA, the thirty-ninth pin of the chip U17 is connected to DN3_TXA, the fortieth pin of the chip U17 is connected to CLKP_TXA, the forty-first pin of the chip U17 is connected to CLKN_TXA, the forty-second pin of the chip U17 is connected to DP2_TXA, the forty-third pin of the chip U17 is connected to DN2_TXA, the forty-fourth pin of the chip U17 is connected to DP1_TXA, the forty-fifth pin of the chip U17 is connected to DN1_TXA, the forty-sixth pin of the chip U17 is connected to DN0_TXA, and the forty-eighth pin of the chip U17 is connected to VCC18.

[0009] Further, the 49th pin of the chip U17 is connected to the junction of LT9211_RST, resistor R31 and capacitor C21, the capacitor C21 is also connected to the ground, the resistor R31 is also connected to VCC18, the 50th pin of the chip U17 is connected to TP_SDA, the 51st pin of the chip U17 is connected to TP_SCI, the 52nd pin of the chip U17 is connected to TP_INT through resistor R112, the 53rd pin of the chip U17 is connected to DSI0_LANE3_N, the 54th pin of the chip U17 is connected to DSI0_LANE3_P, the 55th pin of the chip U17 is connected to DSI0_LANE2_N, and the 56th pin of the chip U17 is connected to DSI0_LANE3_P. The fifty-sixth pin is connected to DSI0_LANE2_P, the fifty-seventh pin of the chip U17 is connected to DSI0_CLK_N, the fifty-eighth pin of the chip U17 is connected to DSI0_CLK_P, the fifty-ninth pin of the chip U17 is connected to DSI0_LANE1_N, the sixtieth pin of the chip U17 is connected to DSI0_LANE1_P, the sixty-first pin of the chip U17 is connected to DSI0_LANE0_N, the sixty-second pin of the chip U17 is connected to DSI0_LANE0_P, the sixty-third pin of the chip U17 is connected to the sixty-fifth pin of the chip U17 through the resistor R93, and the sixty-fifth pin of the chip U17 is also connected to the ground; The VDD is also connected to the junction of one end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206, and the other end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206 is connected to the ground. The VCC18_RX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. The VCC18_TX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. It is connected to the intersection of one end of capacitor C210 and capacitor C227, and the other end of the intersection of capacitor C210 and capacitor C227 is connected to the ground. The VCCIO is also connected to the intersection of one end of capacitor C176, capacitor C178 and capacitor C179, and the other end of the intersection of capacitor C176, capacitor C178 and capacitor C179 is connected to the ground. The VCC18 is also connected to the intersection of one end of capacitor C58 and capacitor C97, and the other end of the intersection of capacitor C58 and capacitor C97 is connected to the ground.

[0010] Further, the USB-HUB circuit includes a chip U2 and a chip U23, the first pin of the chip U2 is respectively connected to the fifth pin of the chip U2 and the tenth pin of the chip U2, the first pin of the chip U2 is also connected to the intersection of capacitor C6, capacitor C7 and one end of resistor B20, the other end of the resistor B20 is connected to the intersection of the sixteenth pin of the chip U2, the twenty-fourth pin of the chip U2, capacitor C8, capacitor C9 and one end of VCC_3V3, the other ends of the capacitors C6, C7, C8 and C9 are mutually connected to the ground, the sixth pin of the chip U2 is connected to 12MHZ_OSC_IN1, the seventh pin of the chip U2 is connected to 12MHZ_OSC_OUT1, the seventeenth pin of the chip U2 is connected to VCC_3V3 through a resistor R164, the fourteenth pin of the chip U2 is connected to the ground through a resistor R165, the thirteenth pin of the chip U2 is connected to resistor R167, capacitor C10, At the intersection of one end of the resistor R166, the other end of the resistor R166 is connected to VCC_3V3, the other ends of the resistor R167 and the capacitor C10 are connected to the ground, the twenty-fifth pin of the chip U2 is connected to USB_DM_HUB, the seventy-twenty-sixth pin of the chip U2 is connected to USB_DP_HUB, the fourth pin of the chip U2 is connected to the ground through the resistor R168, the fifteenth pin of the chip U2 is connected to the ground, the eighteenth pin of the chip U2 is connected to the intersection of the resistor R173 and VCC_3V3 through the resistor R172, the resistor R173 is also connected to the twenty-first pin of the chip U2, the twelfth pin of the chip U2 is connected to the first pin of the filter EMI22, the eleventh pin of the chip U2 is connected to the second pin of the filter EMI22, the third pin of the filter EMI22 is connected to HUB_HOST1_DM4, and the fourth pin of the filter EMI22 is connected to HUB_HOST1_DP4.

[0011] Further, the ninth pin of the chip U2 is connected to the first pin of the filter EMI21, the eighth pin of the chip U2 is connected to the second pin of the filter EMI21, the third pin of the filter EMI21 is connected to HUB_HOST1_DM2, the fourth pin of the filter EMI21 is connected to HUB_HOST1_DP2, the third pin of the chip U2 is connected to the first pin of the filter EMI20, the second pin of the chip U2 is connected to the second pin of the filter EMI20, the third pin of the filter EMI20 is connected to LAN_USB_DM, the fourth pin of the filter EMI20 is connected to LAN_USB_DP, the twenty-eighth pin of the chip U2 is connected to the first pin of the filter EMI19, the twenty-seventh pin of the chip U2 is connected to the second pin of the filter EMI19, the third pin of the filter EMI19 is connected to TP_USB_DM, and the fourth pin of the filter EMI19 is connected to TP_USB_DP; The first pin of the chip U23 is connected to the junction of capacitor C269 and 12MHZ_OSC_OUT1, and the capacitor C269 is also connected to the ground. The second pin of the chip U23 and the fourth pin of the chip U23 are both connected to the ground. The third pin of the chip U23 is connected to the junction of capacitor C32 and 12MHZ_OSC_IN1, and the capacitor C32 is also connected to the ground.

[0012] Furthermore, the network-to-USB adapter circuit includes a chip U21, a chip U46, a connector J2 and a chip U103. The first pin of the chip U21 is connected to the junction of capacitor C139, capacitor C5 and VDD33_PHY, the second pin of the chip U21 is connected to TXOP, the third pin of the chip U21 is connected to TXOH, the fourth pin of the chip U21 is connected to RXIP, the fifth pin of the chip U21 is connected to RXIN, the sixth pin of the chip U21 is connected to ground, the seventh pin of the chip U21 is connected to LAN_USB_DM, the eighth pin of the chip U21 is connected to LAN_USB_DP, and the The ninth pin is connected to the junction of capacitor C135 and VDD10_PHY, the tenth pin of the chip U21 is connected to the junction of capacitor C136, capacitor C131 and VDD33_PHY, the capacitor C136 and capacitor C131 are also connected to the ground, the eleventh pin of the chip U21 is connected to VDD5_PHY, the twelfth pin of the chip U21 is connected to the junction of capacitor C132 and one end of capacitor C134, the other ends of C132 and C134 are connected to the ground, the thirteenth pin of the chip U21 is connected to the junction of capacitor C141 and V The fourteenth pin of the chip U21 is connected to the intersection of the resistor R183, the resistor R184 and VDD33_PHY through the resistor R1, the resistor R183 is also connected to the eighteenth pin of the chip U21, the resistor R184 is also connected to the nineteenth pin of the chip U21, the fifteenth pin of the chip U21 is connected to VDD33_PHY, the sixteenth pin of the chip U21 is connected to the intersection of the capacitor C142 and VDD10_PHY, the seventeenth pin of the chip U21 is connected to LED1_SPEED_Y The 21st pin of the chip U21 is connected to 25MHZ_OSC_OUT, the 22nd pin of the chip U21 is connected to 25MHZ_OSC_IN, the 23rd pin of the chip U21 is connected to the junction of capacitor C143, capacitor C144 and one end of resistor R66, the other ends of capacitor C143 and capacitor C144 are connected to ground, the other end of resistor R66 is connected to VDD10_PHY, the 24th pin of the chip U21 is connected to ground through resistor R85, and the 25th pin of the chip U21 is connected to ground. Further, the VDD33_PHY is connected to the junction of the resistor R134 and one end of the resistor R9, the other end of the resistor R134 is connected to LED1_SPEED_Y through the diode D9, and the other end of the resistor R9 is connected to LED0_LINK_G through the diode D10; The LAN_USB_DM is connected to the test point TP15, the LAN_USB_DP is connected to the test point TP16; the VDD5_PHY is connected to the test point TP17; The first pin of the chip U46 is connected to the junction of the capacitor C484 and 25MHZ_OCS_OUT, and the capacitor C484 is also connected to the ground. The second pin of the chip U46 and the fourth pin of the chip U46 are both connected to the ground. The third pin of the chip U46 is connected to the junction of the capacitor C485 and 25MHZ_OCS_IN, and the capacitor C485 is also connected to the ground. The VDD5_PHY is connected to the junction of the resistor R182, the capacitor C4 and one end of the capacitor C42, the other ends of the capacitor C4 and the capacitor C42 are connected to the ground, and the other end of the resistor R182 is connected to HUB_HOST_VBUS; The first pin of the connector J2 is connected to the connection between the protection diode MLV4, the test point TP51 ​​and one end of TXP, the second pin of the connector J2 is connected to the connection between the protection diode MLV2, the test point TP50 and one end of TXN, the third pin of the connector J2 is connected to the connection between the protection diode MLV6, the test point TP41 and one end of RXP, the fourth pin of the connector J2 and the fifth pin of the connector J2 are connected to each other, the fifth pin of the connector J2 is also connected to the connection between the protection diode MLV5 and one end of the terminal T45, and the sixth pin of the connector J2 is connected to the protection diode MLV6. The diode MLV8, the test point 39 and one end of RXN are connected, the seventh pin of the connector J2 and the eighth pin of the connector J2 are connected to each other, and the eighth pin of the connector J2 is also connected to the connection between the protection diode MLV7 and one end of the terminal T78, the other ends of the protection diodes MLV4, MLV2, MLV6, MLV5, MLV8 and MLV7 are connected to each other and to the ground, and the ninth pin of the connector J2 is connected to the intersection of the tenth pin of the connector J2, the test point TP52 and EARTH_GND.

[0013] Further, the first pin of the chip U103 is connected to RXIP, the second pin of the chip U103 is connected to RXIN, the third pin of the chip U103 is connected to ground through a capacitor C44, the seventh pin of the chip U103 is connected to TXOP, the eighth pin of the chip U103 is connected to TXON, the sixth pin of the chip U103 is connected to ground through a capacitor C43, the ninth pin of the chip U103 is connected to TXN, the tenth pin of the chip U103 is connected to TXP, and the eleventh pin of the chip U103 is connected to ground through a resistor R135. It is connected to the intersection of resistors R5, R6, R136 and one end of capacitor C506, the other end of capacitor C506 is connected to the intersection of capacitor C502, resistor R7 and one end of EARTH_GND, the other ends of capacitor C502 and resistor R7 are connected to ground, the other end of resistor R6 is connected to terminal T78, the other end of resistor R136 is connected to terminal T45, the other end of resistor R5 is connected to the fourteenth pin of chip U103, the fifteenth pin of chip U103 is connected to RXN, and the sixteenth pin of chip U103 is connected to RXP.

[0014] The beneficial effects of the present invention are: The present invention realizes the driving capability of display screens of different sizes and interfaces through an expandable modular signal conversion board. The conversion board integrates multiple key components such as a control signal interface module, a MIPI signal interface module, a power module, a backlight driving circuit, a display screen interface module, and a display signal conversion circuit. These modules work together to not only receive and convert control signals and video signals from different sources, but also adapt to various power requirements and backlight control to ensure the compatibility between signals and different display screens. The display signal conversion circuit is particularly critical, which is responsible for converting MIPI signals into other display interface standards such as LVDS or EDP, so that one mainboard can adapt to multiple displays without redesign, greatly improving flexibility and convenience. The USB-HUB circuit, USB logic circuit and network to USB adapter circuit enhance the expandability and versatility of the conversion board. The USB-HUB circuit allows the access and management of multiple USB devices, while the network to USB adapter circuit enables network devices to be connected to the system through the USB interface. This not only improves the adaptability of electronic devices to different display interfaces, but also shortens the product development cycle, reduces costs, and enables products to quickly respond to market changes and meet diverse display needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0016] Figure 1 One of the circuit schematic diagrams of a control signal interface module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 2 One of the circuit schematic diagrams of a control signal interface module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 3 A second circuit schematic diagram of a signal source interface module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 4 One of the circuit schematic diagrams of a power module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 5 A second circuit schematic diagram of a power module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 6 A third circuit schematic diagram of a power module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 7 A fourth circuit schematic diagram of a power module of an expandable modular signal conversion board provided in an embodiment of the present application; Figure 8 One of the circuit schematic diagrams of a backlight driving circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig. 9 A second circuit schematic diagram of a backlight driving circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.10 A circuit schematic diagram of a display screen interface module of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.11 A circuit schematic diagram of a display signal conversion circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.12 A circuit schematic diagram of a peripheral circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.13 One of the circuit schematic diagrams of a USB-HUB circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.14 A second circuit schematic diagram of a USB-HUB circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.15 One of the circuit schematic diagrams of a USB logic circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.16A second circuit schematic diagram of a USB logic circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.17 A third circuit schematic diagram of a USB logic circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.18 One of the circuit schematic diagrams of a network-to-USB adapter circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.19 A second circuit schematic diagram of a network-to-USB adapter circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig. 20 A third circuit schematic diagram of a network-to-USB adapter circuit of an expandable modular signal conversion board provided in an embodiment of the present application; Fig.21 A schematic diagram of the structure of an expandable modular signal conversion board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0018] See also Figure 1-Figure 21 This embodiment provides an expandable modular signal conversion board to drive display screens of different sizes and interfaces. It can be used with different motherboards to quickly drive displays with different display interfaces.

[0019] The present invention provides an expandable modular signal conversion board, including a control signal interface module, a signal source (MIPI) interface module, a power module, a backlight driving circuit, a display interface module, a display signal conversion circuit, a peripheral circuit, a USB-HUB circuit, a USB logic circuit and a network to USB adapter circuit; The control signal interface module is used to receive signals from a host or other control devices, such as CPU instructions, and convert these control signals into a format suitable for processing by other modules; The signal source (MIPI) interface module is used to receive MIPI signals from the signal source, such as the display output of a smartphone or tablet computer. It also contains the necessary signal conditioning circuits to ensure signal integrity and compatibility.

[0020] The power module provides stable power to the entire converter board, ensuring that all modules can work properly, including voltage regulation and power management functions; The backlight driving circuit is responsible for controlling the backlight of the display screen to ensure the brightness and uniformity of the display effect, and works closely with the display interface module to achieve the best display effect; The display interface module outputs the converted signal to the target display, such as a TV or a car display, and includes signal format conversion and interface adaptation functions to match the requirements of the target display; The display signal conversion circuit is responsible for converting MIPI signals to other display interface standards, such as LVDS or EDP, and contains a digital signal processor (DSP) or a field programmable gate array (FPGA) to handle complex signal conversion.

[0021] Peripheral circuits provide additional functional support, such as signal amplification, filtering, synchronization, etc., including various passive and active components to ensure signal quality and stability.

[0022] The USB-HUB circuit is used to expand the USB interface, provide more connection options, and allow the conversion board to connect multiple USB devices to increase the flexibility of the system.

[0023] The USB logic circuit is used to process USB data transmission and protocol conversion to ensure that the data of the USB device can be correctly transmitted through the conversion board.

[0024] The network to USB adapter circuit converts network signals into USB signals, allowing devices connected via the network to communicate with the conversion board through the USB interface. It contains a network interface card (NIC) and corresponding data processing logic.

[0025] Through the wiring and connectors on the PCB (printed circuit board), the control signal interface module and the signal source interface module pass the signal to the display signal conversion circuit, and then convert the signal into a format suitable for the target display screen. The converted signal is output through the display interface module. At the same time, the power module provides the necessary power for all modules, and the backlight drive circuit adjusts the backlight brightness as needed. The USB-HUB circuit, USB logic circuit and network to USB adapter circuit expand the connection capability and compatibility of the conversion board, enabling it to adapt to more application scenarios. The peripheral circuit provides the necessary signal processing and support throughout the process. This design makes the entire conversion board flexible and scalable, and can adapt to different display devices and application requirements.

[0026] Further, the control signal interface module includes a first chip, a first pin, a seventh pin, a ninth pin, an eleventh pin, a seventeenth pin, a nineteenth pin, a twenty-first pin, a twenty-seventh pin, a twenty-ninth pin, a thirty-fifth pin, a thirty-seventh pin, a thirty-ninth pin and a forty-fifth pin of the first chip are connected to each other and to ground, a second pin, an eighth pin, a fourteenth pin, a sixteenth pin, a twenty-second pin, a twenty-fourth pin, a thirtieth pin, a thirty-second pin, a forty-sixth pin of the first chip are connected to each other and to ground, a third pin of the first chip is connected to USB_DP_HUB, and the USB_DP_HUB is connected to test point TP54, a fifth pin of the first chip is connected to USB_DM_HUB, and the USB_DM_HUB is connected to test point TP53, a forty-seventh pin of the first chip is connected to PMIC_VBUS, and the PMIC_VBUS is connected to test point TP55, and a fourth pin of the first chip is connected to THERM_DCI N is connected, the THERM_DCIN is connected to the ground through the resistor R81, the sixth pin of the first chip is connected to PWEKEY, the PWEKEY is connected to the first pin of the connector J1 through the resistor R86, the second pin of the connector J1 is connected to the ground, the third pin of the connector J1 is connected to the ground through the fourth pin of the connector J1, the thirty-fourth pin of the first chip is connected to the ground through the resistor R78, the forty-second pin of the first chip is connected to THERM_GND, the THERM_GND is connected to the ground through the resistor R185, the forty-fourth pin of the first chip is connected to the ground through the resistor R2, the forty-eighth pin of the first chip is connected to the fiftieth pin of the first chip, the fiftieth pin of the first chip is connected to the forty-seventh pin of the first chip through the forty-ninth pin of the first chip, the fifty-first pin of the first chip is connected to the fifty-second pin of the first chip and then to VDCIN_12V, and the fifty-third pin of the first chip is connected to the fifty-fourth pin of the first chip and then to the ground; The signal source (MIPI) interface module includes a second chip, wherein a first pin, a fifth pin, a ninth pin, a seventeenth pin, a thirty-first pin and a thirty-ninth pin of the second chip are connected and connected to ground, a second pin, an eighth pin, a fourteenth pin, a twentieth pin, a twenty-sixth pin, a thirty-second pin and a fortieth pin of the second chip are connected to each other and connected to ground, a seventh pin of the second chip is connected to GPIO_LCD_EN, an eleventh pin of the second chip is connected to LCD_ID1, and LCD_ID1 is connected to VBUS_SWITCH through a resistor R88, a nineteenth pin of the second chip is connected to S_TE, and S_TE is connected to HUB1_INT through a resistor R83, a twenty-first pin of the second chip is connected to M_TE, and M_TE is connected to HUB2_INT through a resistor R87, a twenty-third pin of the second chip and a twenty-fifth pin of the second chip are connected to each other and connected to VCCIO_1P8, and VCCIO_1P8 is connected to L11_1V8 through a resistor R91, and the resistor R91 is connected to ground through a capacitor C17, and a forty-ninth pin of the second chip is connected to TP_SCL B is connected, the SCL B is connected to one end of the resistor R80 through the resistor R32, one end of the resistor R80 is connected to the intersection of the test point TP56 and TP_SCL, the fourth pin of the second chip is connected to RDN3_B, the sixth pin of the second chip is connected to RDP3_B, the tenth pin of the second chip is connected to RDN2_B, the twelfth pin of the second chip is connected to RDP2_B, the sixteenth pin of the second chip is connected to RCN_B, the eighteenth pin of the second chip is connected to RCP_B, the twenty-second pin of the second chip is connected to RDN1_B, and the second The 24th pin of the chip is connected to RDP1_B, the 28th pin of the second chip is connected to EDN0_B, the 30th pin of the second chip is connected to RDP0_B, the 36th pin of the second chip is connected to DISP_PWM through resistor R96, the 42nd pin of the second chip is connected to TP_RESET_N, the TP_RESET_N is connected to LT9211_RST through resistor R82, the 44th pin of the second chip is connected to DISP_PWM through resistor R97, the 46th pin of the second chip is connected to TP INT, the 50th pin of the second chip is connected to TP_SDA_B, the TP_SDA_B is connected to one end of resistor R79 through resistor R40, one end of the resistor R79 is connected to the junction of test point TP57 and TP SDA, the other end of the resistor R79 is connected to the junction of resistor R80 and L11_1V8, the 51st pin of the second chip is connected to the 52nd pin of the second chip, and then connected to ground,The fifty-third pin of the second chip is connected to the fifty-fourth pin of the second chip, and then connected to the ground. The L11_1V8 is connected to the eighth pin of the chip U8 through the resistor R99, the resistor R99 is also connected to the ground through the capacitor C46, ​​the capacitor C46 is also connected to the ground through the capacitor C89, the TP_SCL is connected to the seventh pin of the chip U8, the TP SDA is connected to the sixth pin of the chip U8, the fifth pin of the chip U8 is connected to the ground, the first pin of the chip U8 is connected to the ground through the capacitor C98, the capacitor C98 is also connected to 3V3, the second pin of the chip U8 is connected to BATT_I2C_SCL, the third pin of the chip U8 is connected to BATT_I2C_SDA, and the fourth pin of the chip U8 is connected to L11_1V8 through the resistor R100; The BATT_I2C_SCL is connected to the tenth pin of the connector J8 through a resistor R113, the BATT_I2C_SDA is connected to the twelfth pin of the connector J8 through a resistor R114, the second pin, the eighth pin, the fourteenth pin and the sixteenth pin of the connector J8 are connected to each other and to the ground, the fourth pin of the connector J8 is connected to VBAT_4V2 through a resistor R89, the resistor R89 ​​is also connected to the sixth pin of the connector J8 through a resistor R92, the seventeenth pin of the connector J8 is connected to the eighteenth pin of the connector J8 and then to the ground, the nineteenth pin of the connector J8 is connected to the twentieth pin of the connector J8 and then to the ground, and the first pin of the connector J8 is connected to the seventh pin of the connector J8 and then to the ground. Specifically, USB_DP_HUB and USB_DM_HUB represent USB differential signal lines for transmitting USB data; PMIC_VBUS represents the power voltage input of the power management integrated circuit (Power Management Integrated Circuit); THERM_DCIN represents the DC input of the thermocouple or temperature sensor; PWEKEY represents the power key, which is used to control the opening and closing of the device; GPIO_LCD_EN represents the enable signal of the general input / output (GPIO) for controlling the LCD; LCD_ID1 represents the identification or selection signal of the LCD; VBUS_SWITCH is used to control the switch of VBUS (USB power bus); HUB1_INT and HUB2_INT represent the interrupt signals of hub 1 and hub 2; VCCIO_1P8 represents I / O voltage, which is 1.8V; DISP_PWM represents the pulse width modulation signal of the display, which is used to control the brightness; LT9211_RST represents the reset signal of the LT9211 chip; TP_SCL_B and TP_SDA_B represent the test points of the clock line and data line of the I2C bus; EDN0_B represents the connection point of the error detection network; BATT_I2C_SCL and BATT_I2C_SDA represent the clock line and data line of the battery I2C communication; VBAT_4V2 represents the battery voltage, which is 4.2V; V3P3_USB represents the 3.3V power supply of the USB port.

[0027] Furthermore, the power module includes a chip U1, a chip U7, a chip U203, a chip U204, a chip U10, a chip U11, a chip U12, a chip U13 and a chip U205. The first pin of the chip U1 is connected to the second pin of the chip U1 through the resistor R4, the second pin of the chip U1 is also connected to one end of the resistor R34, the other end of the resistor R34 is connected to the intersection of the fourth pin of the chip U1 and the resistor R35, and then connected to the ground, one end of the resistor R34 is also connected to the intersection of the third pin of the chip U1 and the resistor R33 through the resistor R29, the resistor R33 is also connected to the ground, the resistor R29 is also connected to the ground through the capacitor C3, the capacitor C3 is also connected to the ground through the capacitor C207, the capacitor C207 is also connected to 24V_ADP, the 24V_ADP is connected to the ground through the diode D107, the diode D107 is also connected to the first pin of the connector J10 through the test point TP4, the second pin, the third pin, the fourth pin, the fifth pin and the sixth pin of the connector J10 are connected to each other and to the ground, The seventh pin of the chip U1 is connected to the ground through the resistor R30, the fifth pin of the chip U1 is connected to the ground, the sixth pin of the chip U1 is connected to the ground through the capacitor C47, the eighth pin of the chip U1 is connected to OVP_PG through the junction of the resistor R28 and the resistor R41, the ninth pin of the chip U1 is connected to the junction of the resistor R28 and the third pin of the chip U6, the tenth pin of the chip U1 is connected to the first pin of the chip U6, the second pin of the chip U6 is also connected to the first pin of the chip U1, the third pin of the chip U6 is also connected to the ground through the capacitor C51, the capacitor C51 is also connected to the ground through C45, the capacitor C45 is also connected to the ground through the capacitor C2, and the capacitor C2 is also connected to the junction of the diode D32 and 24V; The first pin of the chip U7 is connected to the ground through a resistor R102, and the resistor R102 is also connected to OVP_PG through a resistor R36. The resistor R36 is connected to the junction of the seventh pin of the chip U7 and the ninth pin of the chip U7 through a resistor R101. The junction of the seventh pin of the chip U7 and the ninth pin of the chip U7 is also connected to the junction of the capacitor C74 and one end of the capacitor C49. The junction of the capacitor C74 and the other end of the capacitor C49 is connected to the ground. The junction of the capacitor C74 and one end of the capacitor C49 is connected to the ground through a capacitor C4. 8 is connected to the ground, the capacitor C48 is connected to the junction of the capacitor C18 and 24V, the seventh pin of the chip U7 is also connected to the second pin of the chip U7 through the resistor R103, the third pin of the chip U7 is connected to the ground through the resistor R104, and the resistor R104 is also connected to VCC3V through the resistor R106, the tenth pin of the chip U7 is connected to the twelfth pin of the chip U7, the eighth pin of the chip U7 is connected to the junction of the eleventh pin of the chip U7, the inductor L4 and the capacitor C76, and the capacitor C 76 is also connected to the sixth pin of the chip U7, the inductor L4 is also connected to the resistor R108, the resistor R110, the capacitor R77, the capacitor R78, the capacitor R79, the capacitor R73, the capacitor R90 and one end of the test point TP5, the other ends of the capacitors R77, the capacitor R78, the capacitor R79, the capacitor R73 and the capacitor R90 are connected to the ground, the other end of the resistor R110 is connected to one end of the capacitor C81, and one end of the capacitor R90 is also connected to the resistor R94, the resistor R54, the resistor R58, the resistor R62, the resistor R75, the resistor R 76, one end of the resistor R77, the resistor R84 and the resistor R95, the other ends of the resistor R94, the resistor R54, the resistor R58, the resistor R62, the resistor R75 and the resistor R76 are connected to VBAT_4V2, the other ends of the resistor R77, the resistor R84 and the resistor R95 are connected to VDCIN_12V, the fourth pin of the chip U7 is connected to the junction of the resistor R108, the resistor R109 and the other end of the capacitor C81, the fifth pin of the chip U7 is connected to the junction of the capacitor C75 and VCC3V, The first pin of the chip U203 is connected to the intersection of the eighth pin of the chip U203 and the first pin of the inductor L1101 through the capacitor C1109, the second pin of the inductor L1101 is connected to the intersection of the test point TP7 and BUCK5V through the interconnection of one end of the capacitor C1113, the capacitor C1112, the capacitor C20, the capacitor C25 and the capacitor C54, the other ends of the capacitor C1113, the capacitor C1112, the capacitor C20, the capacitor C25 and the capacitor C54 are connected to the ground, the fourth pin of the chip U203 is connected to the connection of the resistor R216 and the resistor R215, the resistor R216 is also connected to the BUCK5V. V is connected, the sixth pin and the ninth pin of the chip U203 are connected to the ground, the fifth pin of the chip U203 is connected to the intersection of the resistor R37, the resistor R217 and the resistor R218, the resistor R37 is also connected to OVP_PG, the resistor R217 is also connected to the seventh pin of the chip U203, the seventh pin of the chip U203 is also connected to the intersection of the capacitor C1108, the capacitor C1104, the capacitor C1114 and one end of the capacitor C82, one end of the capacitor C82 is also connected to 24V, the other ends of the capacitor C1108 and the capacitor C1104 are connected to the ground, the capacitor C1114 and the capacitor C82 are both connected to the ground, The components and connection methods of the chip U204 are the same as those of the chip U203, wherein the differences from the chip U203 include: the fifth pin of the chip U204 is also connected to PMIC_VBUS through a resistor R49, and the BUCK5V is HUB_HOST_VBUS; The components and connection methods of the chip U205 are the same as those of the chip U204, wherein the differences from the chip U204 include: the HUB_HOST_VBUS is VBUS; The first pin of the chip U10 is connected to the ground through the capacitor C68, and the capacitor C68 is also connected to the intersection of the test point TP10 and HUB_HOST_VBUS_1. The second pin of the chip U10 is connected to the ground. The fourth pin of the chip U10 is connected to the fifth pin of the chip U10 through the resistor R23, and the fifth pin of the chip U10 is also connected to the intersection of the capacitor C69 and HUB_HOST_VBUS. The first pin of the chip U11 is connected to the ground through the capacitor C67, and the capacitor C67 is also connected to the intersection of the test point TP11 and HUB_HOST_VBUS_2. The second pin of the chip U11 is connected to the ground. The fourth pin of the chip U11 is connected to the fifth pin of the chip U11 through the resistor R24. The fifth pin of the chip U11 is also connected to the intersection of the capacitor C66 and HUB_HOST_VBUS. The first pin of the chip U12 is connected to the ground through the capacitor C64, and the capacitor C64 is also connected to the intersection of the test point TP12, the capacitor C80 and VBUS_1_1. The second pin of the chip U12 is connected to the ground. The fourth pin of the chip U12 is connected to the fifth pin of the chip U12 through the resistor R50, and the resistor R50 is also connected to USB_EN1. The fifth pin of the chip U12 is also connected to the intersection of the capacitor C62 and VBUS, and the capacitor C62 is also connected to the ground. The first pin of the chip U13 is connected to the ground through the capacitor C65, and the capacitor C65 is also connected to the intersection of the test point TP13, the capacitor C95 and VBUS_1_2. The second pin of the chip U13 is connected to the ground. The fourth pin of the chip U13 is connected to the fifth pin of the chip U13 through the resistor R51. The fourth pin of the chip U13 is also connected to the resistor R145 and USB_EN2 respectively. The fifth pin of the chip U13 is also connected to the intersection of the capacitor C63 and VBUS, and the capacitor C62 is also connected to the ground.

[0028] Specifically, 24V_ADP indicates a 24-volt power adapter output, which is used to power the device; VCC3V indicates a 3-volt power line, which is used to provide operating voltage for logic circuits or certain chips; VBAT_4V2 indicates a 4.2-volt battery power line; VDCIN_12V indicates a 12-volt DC input power line, which is usually used to convert external power to the voltage required by the device; OVP_PG indicates an overvoltage protection signal line, which is used to provide protection when the voltage exceeds the safety threshold; HUB_HOST_VBUS indicates the VBUS power line of the hub or host, which is used to provide power to the USB hub or host port; HUB_HOST_VBUS_1 and HUB_HOST_VBUS_2 are used to distinguish the VBUS power lines of different hubs or host ports, and the numbers may indicate different power channels or physical connections; VBUS_1_1 and VBUS_1_2 represent two different VBUS power lines, which are used to power different devices or circuit parts; VBUS represents the VBUS power line identifier, which is used for the USB interface to provide power to the connected device; USB_EN1 and USB_EN2 represent USB enable signal lines, which are used to control the power switch of the USB interface.

[0029] Furthermore, the backlight driving circuit includes a chip U15, a first pin of the chip U15 is connected to a feedback terminal FB1, a thirteenth pin of the chip U15 is connected to a feedback terminal FB2, a fourteenth pin of the chip U15 is connected to a feedback terminal FB3, a sixteenth pin of the chip U15 is connected to a feedback terminal FB4, a seventh pin of the chip U15 is connected to a junction of a resistor R26 and a fourth pin of the chip U4 through a resistor R22, a sixth pin of the chip U15 is connected to a junction of a resistor R26, a third pin of the chip U4, a second pin of the chip U4, a first pin of the chip U4 and a resistor R17 through a resistor R25, the resistor R17 is also connected to ground, and an eighth pin of the chip U15 is connected to a ground. The capacitor C70 is connected to the ground, and the capacitor C70 is also connected to VCC. The fifteenth pin and the seventeenth pin of the chip U15 are both connected to the ground. The fifth pin, the seventh pin, the sixth pin and the eighth pin of the chip U4 are mutually connected at the intersection of the diode D11, the diode D6 and one end of the inductor L3. The intersection of the diode D6 and the other end of the inductor L3 is connected to the intersection of the resistor R20, the capacitor C72, the capacitor C71, the capacitor C50 and one end of the capacitor C83. One end of the capacitor C83 is also connected to LCD_LED. The intersection of the capacitor C72, the capacitor C71, the capacitor C50 and the other end of the capacitor C83 is connected to the ground. The third pin of the chip U4 is connected to the intersection of the resistor R20 and the resistor R21. The resistor R21 is also connected to the ground, the ninth pin of the chip U15 is connected to the intersection of the resistor R27 and the capacitor C22, the resistor R27 is also connected to the intersection of the inductor L3, the capacitor C40, the capacitor C23, the capacitor C28, the capacitor C91 and 24V, the capacitor C28 and the capacitor C91 are both connected to the ground, the capacitor C40 and the capacitor C23 are also connected to the ground, the tenth pin of the chip U15 is also connected to the intersection of the resistor R43, the resistor R19 and one end of the capacitor C11, the other end of the resistor R19 and the capacitor C11 intersects with the ground, the other end of the resistor R43 is connected to VCC, and the fifth pin of the chip U15 is also connected to the intersection of the resistor R119 and one end of the resistor R120 , the other end of the resistor R119 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to the junction of one end of the resistor R117 and 3V3, the other end of the resistor R117 is connected to the junction of the base of the transistor Q3 and the resistor R118, the resistor R118 is also connected to the collector of the transistor Q2, the emitter of the transistor Q2 is connected to the ground, the base of the transistor Q2 is connected to GPIO_LCD_EN, the twelfth pin of the chip U15 is connected to the junction of the resistor R56 and BL_PWM, the second pin of the chip U15 is connected to the ground through the resistor R42, the eleventh pin of the chip U15 is connected to the capacitor C1 through the resistor R38, and the capacitor C1 is also connected to the ground,The fourth pin of the chip U15 is connected to the ground through a resistor R39; The feedback terminal FB1 is also connected to the intersection of the sixth pin of the connector J6, the test point TP22 and the protection diode VR6, the feedback terminal FB4 is also connected to the intersection of the fifth pin of the connector J6, the test point TP21 and the protection diode VR2, the feedback terminal FB3 is also connected to the intersection of the second pin of the connector J6, the test point TP19 and the protection diode VR7, the feedback terminal FB2 is also connected to the intersection of the first pin of the connector J6, the test point TP18 and the protection diode VR5, the LCD_LED is also connected to the intersection of the second pin of the connector J6, the third pin of the connector J6 and the test point TP20, the seventh pin of the connector J6 and the eighth pin of the connector J6 are connected to the ground; The BL_PWM is connected at the connection between the resistor R1509 and the resistor R1517, the resistor R1517 is also connected to the collector of the transistor Q1502, the emitter of the transistor Q1502 is connected to the intersection of one end of the resistor R1529 and 3V3, the other end of the resistor R1529 is connected to the intersection of the base of the transistor Q1502 and the resistor R1530, the resistor R1530 is also connected to the collector of the transistor Q1501, the emitter of the transistor Q1501 is connected to the ground, and the base of the transistor Q1501 is connected to DISP_PWM.

[0030] Specifically, GPIO_LCD_EN is an input / output (GPIO) pin used to enable or disable the LCD display. It is a control signal used to turn on or off the LCD display function; BL_PWM is another PWM control signal used to adjust the brightness of the backlight.

[0031] Further, the display screen interface module includes a connector J20, a filter EMI5, a filter EMI6, a filter EMI7, a filter EMI8 and a filter EMI9, a first pin of the connector J20 is connected to DN0_TXA through a resistor R147, a third pin of the connector J20 is connected to DN1_TXA through a resistor R50, a fifth pin of the connector J20 is connected to DN2_TXA through a resistor R153, a seventh pin of the connector J20 is connected to the seventeenth pin of the connector J20 and is connected to ground, The ninth pin of the connector J20 is connected to CLKP_TXA through a resistor R154, the eleventh pin of the connector J20 is connected to DN3_TXA through a resistor R156, the thirteenth pin of the connector J20 is connected to DP0_TXB through a resistor R158, the fifteenth pin of the connector J20 is connected to DN1_TXB through a resistor R160, the nineteenth pin of the connector J20 is connected to DP2_TXB through a resistor R161, the twenty-first pin of the connector J20 is connected to CLKP_TXB through a resistor R162, the twenty-third pin of the connector J20 is connected to DP3_TXB through a resistor R163, the twenty-ninth pin of the connector J20 is connected to BUCK5V, and the intersection of the thirty-first pin and the thirty-second pin of the connector J20 is connected to ground. The second pin of the connector J20 is connected to DP0_TXA through a resistor R148, the fourth pin of the connector J20 is connected to DP1_TXA through a resistor R149, the sixth pin of the connector J20 is connected to DO2_TXA through a resistor R151, the eighth pin of the connector J20 is connected to CLKN_TXA through a resistor R152, the tenth pin of the connector J20 is connected to DP3_TXA through a resistor R155, the twelfth pin of the connector J20 is connected to DN0_TXB through a resistor R157, and the connector The fourteenth pin and the twenty-fourth pin of the connector J20 are connected to each other and to ground, the sixteenth pin of the connector J20 is connected to DP1_TXB through a resistor R159, the eighteenth pin of the connector J20 is connected to DN2_TXB through a resistor R169, the twentieth pin of the connector J20 is connected to CLKN_TXB through a resistor R170, the twenty-second pin of the connector J20 is connected to DN3_TXB through a resistor R171, and the twenty-eighth pin and the thirtieth pin of the connector J20 are connected to each other and to BUCK5V; The first pin of the filter EMI5 is connected to the intersection of RDN2_B and one end of the resistor R65, the second pin of the filter EMI5 is connected to the intersection of RDP2_B and one end of the resistor R64, the third pin of the filter EMI5 is connected to the intersection of DSI0_LANE2_P and the other end of the resistor R64, and the fourth pin of the filter EMI5 is connected to the intersection of DSI0_LANE2_N and the other end of the resistor R65; The first pin of the filter EMI6 is connected to the intersection of RDN0_B and one end of the resistor R68, the second pin of the filter EMI6 is connected to the intersection of RDP0_B and one end of the resistor R67, the third pin of the filter EMI6 is connected to the intersection of DSI0_LANE0_P and the other end of the resistor R67, and the fourth pin of the filter EMI6 is connected to the intersection of DSI0_LANE0_N and the other end of the resistor R68; The first pin of the filter EMI7 is connected to the intersection of RCN_B and one end of the resistor R69, the second pin of the filter EMI7 is connected to the intersection of RCP_B and one end of the resistor R70, the third pin of the filter EMI7 is connected to the intersection of DSI0_CLK_P and the other end of the resistor R70, and the fourth pin of the filter EMI7 is connected to the intersection of DSI0_CLK_N and the other end of the resistor R69; The first pin of the filter EMI8 is connected to the intersection of RDN1_B and one end of the resistor R71, the second pin of the filter EMI8 is connected to the intersection of RDP1_B and one end of the resistor R72, the third pin of the filter EMI8 is connected to the intersection of DSI0_LANE1_P and the other end of the resistor R72, and the fourth pin of the filter EMI8 is connected to the intersection of DSI0_LANE1_N and the other end of the resistor R71; The first pin of the filter EMI9 is ​​connected to the intersection of RDN3_B and one end of the resistor R74, the second pin of the filter EMI9 is ​​connected to the intersection of RDP3_B and one end of the resistor R73, the third pin of the filter EMI9 is ​​connected to the intersection of DSI0_LANE3_P and the other end of the resistor R73, and the fourth pin of the filter EMI9 is ​​connected to the intersection of DSI0_LANE3_N and the other end of the resistor R74.

[0032] Specifically, DNx_TXA / DNx_TXB, DPx_TXA / DPx_TXB, these identifiers represent different data signal channels, where "DN" represents the negative data line, "DP" represents the positive data line, "TXA" and "TXB" represent different channels or groups; CLKP_TXA / CLKP_TXB, CLKN_TXA / CLKN_TXB represent clock signal lines, where "CLKP" and "CLKN" represent the positive and negative polarities of the clock signal, respectively, and "TXA" and "TXB" also represent different channels or groups; DSI0_LANEx_P / DSI0_LANEx_N represents the Display Serial Interface, The data channel of DSI (DSI), where "P" and "N" represent the positive and negative data lines respectively, and "x" represents the channel number; RDNx_B / RDPx_B, RCN_B / RCP_B represent the resistor connections related to the DSI interface, which are used for signal matching or impedance control; BUCK5V refers to a 5-volt buck converter output, which provides a stable 5V power supply for the circuit; RDx, RDPx represent the resistors related to the DSI interface, which are used for signal impedance matching or signal conditioning.

[0033] Through this carefully designed circuit layout, the display interface module achieves efficient and stable data transmission and signal control. At the same time, the integrated EMI filter effectively reduces electromagnetic interference, ensuring signal integrity and circuit reliability. The combined use of connector J20 and multiple filters EMIx provides a solid foundation for high-speed data communication and supports complex display technology requirements such as MIPI and DSI interfaces, so that display devices can operate stably with high resolution and high refresh rate, improve user experience, and ensure compatibility and scalability with various display technologies.

[0034] Further, the display signal conversion circuit includes a chip U17, a first pin of the chip U17 is connected to the intersection of VDD, the fifteenth pin of the chip U17 and the thirty-fifth pin of the chip U17, a twelfth pin of the chip U17 is connected to the intersection of VCC18_RX and the sixty-fourth pin of the chip U17, a thirteenth pin of the chip U17 is connected to the intersection of the resistor R90, the capacitor C93 and the first pin of the chip U18, the capacitor C93 is also connected to the ground, a second pin of the chip U18 and a fourth pin of the chip U18 are connected to the ground, and a third pin of the chip U18 is connected to the intersection of the capacitor C124, the resistor R90 and the fourteenth pin of the chip U17 , the twenty-fourth pin of the chip U17 is connected to the thirty-seventh pin of the chip U17 and to VCCIO, the twenty-fifth pin of the chip U17 is connected to DP3_TXB, the twenty-sixth pin of the chip U17 is connected to DN3_TXB, the twenty-seventh pin of the chip U17 is connected to CLKP_TXB, the twenty-eighth pin of the chip U17 is connected to CLKN_TXB, the twenty-ninth pin of the chip U17 is connected to DP2_TXB, the 30th pin of the chip U17 is connected to DN2_TXB, the thirty-first pin of the chip U17 is connected to DP1_TXB, and the thirty-second pin of the chip U17 is connected to DN1_TXB, The thirty-third pin of the chip U17 is connected to DN0_TXB, the thirty-fourth pin of the chip U17 is connected to DP0_TXB, the thirty-sixth pin of the chip U17 is connected to VCC18_TX, the thirty-seventh pin of the chip U17 is connected to VCCIO, the thirty-eighth pin of the chip U17 is connected to DP3_TXA, the thirty-ninth pin of the chip U17 is connected to DN3_TXA, the fortieth pin of the chip U17 is connected to CLKP_TXA, the forty-first pin of the chip U17 is connected to CLKN_TXA, the forty-second pin of the chip U17 is connected to DP2_TXA, the forty-third pin of the chip U17 is connected to DN2_TXA, the forty-fourth pin of the chip U17 is connected to DP1_TXA, the forty-fifth pin of the chip U17 is connected to DN1_TXA, the forty-sixth pin of the chip U17 is connected to DN0_TXA, and the forty-eighth pin of the chip U17 is connected to VCC18, The 49th pin of the chip U17 is connected to the junction of LT9211_RST, resistor R31 and capacitor C21, the capacitor C21 is also connected to the ground, the resistor R31 is also connected to VCC18, the 50th pin of the chip U17 is connected to TP_SDA, the 51st pin of the chip U17 is connected to TP_SCI, the 52nd pin of the chip U17 is connected to TP_INT through resistor R112, the 53rd pin of the chip U17 is connected to DSI0_LANE3_N, the 54th pin of the chip U17 is connected to DSI0_LANE3_P, the 55th pin of the chip U17 is connected to DSI0_LANE2_N, and the 50th pin of the chip U17 is connected to DSI0_LANE3_V The 56th pin of the chip U17 is connected to DSI0_LANE2_P, the 57th pin of the chip U17 is connected to DSI0_CLK_N, the 58th pin of the chip U17 is connected to DSI0_CLK_P, the 59th pin of the chip U17 is connected to DSI0_LANE1_N, the 60th pin of the chip U17 is connected to DSI0_LANE1_P, the 61st pin of the chip U17 is connected to DSI0_LANE0_N, the 62nd pin of the chip U17 is connected to DSI0_LANE0_P, the 63rd pin of the chip U17 is connected to the 65th pin of the chip U17 through the resistor R93, and the 65th pin of the chip U17 is also connected to ground; The VDD is also connected to the junction of one end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206, and the other end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206 is connected to the ground. The VCC18_RX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. The VCC18_TX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. It is connected to the intersection of one end of capacitor C210 and capacitor C227, and the other end of the intersection of capacitor C210 and capacitor C227 is connected to the ground. The VCCIO is also connected to the intersection of one end of capacitor C176, capacitor C178 and capacitor C179, and the other end of the intersection of capacitor C176, capacitor C178 and capacitor C179 is connected to the ground. The VCC18 is also connected to the intersection of one end of capacitor C58 and capacitor C97, and the other end of the intersection of capacitor C58 and capacitor C97 is connected to the ground.

[0035] Specifically, VCC18_RX, VCC18_TX, VCCIO, and VCC18 represent power lines with different functions, such as receiving (RX), transmitting (TX), and I / O voltage (VCCIO), which are used to provide stable voltages for different parts of the chip; TP_SDA, TP_SCL, and TP_INT represent test point identifiers for debugging and testing; DSI0_LANEx_N / P represents the data line of the Display Serial Interface (DSI), where "N" and "P" represent the negative and positive data lines, respectively; DPx_TXB / A, DNx_TXB / A, CLKP_TXB / A, and CLKN_TXB / A represent data and clock signals of different channels for transmitting display data; LT9211_RST is a reset signal used to reset or initialize the LT9211 chip.

[0036] The display signal conversion circuit achieves precise signal management and power control through chips U17 and U18 and related power, ground, resistor and capacitor configurations, ensuring signal integrity and circuit stability. This design supports high-speed data transmission and is suitable for complex display interfaces such as DSI and DP. At the same time, it achieves signal filtering and decoupling through a sophisticated resistor and capacitor network, reducing electromagnetic interference and improving signal quality. In addition, by connecting multiple test points, it is easy to perform system debugging and performance optimization, ensuring the reliability and efficient operation of the display signal conversion circuit.

[0037] Further, the peripheral circuit includes a chip U49, a first pin of the chip U49 is connected to the intersection of the fourth pin of the chip U49, the capacitor C224, the capacitor C215 and the BUCK5V through a resistor R144, the capacitor C224 and the capacitor C215 are also connected to the ground, the second pin of the chip U49 is connected to the ground, the third pin of the chip U49 is connected to the intersection of the resistor R107, the capacitor C397, the capacitor C216, the resistor R57 and one end of the protection diode VR3 through an inductor L84, one end of the protection diode VR3 is also connected to VDD, the other end of the resistor R57 is connected to L11_1V8, the capacitor C397, the capacitor C216 and the other end of the protection diode VR3 are all connected to the ground, the fifth pin of the chip U49 is connected to the intersection of the other end of the resistor R107 and one end of the resistor R105, and the other end of the resistor R105 is connected to the ground; The VDD is connected to the intersection of resistor B4, resistor B5, resistor B12, resistor B1, protection diode VR1 and one end of VDD_1V8 through resistor B10, the other end of the resistor B4 is connected to VCC18_RX, the other end of the resistor B5 is connected to VCC18_TX, the other end of the resistor B12 is connected to VCCIO, the other end of the resistor B1 is connected to VCC18, and the other end of the protection diode VR1 is connected to ground.

[0038] Specifically, the peripheral circuit design forms a complex power management and signal conditioning network through chip U49 and its supporting resistors, inductors, capacitors and protection diodes. This design not only ensures a stable power supply, providing the required 5V voltage to chip U49 through BUCK5V, but also achieves the filtering of power supply noise and the maintenance of signal integrity through fine resistor and capacitor configuration. The use of inductor L84 further stabilizes the current supply, while protection diode VR3 helps smooth voltage fluctuations on the power line. At the same time, the distribution of VDD ensures stable power supply in different voltage domains through multiple resistors and protection diode VR1, which is essential to maintain the reliability of the circuit and improve signal quality. Overall, this design improves the anti-interference ability of the circuit, ensures clear signal transmission, and provides a solid foundation for high-performance electronic devices.

[0039] Further, the USB-HUB circuit includes a chip U2 and a chip U23, the first pin of the chip U2 is respectively connected to the fifth pin of the chip U2 and the tenth pin of the chip U2, the first pin of the chip U2 is also connected to the intersection of capacitor C6, capacitor C7 and one end of resistor B20, the other end of the resistor B20 is connected to the intersection of the sixteenth pin of the chip U2, the twenty-fourth pin of the chip U2, capacitor C8, capacitor C9 and one end of VCC_3V3, the other ends of the capacitors C6, C7, C8 and C9 are mutually connected to the ground, the sixth pin of the chip U2 is connected to 12MHZ_OSC_IN1, the seventh pin of the chip U2 is connected to 12MHZ_OSC_OUT1, the seventeenth pin of the chip U2 is connected to VCC_3V3 through a resistor R164, the fourteenth pin of the chip U2 is connected to the ground through a resistor R165, the thirteenth pin of the chip U2 is connected to resistor R167, capacitor C10, At the junction of one end of the resistor R166, the other end of the resistor R166 is connected to VCC_3V3, the other ends of the resistor R167 and the capacitor C10 are connected to the ground, the twenty-fifth pin of the chip U2 is connected to USB_DM_HUB, the seventh and twenty-sixth pins of the chip U2 are connected to USB_DP_HUB, the fourth pin of the chip U2 is connected to the ground through the resistor R168, the fifteenth pin of the chip U2 is connected to the ground, the eighteenth pin of the chip U2 is connected to the junction of the resistor R173 and VCC_3V3 through the resistor R172, the resistor R173 is also connected to the twenty-first pin of the chip U2, the twelfth pin of the chip U2 is connected to the first pin of the filter EMI22, the eleventh pin of the chip U2 is connected to the second pin of the filter EMI22, the third pin of the filter EMI22 is connected to HUB_HOST1_DM4, and the fourth pin of the filter EMI22 is connected to HUB_HOST1_DP4; The ninth pin of the chip U2 is connected to the first pin of the filter EMI21, the eighth pin of the chip U2 is connected to the second pin of the filter EMI21, the third pin of the filter EMI21 is connected to HUB_HOST1_DM2, the fourth pin of the filter EMI21 is connected to HUB_HOST1_DP2, the third pin of the chip U2 is connected to the first pin of the filter EMI20, the second pin of the chip U2 is connected to the second pin of the filter EMI20, the third pin of the filter EMI20 is connected to LAN_USB_DM, the fourth pin of the filter EMI20 is connected to LAN_USB_DP, the twenty-eighth pin of the chip U2 is connected to the first pin of the filter EMI19, the twenty-seventh pin of the chip U2 is connected to the second pin of the filter EMI19, the third pin of the filter EMI19 is connected to TP_USB_DM, and the fourth pin of the filter EMI19 is connected to TP_USB_DP; The first pin of the chip U23 is connected to the junction of capacitor C269 and 12MHZ_OSC_OUT1, and the capacitor C269 is also connected to the ground. The second pin of the chip U23 and the fourth pin of the chip U23 are both connected to the ground. The third pin of the chip U23 is connected to the junction of capacitor C32 and 12MHZ_OSC_IN1, and the capacitor C32 is also connected to the ground.

[0040] Specifically, 12MHZ_OSC_IN1 and 12MHZ_OSC_OUT1 represent the input and output pins of a 12MHz crystal or clock oscillator, which are used to provide a clock signal for chip U2; USB_DM_HUB and USB_DP_HUB represent USB differential signal lines for transmitting USB data, "DM" represents differential negative, and "DP" represents differential positive; HUB_HOST1_DM4, HUB_HOST1_DP4, HUB_HOST1_DM2, HUB_HOST1_DP2 represent the differential signal lines of the host or hub connected to the USB-HUB; LAN_USB_DM and LAN_USB_DP represent the USB differential signal lines connected to the network interface; TP_USB_DM and TP_USB_DP represent the USB differential signal lines on the test point, which are used for debugging and testing.

[0041] The USB-HUB circuit design achieves efficient USB signal management and electromagnetic interference suppression through chips U2 and U23 and matching resistors, capacitors and filters. This design not only ensures the stability and reliability of USB data transmission, but also enhances the compatibility and scalability of the entire system through precise clock signal distribution (provided by 12MHz_OSC_IN1 and 12MHz_OSC_OUT1) and power management (provided by VCC_3V3). The application of filters EMI22, EMI21, EMI20 and EMI19 further reduces electromagnetic interference and protects data integrity, while the close collaboration between chips U2 and U23 optimizes the performance of the USB port, enabling multiple USB devices to work together efficiently and improve overall system performance.

[0042] Furthermore, the USB logic circuit includes a connector J19, a connector J7, a chip U19, a connector J58, a chip U14, a chip 16, a connector J96 and a connector 21. The B1 pin of the connector J19 and the B12 pin of the connector J19 are connected to the ground, the B4 pin of the connector J19 is connected to the B9 pin of the connector J19 and the A9 pin of the connector J19, the B5 pin of the connector J19 is connected to the intersection of USB_CC2, the protection diode T11 and the test point TP44, the B6 pin of the connector J19 and the A6 pin of the connector J19, the A6 pin of the connector J19 is also connected to the intersection of the protection diode T3, the test point TP37 and USB_DP1, the B7 pin of the connector J19 and the A7 pin of the connector J19, the A7 pin of the connector J19 is also connected to the intersection of the protection diode T4, the test point TP36 and USB_DM1, and the protection diode T3 and the protection diode T4 are also connected to the ground; The A1 pin of the connector J19 and the A12 pin of the connector J19 are connected to the ground, the A4 pin of the connector J19 is connected to the junction of the capacitor C88, the third pin of the transistor D3, the test point 38 and VBUS_1_1 through the resistor R111, the capacitor C88, the first pin of the transistor D3 and the second pin of the transistor D3 are connected to the ground, and the A5 pin of the connector J19 is connected to the junction of USB1_CC1 and the protection diode T12; The connector J7 is different from the connector J19, specifically: the B4th pin of the connector J7 is also connected to the A4th pin of the connector J7; The NC pin of the chip U19 is connected to the ground through the capacitor C92, the VSS pin of the chip U19 is connected to the ground, the VOUT pin of the chip U19 is connected to the junction of the capacitor C94 and 3V3, the VN pin of the chip U19 is connected to the junction of the resistor R53, the capacitor C61 and one end of BUCK5V, and the other end of the capacitor C61 is connected to the ground; The components and connection methods on the left and right sides of the connector J58 are consistent, wherein the contents on the left side of the connector J58 include: the first pin of the connector J58 is connected to the intersection of the capacitor C84, the test point TP30, the third pin of the transistor D2 and HUB_HOST_VBUS_2 through the resistor R122, the first pin of the transistor D2 and the second pin of the transistor D2 are mutually connected to the intersection of the capacitor C84 and the ground, the second pin of the connector J58 is connected to the intersection of the test point TP31, the protection diode T2 and HUB_HOST1_DM2, the third pin of the connector J58 is connected to the intersection of the test point TP32, the protection diode T1 and HUB_HOST1_DP2, the fourth pin and the eighth pin of the connector J58 are both connected to the ground, the ninth pin and the tenth pin of the connector J58 are mutually connected to the ground, and the eleventh pin and the twelfth pin of the connector J58 are mutually connected to the ground; The first pin of the chip U14 is connected to USB1_CC1 through a resistor R140, the second pin of the chip U14 is connected to USB1_CC2 through a resistor R139, the third pin of the chip U14 is connected to 3V3 through a resistor R133, the fourth pin of the chip U14 is connected to VBUS_1_1 through a resistor R138, the fifth pin of the chip U14 is connected to ground, the sixth pin of the chip U14 is connected to the junction of HUB1_INT and resistor R137, the resistor R137 is also connected to L11_1V8, the seventh ... seventh pin of the chip U14 is connected to 3V3 through a resistor R133, the fourth pin of the chip U14 is connected to VBUS connected to TP_SDA, the eighth pin of the chip U14 is connected to TP_SCI through a resistor R60, the ninth pin of the chip U14 is connected to the junction of the base of the transistor and the resistor R130, the emitter of the transistor is connected to the ground, the collector of the transistor is connected to the junction of the resistor R143 and USB_EN1, the tenth pin of the chip U14 is connected to the ground, the eleventh pin of the chip U14 is connected to the ground through a resistor R59, the twelfth pin of the chip U14 is connected to the junction of the resistor R130, the resistor R143, the capacitor C60 and 3V3, and the capacitor C60 is also connected to the ground; The difference between the chip 16 and the chip 14 is that the fifth pin of the chip 16 is connected to 3V3 via a resistor R52; The first pin of the connector J96 is connected to the intersection of the test point TP25, the protection diode MLV3 and TP_USB_DM, the second pin of the connector J96 is connected to the intersection of the test point TP24, the protection diode MLV1 and TP_USB_DP, the protection diode MLV3 and the protection diode MLV1 are also connected to the ground, the third pin of the connector J96 is respectively connected to the test point TP26, the fifth pin of the connector J96 and the ground, the fourth pin of the connector J96 is connected to the intersection of the capacitor C85, the test point TP23, the third pin of the transistor D5 and HUB_HOST_VBUS through the resistor R124, the second pin of the transistor D5 and the first pin of the transistor D5 are connected to the capacitor C85 and then to the ground, and the sixth pin and the seventh pin of the connector J96 are mutually connected to the ground; The first pin of the connector 21 is connected to the intersection of the protection diode VR4, the test point TP2, the capacitor C14 and one end of the resistor R44, the other ends of the protection diode VR4 and the capacitor C14 are connected to the ground, and the other end of the resistor R44 is connected to PWRKEY.

[0043] Specifically, USB_CC2, USB1_CC1, and USB1_CC2 represent configuration channels of USB connections, which are used for detecting and configuring the USB connection status; L11_1V8 is an identifier of a 1.8 volt power line, which provides power for low-power circuits.

[0044] The USB logic circuit design achieves stable and reliable USB data transmission and power management through carefully laid out connectors, chips and protection components. This design not only provides efficient power distribution and signal integrity protection, but also reduces electromagnetic interference through integrated protection diodes and filters, enhancing the system's anti-interference ability. At the same time, the setting of test points facilitates debugging and maintenance, ensures the flexibility of the USB interface and the compatibility of the equipment, and improves the stability and reliability of the overall system.

[0045] Furthermore, the network-to-USB adapter circuit includes a chip U21, a chip U46, a connector J2 and a chip U103. The first pin of the chip U21 is connected to the junction of capacitor C139, capacitor C5 and VDD33_PHY, the second pin of the chip U21 is connected to TXOP, the third pin of the chip U21 is connected to TXOH, the fourth pin of the chip U21 is connected to RXIP, the fifth pin of the chip U21 is connected to RXIN, the sixth pin of the chip U21 is connected to ground, the seventh pin of the chip U21 is connected to LAN_USB_DM, the eighth pin of the chip U21 is connected to LAN_USB_DP, and the The ninth pin is connected to the junction of capacitor C135 and VDD10_PHY, the tenth pin of the chip U21 is connected to the junction of capacitor C136, capacitor C131 and VDD33_PHY, the capacitor C136 and capacitor C131 are also connected to the ground, the eleventh pin of the chip U21 is connected to VDD5_PHY, the twelfth pin of the chip U21 is connected to the junction of capacitor C132 and one end of capacitor C134, the other ends of C132 and C134 are connected to the ground, the thirteenth pin of the chip U21 is connected to the junction of capacitor C141 and V The fourteenth pin of the chip U21 is connected to the intersection of the resistor R183, the resistor R184 and VDD33_PHY through the resistor R1, the resistor R183 is also connected to the eighteenth pin of the chip U21, the resistor R184 is also connected to the nineteenth pin of the chip U21, the fifteenth pin of the chip U21 is connected to VDD33_PHY, the sixteenth pin of the chip U21 is connected to the intersection of the capacitor C142 and VDD10_PHY, the seventeenth pin of the chip U21 is connected to LED1_SPEED_Y The 21st pin of the chip U21 is connected to 25MHZ_OSC_OUT, the 22nd pin of the chip U21 is connected to 25MHZ_OSC_IN, the 23rd pin of the chip U21 is connected to the junction of capacitor C143, capacitor C144 and one end of resistor R66, the other ends of capacitor C143 and capacitor C144 are connected to ground, the other end of resistor R66 is connected to VDD10_PHY, the 24th pin of the chip U21 is connected to ground through resistor R85, and the 25th pin of the chip U21 is connected to ground. The VDD33_PHY is connected to the junction of the resistor R134 and one end of the resistor R9, the other end of the resistor R134 is connected to LED1_SPEED_Y through the diode D9, and the other end of the resistor R9 is connected to LED0_LINK_G through the diode D10; The LAN_USB_DM is connected to the test point TP15, the LAN_USB_DP is connected to the test point TP16; the VDD5_PHY is connected to the test point TP17; The first pin of the chip U46 is connected to the junction of the capacitor C484 and 25MHZ_OCS_OUT, and the capacitor C484 is also connected to the ground. The second pin of the chip U46 and the fourth pin of the chip U46 are both connected to the ground. The third pin of the chip U46 is connected to the junction of the capacitor C485 and 25MHZ_OCS_IN, and the capacitor C485 is also connected to the ground. The VDD5_PHY is connected to the junction of the resistor R182, the capacitor C4 and one end of the capacitor C42, the other ends of the capacitor C4 and the capacitor C42 are connected to the ground, and the other end of the resistor R182 is connected to HUB_HOST_VBUS; The first pin of the connector J2 is connected to the connection between the protection diode MLV4, the test point TP51 ​​and one end of TXP, the second pin of the connector J2 is connected to the connection between the protection diode MLV2, the test point TP50 and one end of TXN, the third pin of the connector J2 is connected to the connection between the protection diode MLV6, the test point TP41 and one end of RXP, the fourth pin of the connector J2 and the fifth pin of the connector J2 are connected to each other to form a terminal T45, the fifth pin of the connector J2 is also connected to the connection between the protection diode MLV5 and one end of the terminal T45, and the sixth pin of the connector J2 is connected to the protection diode MLV5 and one end of the terminal T45. Connected to the connection of the protection diode MLV8, the test point TP39 and one end of RXN, the seventh pin of the connector J2 and the eighth pin of the connector J2 are connected to each other to form a terminal T78, the eighth pin of the connector J2 is also connected to the protection diode MLV7, the other ends of the protection diodes MLV4, MLV2, MLV6, MLV5, MLV8 and MLV7 are connected to each other and to the ground, and the ninth pin of the connector J2 is connected to the intersection of the tenth pin of the connector J2, the test point TP52 and EARTH_GND; The first pin of the chip U103 is connected to RXIP, the second pin of the chip U103 is connected to RXIN, the third pin of the chip U103 is connected to ground through a capacitor C44, the seventh pin of the chip U103 is connected to TXOP, the eighth pin of the chip U103 is connected to TXON, the sixth pin of the chip U103 is connected to ground through a capacitor C43, the ninth pin of the chip U103 is connected to TXN, the tenth pin of the chip U103 is connected to TXP, and the eleventh pin of the chip U103 is connected to The resistor R5, the resistor R6, the resistor R136 and one end of the capacitor C506 intersect, the other end of the capacitor C506 is connected to the intersection of the capacitor C502, the resistor R7 and one end of EARTH_GND, the other ends of the capacitor C502 and the resistor R7 are connected to the ground, the other end of the resistor R6 is connected to the terminal T78, the other end of the resistor R136 is connected to the terminal T45, the other end of the resistor R5 is connected to the fourteenth pin of the chip U103, the fifteenth pin of the chip U103 is connected to RXN, and the sixteenth pin of the chip U103 is connected to RXP.

[0046] Specifically, TXOP, TXOH, RXIP, and RXIN represent signal lines in network communications, where "TX" usually refers to transmit, "RX" refers to receive, and "OP" and "OH" may represent specific states or levels of the signal; VDD33_PHY, VDD10_PHY, and VDD5_PHY represent power lines of different voltage levels, which provide the required power supply voltage for chip U21; LED1_SPEED_Y and LED0_LINK_G represent LED lights used to indicate the network connection status and data transmission rate; 25MHZ_OSC_OUT and 25MHZ_OSC_IN represent the output and input pins of the crystal oscillator or clock oscillator, which provide clock signals for network communication; EARTH_GND represents the ground wire or reference ground of the circuit.

[0047] Through the PCB circuit board, different display signals are bridged, for example, the motherboard display signal (MIPI) of the flat panel display product is converted into the driving signal of the TV display product (LVDS). Or the MIPI display signal is converted into the EDP display signal.

[0048] In this embodiment, the PCB circuit board of the present invention can bridge different display signals, such as converting the mainboard display signal (MIPI) of a flat panel display product into a driving signal of a TV display product (LVDS), or converting the MIPI display signal into an EDP display signal. This modular design allows for rapid adaptation of displays with different mainboards and display interfaces, greatly reducing hardware development time and product development cycle, and improving development efficiency. In addition, the modular signal conversion board of the present invention has a high degree of scalability and can drive display screens of different sizes and interfaces, so that the mainboard originally applied to one product can be directly used for another product, such as directly using the mainboard of a flat panel product for commercial TV products. The present invention is compatible with different interface conversions, is easy and fast to use, has a short development cycle, and can be used with different mainboards to convert and modify products that have been designed and mass-produced, which not only improves the compatibility and flexibility of electronic products, but also reduces development costs and time, providing electronic equipment manufacturers with a solution that can quickly respond to market changes.

[0049] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An expandable modular signal conversion board, characterized in that: It includes a control signal interface module, a signal source interface module, a power module, a backlight driving circuit, a display interface module, a display signal conversion circuit, a USB-HUB circuit, a USB logic circuit and a network to USB adapter circuit; The control signal interface module is used to receive signals from a host or other control devices; The signal source interface module is used to receive the MIPI signal from the signal source; The power module provides power to the conversion board; The backlight driving circuit is responsible for controlling the backlight of the display screen; The display screen interface module outputs the converted signal to the target display screen; The display signal conversion circuit converts the MIPI signal into other display interface standards; The USB-HUB circuit is used to expand the USB interface, allowing the conversion board to connect multiple USB devices; The USB logic circuit is used to process USB data transmission and protocol conversion; The network-to-USB adapter circuit converts network signals into USB signals, communicates with the conversion board through the USB interface of the network-connected device, and includes a network interface card and data processing logic.

2. The expandable modular signal conversion board according to claim 1, characterized in that: The backlight driving circuit includes a chip U15, wherein the first pin of the chip U15 is connected to the feedback terminal FB1, the thirteenth pin of the chip U15 is connected to the feedback terminal FB2, the fourteenth pin of the chip U15 is connected to the feedback terminal FB3, the sixteenth pin of the chip U15 is connected to the feedback terminal FB4, the seventh pin of the chip U15 is connected to the intersection of the resistor R26 and the fourth pin of the chip U4 through the resistor R22, the sixth pin of the chip U15 is connected to the intersection of the resistor R26, the third pin of the chip U4, the second pin of the chip U4, the first pin of the chip U4 and the resistor R17 through the resistor R25, the resistor R17 is also connected to the ground, and the eighth pin of the chip U15 is connected to the intersection of the resistor R26, the third pin of the chip U4, the second pin of the chip U4, the first pin of the chip U4 and the resistor R17 through the resistor R25, the resistor R17 is also connected to the ground, and the eighth pin of the chip U15 is connected to the intersection of the resistor R26, the third pin of the chip U4, the second pin of the chip U4, the first pin of the chip U4 and the resistor R17 through the capacitor C 70 is connected to ground, the capacitor C70 is also connected to VCC, the fifteenth pin and the seventeenth pin of the chip U15 are both connected to ground, the fifth pin, the seventh pin, the sixth pin and the eighth pin of the chip U4 are mutually connected at the intersection of the diode D11, the diode D6 and one end of the inductor L3, the intersection of the diode D6 and the other end of the inductor L3 is connected to the intersection of the resistor R20, the capacitor C72, the capacitor C71, the capacitor C50 and one end of the capacitor C83, one end of the capacitor C83 is also connected to LCD_LED, the other end of the capacitor C72, the capacitor C71, the capacitor C50 and the capacitor C83 is connected to ground, the third pin of the chip U4 is connected to the intersection of the resistor R20 and the resistor R21, The resistor R21 is also connected to the ground, the ninth pin of the chip U15 is connected to the intersection of the resistor R27 and the capacitor C22, the resistor R27 is also connected to the intersection of the inductor L3, the capacitor C40, the capacitor C23, the capacitor C28, the capacitor C91 and 24V, the capacitor C28 and the capacitor C91 are both connected to the ground, the capacitor C40 and the capacitor C23 are also connected to the ground, the tenth pin of the chip U15 is also connected to the intersection of the resistor R43, the resistor R19 and one end of the capacitor C11, the other ends of the resistor R19 and the capacitor C11 intersect with the ground, the other end of the resistor R43 is connected to VCC, the fifth pin of the chip U15 is also connected to the intersection of the resistor R119 and one end of the resistor R120, The other end of the resistor R119 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is connected to the junction of one end of the resistor R117 and 3V3, the other end of the resistor R117 is connected to the junction of the base of the transistor Q3 and the resistor R118, the resistor R118 is also connected to the collector of the transistor Q2, the emitter of the transistor Q2 is connected to the ground, the base of the transistor Q2 is connected to GPIO_LCD_EN, the twelfth pin of the chip U15 is connected to the junction of the resistor R56 and BL_PWM, the second pin of the chip U15 is connected to the ground through the resistor R42, the eleventh pin of the chip U15 is connected to the capacitor C1 through the resistor R38, and the capacitor C1 is also connected to the ground,The fourth pin of the chip U15 is connected to the ground through a resistor R39.

3. The expandable modular signal conversion board according to claim 2, characterized in that: The feedback terminal FB1 is also connected to the intersection of the sixth pin of the connector J6, the test point TP22 and the protection diode VR6, the feedback terminal FB4 is also connected to the intersection of the fifth pin of the connector J6, the test point TP21 and the protection diode VR2, the feedback terminal FB3 is also connected to the intersection of the second pin of the connector J6, the test point TP19 and the protection diode VR7, the feedback terminal FB2 is also connected to the intersection of the first pin of the connector J6, the test point TP18 and the protection diode VR5, the LCD_LED is also connected to the intersection of the second pin of the connector J6, the third pin of the connector J6 and the test point TP20, the seventh pin of the connector J6 and the eighth pin of the connector J6 are connected to the ground; The BL_PWM is connected at the connection between the resistor R1509 and the resistor R1517, the resistor R1517 is also connected to the collector of the transistor Q1502, the emitter of the transistor Q1502 is connected to the intersection of one end of the resistor R1529 and 3V3, the other end of the resistor R1529 is connected to the intersection of the base of the transistor Q1502 and the resistor R1530, the resistor R1530 is also connected to the collector of the transistor Q1501, the emitter of the transistor Q1501 is connected to the ground, and the base of the transistor Q1501 is connected to DISP_PWM.

4. The expandable modular signal conversion board according to claim 1, characterized in that: The display signal conversion circuit includes a chip U17, a first pin of the chip U17 is connected to the intersection of VDD, the fifteenth pin of the chip U17 and the thirty-fifth pin of the chip U17, a twelfth pin of the chip U17 is connected to the intersection of VCC18_RX and the sixty-fourth pin of the chip U17, a thirteenth pin of the chip U17 is connected to the intersection of the resistor R90, the capacitor C93 and the first pin of the chip U18, the capacitor C93 is also connected to the ground, a second pin of the chip U18 and the fourth pin of the chip U18 are connected to the ground, a third pin of the chip U18 is connected to the intersection of the capacitor C124, the resistor R90 and the fourteenth pin of the chip U17, and the The 24th pin of the chip U17 is connected to the 37th pin of the chip U17 and to VCCIO, the 25th pin of the chip U17 is connected to DP3_TXB, the 26th pin of the chip U17 is connected to DN3_TXB, the 27th pin of the chip U17 is connected to CLKP_TXB, the 28th pin of the chip U17 is connected to CLKN_TXB, the 29th pin of the chip U17 is connected to DP2_TXB, the 30th pin of the chip U17 is connected to DN2_TXB, the 31st pin of the chip U17 is connected to DP1_TXB, and the 32nd pin of the chip U17 is connected to DN1_TXB. The thirty-third pin of the chip U17 is connected to DN0_TXB, the thirty-fourth pin of the chip U17 is connected to DP0_TXB, the thirty-sixth pin of the chip U17 is connected to VCC18_TX, the thirty-seventh pin of the chip U17 is connected to VCCIO, the thirty-eighth pin of the chip U17 is connected to DP3_TXA, the thirty-ninth pin of the chip U17 is connected to DN3_TXA, the fortieth pin of the chip U17 is connected to CLKP_TXA, the forty-first pin of the chip U17 is connected to CLKN_TXA, the forty-second pin of the chip U17 is connected to DP2_TXA, the forty-third pin of the chip U17 is connected to DN2_TXA, the forty-fourth pin of the chip U17 is connected to DP1_TXA, the forty-fifth pin of the chip U17 is connected to DN1_TXA, the forty-sixth pin of the chip U17 is connected to DN0_TXA, and the forty-eighth pin of the chip U17 is connected to VCC18.

5. The expandable modular signal conversion board according to claim 4, characterized in that: The 49th pin of the chip U17 is connected to the junction of LT9211_RST, resistor R31 and capacitor C21, the capacitor C21 is also connected to the ground, the resistor R31 is also connected to VCC18, the 50th pin of the chip U17 is connected to TP_SDA, the 51st pin of the chip U17 is connected to TP_SCI, the 52nd pin of the chip U17 is connected to TP_INT through resistor R112, the 53rd pin of the chip U17 is connected to DSI0_LANE3_N, the 54th pin of the chip U17 is connected to DSI0_LANE3_P, the 55th pin of the chip U17 is connected to DSI0_LANE2_N, and the 50th pin of the chip U17 is connected to DSI0_LANE3_V The 56th pin of the chip U17 is connected to DSI0_LANE2_P, the 57th pin of the chip U17 is connected to DSI0_CLK_N, the 58th pin of the chip U17 is connected to DSI0_CLK_P, the 59th pin of the chip U17 is connected to DSI0_LANE1_N, the 60th pin of the chip U17 is connected to DSI0_LANE1_P, the 61st pin of the chip U17 is connected to DSI0_LANE0_N, the 62nd pin of the chip U17 is connected to DSI0_LANE0_P, the 63rd pin of the chip U17 is connected to the 65th pin of the chip U17 through the resistor R93, and the 65th pin of the chip U17 is also connected to ground; The VDD is also connected to the junction of one end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206, and the other end of capacitor C190, capacitor C203, capacitor C205 and capacitor C206 is connected to the ground. The VCC18_RX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. The VCC18_TX is also connected to the junction of one end of capacitor C133, capacitor C204 and capacitor C208, and the other end of capacitor C133, capacitor C204 and capacitor C208 is connected to the ground. It is connected to the intersection of one end of capacitor C210 and capacitor C227, and the other end of the intersection of capacitor C210 and capacitor C227 is connected to the ground. The VCCIO is also connected to the intersection of one end of capacitor C176, capacitor C178 and capacitor C179, and the other end of the intersection of capacitor C176, capacitor C178 and capacitor C179 is connected to the ground. The VCC18 is also connected to the intersection of one end of capacitor C58 and capacitor C97, and the other end of the intersection of capacitor C58 and capacitor C97 is connected to the ground.

6. The expandable modular signal conversion board according to claim 1, characterized in that: The USB-HUB circuit includes a chip U2 and a chip U23, wherein the first pin of the chip U2 is connected to the fifth pin of the chip U2 and the tenth pin of the chip U2 respectively, the first pin of the chip U2 is also connected to the intersection of capacitor C6, capacitor C7 and one end of resistor B20, the other end of the resistor B20 is connected to the intersection of the sixteenth pin of the chip U2, the twenty-fourth pin of the chip U2, capacitor C8, capacitor C9 and one end of VCC_3V3, the other ends of the capacitors C6, C7, C8 and C9 are mutually connected to the ground, the sixth pin of the chip U2 is connected to 12MHZ_OSC_IN1, the seventh pin of the chip U2 is connected to 12MHZ_OSC_OUT1, the seventeenth pin of the chip U2 is connected to VCC_3V3 through a resistor R164, the fourteenth pin of the chip U2 is connected to the ground through a resistor R165, the thirteenth pin of the chip U2 is connected to resistor R167, capacitor C10, resistor R The second end of the resistor R166 is connected to VCC_3V3, the other end of the resistor R167 and the capacitor C10 are connected to the ground, the twenty-fifth pin of the chip U2 is connected to USB_DM_HUB, the seventh and twenty-sixth pins of the chip U2 are connected to USB_DP_HUB, the fourth pin of the chip U2 is connected to the ground through the resistor R168, the fifteenth pin of the chip U2 is connected to the ground, the eighteenth pin of the chip U2 is connected to the intersection of the resistor R173 and VCC_3V3 through the resistor R172, the resistor R173 is also connected to the twenty-first pin of the chip U2, the twelfth pin of the chip U2 is connected to the first pin of the filter EMI22, the eleventh pin of the chip U2 is connected to the second pin of the filter EMI22, the third pin of the filter EMI22 is connected to HUB_HOST1_DM4, and the fourth pin of the filter EMI22 is connected to HUB_HOST1_DP4.

7. The expandable modular signal conversion board according to claim 6, characterized in that: The ninth pin of the chip U2 is connected to the first pin of the filter EMI21, the eighth pin of the chip U2 is connected to the second pin of the filter EMI21, the third pin of the filter EMI21 is connected to HUB_HOST1_DM2, the fourth pin of the filter EMI21 is connected to HUB_HOST1_DP2, the third pin of the chip U2 is connected to the first pin of the filter EMI20, the second pin of the chip U2 is connected to the second pin of the filter EMI20, the third pin of the filter EMI20 is connected to LAN_USB_DM, the fourth pin of the filter EMI20 is connected to LAN_USB_DP, the twenty-eighth pin of the chip U2 is connected to the first pin of the filter EMI19, the twenty-seventh pin of the chip U2 is connected to the second pin of the filter EMI19, the third pin of the filter EMI19 is connected to TP_USB_DM, and the fourth pin of the filter EMI19 is connected to TP_USB_DP; The first pin of the chip U23 is connected to the junction of capacitor C269 and 12MHZ_OSC_OUT1, and the capacitor C269 is also connected to the ground. The second pin of the chip U23 and the fourth pin of the chip U23 are both connected to the ground. The third pin of the chip U23 is connected to the junction of capacitor C32 and 12MHZ_OSC_IN1, and the capacitor C32 is also connected to the ground.

8. The expandable modular signal conversion board according to claim 1, characterized in that: The network to USB adapter circuit includes a chip U21, a chip U46, a connector J2 and a chip U103. The first pin of the chip U21 is connected to the junction of capacitor C139, capacitor C5 and VDD33_PHY, the second pin of the chip U21 is connected to TXOP, the third pin of the chip U21 is connected to TXOH, the fourth pin of the chip U21 is connected to RXIP, the fifth pin of the chip U21 is connected to RXIN, the sixth pin of the chip U21 is connected to ground, the seventh pin of the chip U21 is connected to LAN_USB_DM, the eighth pin of the chip U21 is connected to LAN_USB_DP, and the The ninth pin is connected to the junction of capacitor C135 and VDD10_PHY, the tenth pin of the chip U21 is connected to the junction of capacitor C136, capacitor C131 and VDD33_PHY, the capacitor C136 and capacitor C131 are also connected to the ground, the eleventh pin of the chip U21 is connected to VDD5_PHY, the twelfth pin of the chip U21 is connected to the junction of capacitor C132 and one end of capacitor C134, the other ends of C132 and C134 are connected to the ground, the thirteenth pin of the chip U21 is connected to the junction of capacitor C141 and V The fourteenth pin of the chip U21 is connected to the intersection of the resistor R183, the resistor R184 and VDD33_PHY through the resistor R1, the resistor R183 is also connected to the eighteenth pin of the chip U21, the resistor R184 is also connected to the nineteenth pin of the chip U21, the fifteenth pin of the chip U21 is connected to VDD33_PHY, the sixteenth pin of the chip U21 is connected to the intersection of the capacitor C142 and VDD10_PHY, the seventeenth pin of the chip U21 is connected to LED1_SPEED_Y The twenty-first pin of the chip U21 is connected to 25MHZ_OSC_OUT, the twenty-second pin of the chip U21 is connected to 25MHZ_OSC_IN, the twenty-third pin of the chip U21 is connected at the junction of capacitor C143, capacitor C144 and one end of resistor R66, the other ends of capacitor C143 and capacitor C144 are connected to ground, the other end of resistor R66 is connected to VDD10_PHY, the twenty-fourth pin of the chip U21 is connected to ground through resistor R85, and the twenty-fifth pin of the chip U21 is connected to ground.

9. The expandable modular signal conversion board according to claim 8, characterized in that: The VDD33_PHY is connected to the junction of the resistor R134 and one end of the resistor R9, the other end of the resistor R134 is connected to LED1_SPEED_Y through the diode D9, and the other end of the resistor R9 is connected to LED0_LINK_G through the diode D10; The LAN_USB_DM is connected to the test point TP15, the LAN_USB_DP is connected to the test point TP16; the VDD5_PHY is connected to the test point TP17; The first pin of the chip U46 is connected to the junction of the capacitor C484 and 25MHZ_OCS_OUT, and the capacitor C484 is also connected to the ground. The second pin of the chip U46 and the fourth pin of the chip U46 are both connected to the ground. The third pin of the chip U46 is connected to the junction of the capacitor C485 and 25MHZ_OCS_IN, and the capacitor C485 is also connected to the ground. The VDD5_PHY is connected to the junction of the resistor R182, the capacitor C4 and one end of the capacitor C42, the other ends of the capacitor C4 and the capacitor C42 are connected to the ground, and the other end of the resistor R182 is connected to HUB_HOST_VBUS; The first pin of the connector J2 is connected to the connection between the protection diode MLV4, the test point TP51 ​​and one end of TXP, the second pin of the connector J2 is connected to the connection between the protection diode MLV2, the test point TP50 and one end of TXN, the third pin of the connector J2 is connected to the connection between the protection diode MLV6, the test point TP41 and one end of RXP, the fourth pin of the connector J2 and the fifth pin of the connector J2 are connected to each other, the fifth pin of the connector J2 is also connected to the connection between the protection diode MLV5 and one end of the terminal T45, and the sixth pin of the connector J2 is connected to the protection diode MLV6. The diode MLV8, the test point 39 and one end of RXN are connected, the seventh pin of the connector J2 and the eighth pin of the connector J2 are connected to each other, and the eighth pin of the connector J2 is also connected to the connection between the protection diode MLV7 and one end of the terminal T78, the other ends of the protection diodes MLV4, MLV2, MLV6, MLV5, MLV8 and MLV7 are connected to each other and to the ground, and the ninth pin of the connector J2 is connected to the intersection of the tenth pin of the connector J2, the test point TP52 and EARTH_GND.

10. The expandable modular signal conversion board according to claim 8, characterized in that: The first pin of the chip U103 is connected to RXIP, the second pin of the chip U103 is connected to RXIN, the third pin of the chip U103 is connected to ground through a capacitor C44, the seventh pin of the chip U103 is connected to TXOP, the eighth pin of the chip U103 is connected to TXON, the sixth pin of the chip U103 is connected to ground through a capacitor C43, the ninth pin of the chip U103 is connected to TXN, the tenth pin of the chip U103 is connected to TXP, and the eleventh pin of the chip U103 is connected to The resistor R5, the resistor R6, the resistor R136 and one end of the capacitor C506 intersect, the other end of the capacitor C506 is connected to the intersection of the capacitor C502, the resistor R7 and one end of EARTH_GND, the other ends of the capacitor C502 and the resistor R7 are connected to the ground, the other end of the resistor R6 is connected to the terminal T78, the other end of the resistor R136 is connected to the terminal T45, the other end of the resistor R5 is connected to the fourteenth pin of the chip U103, the fifteenth pin of the chip U103 is connected to RXN, and the sixteenth pin of the chip U103 is connected to RXP.

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