Test method
By traversing the test program set in the aging test, generating activation signals and voltage control signals, and applying different voltages on some word lines of the memory, the problem of weak memory cells in the memory is difficult to be exposed early, and the memory product is improved Quality effect.
Patent Information
- Application Number
- CN202310915969.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-24
- Publication Date
- 2025-02-07
AI Technical Summary
The prior art is difficult to expose weak memory units in the memory as early as possible during the aging test, affecting the product quality of the memory.
By traversing the test programs in the test program set, an activation signal and voltage control signal are generated, partial word lines are activated and different voltages are applied on the adjacent two bit lines, thereby generating stronger stress effects and weaker storage The unit failed during the early testing phase.
Effectively expose weak memory cells to the early stages of aging testing, preventing memory containing weak memory cells from flowing into the market, thereby improving the product quality of the memory.
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Figure CN119400229A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a testing method. Background Art
[0002] The memory usually includes a plurality of storage units, each of which usually includes a capacitor for storing data in the form of electric charge. The time between the leakage of the capacitor from a high-level signal to a low-level signal is the data retention time of the corresponding storage unit.
[0003] In order to prevent data loss in the memory, the memory needs to refresh all the data stored in it within a limited time. When the data retention time of weak storage cells in the memory is less than the refresh interval of the memory, these weak storage cells will have data reading errors, which will affect the product quality of the memory.
[0004] At present, in order to improve the product quality of memory, a burn-in test is usually performed on the memory to determine whether there are weak memory cells in the memory. However, how to expose the weak memory cells in the memory as early as possible during the burn-in test is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present disclosure provides a testing method that can expose weak memory cells in a memory as early as possible during an aging test, thereby facilitating accurate detection of whether there are weak memory cells in the memory.
[0006] In an embodiment of the present disclosure, a test method is provided, which is applied to a memory, wherein the memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage cells, each of the storage cells being connected to a corresponding one of the word lines and one of the bit lines; the method includes:
[0007] Traversing the test programs in the test program set, and generating an activation signal and a voltage control signal according to the traversed test programs; the test program set includes at least one test program;
[0008] Activating some of the word lines in the plurality of word lines using the activation signal, and applying voltage to the plurality of bit lines using the voltage control signal; wherein there is at least one unactivated word line between two adjacent activated word lines, and there is a voltage difference between the voltages applied to any two adjacent bit lines;
[0009] After traversing the test programs in the test program set, it is detected whether there is a target memory cell with a defect in the plurality of memory cells.
[0010] In some embodiments, the test program set includes a first test program, and generating an activation signal and a voltage control signal according to the traversed test program includes:
[0011] A first activation signal and a first voltage control signal are generated according to the traversed first test program; the first activation signal is used to activate even-numbered word lines among the multiple word lines, and the first voltage control signal is used to apply a first voltage to even-numbered bit lines among the multiple bit lines, and to apply a second voltage to odd-numbered bit lines among the multiple bit lines; there is a voltage difference between the first voltage and the second voltage.
[0012] In some embodiments, the test program set further includes a second test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes:
[0013] A second activation signal and a second voltage control signal are generated according to the traversed second test program; the second activation signal is used to activate the even-numbered word lines among the multiple word lines, and the second voltage control signal is used to apply the second voltage to the even-numbered bit lines among the multiple bit lines, and to apply the first voltage to the odd-numbered bit lines among the multiple bit lines.
[0014] In some embodiments, the test program set further includes a third test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes:
[0015] A third activation signal and a third voltage control signal are generated according to the traversed third test program; the third activation signal is used to activate odd-numbered word lines among the multiple word lines, and the third voltage control signal is used to apply the first voltage to even-numbered bit lines among the multiple bit lines, and to apply the second voltage to odd-numbered bit lines among the multiple bit lines.
[0016] In some embodiments, the test program set further includes a fourth test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes:
[0017] A fourth activation signal and a fourth voltage control signal are generated according to the traversed fourth test program; the fourth activation signal is used to activate odd-numbered word lines among the multiple word lines, and the fourth voltage control signal is used to apply the second voltage to even-numbered bit lines among the multiple bit lines, and to apply the first voltage to odd-numbered bit lines among the multiple bit lines.
[0018] In some embodiments, the first voltage is a high voltage and the second voltage is a low voltage.
[0019] In some embodiments, the method further comprises:
[0020] After the holding time of the activation signal and the voltage control signal is equal to the preset time, the currently activated word line is turned off.
[0021] In some embodiments, before generating the activation signal and the voltage control signal according to the traversed test program, the method further includes:
[0022] First data or second data is written into each of the storage units; the first data is different from the second data.
[0023] In some embodiments, the detecting whether there is a target memory cell with a defect in the plurality of memory cells comprises:
[0024] Writing test data into the plurality of storage cells;
[0025] Storage data is read from the plurality of storage cells, and whether the target storage cell exists in the plurality of storage cells is determined according to the test data and the storage data.
[0026] In some embodiments, determining whether the target storage unit exists in the plurality of storage units according to the test data and the storage data includes:
[0027] If the storage data is the same as the test data, determining that the target storage unit does not exist in the plurality of storage units;
[0028] If the stored data is different from the test data, a storage unit corresponding to a bit position where the stored data and the test data are different is determined as the target storage unit.
[0029] The testing method provided in the embodiment of the present disclosure applies different voltages to any two adjacent bit lines when activating some word lines in the memory, thereby producing a stronger stress effect, causing weaker memory cells to fail in the early testing stage, and preventing memories containing such weak memory cells from entering the market, thereby improving the product quality of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of a layout of a memory device provided in an embodiment of the present disclosure;
[0031] Figure 2 A schematic diagram of the structure of a storage unit of a storage device provided in an embodiment of the present disclosure;
[0032] Figure 3 A schematic diagram of a testing method provided in an embodiment of the present disclosure;
[0033] Figure 4 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 1 ;
[0034] Figure 5 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 2 ;
[0035] Figure 6 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 3 ;
[0036] Figure 7 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 4 ;
[0037] Figure 8 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 5 ;
[0038] Fig. 9 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 6 ;
[0039] Fig.10 A schematic diagram of a program module of a testing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of the disclosure can also constitute a complete implementation method separately.
[0041] It should be noted that the brief description of terms in the present disclosure is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.
[0042] The terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and are not necessarily meant to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, for example, they can be implemented in an order other than those given in the diagrams or descriptions of the embodiments of the present disclosure.
[0043] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.
[0044] It should be understood that when an element is referred to as being “connected” or “electrically connected” to other elements in an embodiment of the present disclosure, the element may be directly connected or electrically connected to the other elements; or there may be several intermediate elements, and the element may be connected or electrically connected to the other elements through the several intermediate elements.
[0045] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or a combination of hardware and / or software code that can perform the functions associated with the element.
[0046] The embodiments of the present disclosure relate to the field of semiconductor memory technology. In some embodiments, the present disclosure can be applied to dynamic random access memory (DRAM), including DRAM aging test. It should be noted that the test method provided in the embodiments of the present disclosure can be applied to DRAM as well as other memories with aging test requirements, which is not limited in the embodiments of the present disclosure.
[0047] It can be understood that a memory generally includes a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding WL and a corresponding BL.
[0048] In some embodiments, each storage unit includes a transistor and a capacitor, the gate of the transistor is connected to WL, one of the source / drain of the transistor is connected to BL, and the other is connected to the capacitor. The voltage signal on WL can control the opening or closing of the above transistor, and then read the data signal stored in the above capacitor through BL, or write the data signal into the above capacitor for storage through BL.
[0049] In order to better understand the embodiments of the present disclosure, refer to Figure 1 , Figure 1 A schematic diagram of the layout of a storage device provided in an embodiment of the present disclosure.
[0050] In some embodiments, taking a Bank in a DRAM as an example, a plurality of bit lines can be divided into 128 bit line groups, each of which has 8 bit lines. For the convenience of the following description, the bit lines in each bit line group are recorded as BL0, BL1, BL2, ... BL7. A plurality of word lines can be divided into 8192 word line groups, each of which has 8 word lines. For the convenience of the following description, the word lines in each word line group are recorded as WL0, WL1, WL2, ... WL7.
[0051] Multiple memory cells P11~P88 are distributed in a matrix, wherein the memory cells in the first column are all connected to the word line BL0, the memory cells in the second column are all connected to the word line BL1, and so on, the memory cells in the eighth column are all connected to the word line BL7; the memory cells in the first row are all connected to the bit line WL0, the memory cells in the second row are all connected to the bit line WL1, and so on, the memory cells in the eighth row are all connected to the bit line WL7, so that each memory cell is connected to a word line WL and a bit line BL.
[0052] Reference Figure 2 , Figure 2 A schematic diagram of the structure of a storage unit of a storage device provided in an embodiment of the present disclosure.
[0053] In some embodiments, each memory cell 10 includes a transistor 12 and a capacitor 11, the gate of the transistor 12 is connected to WL, the source of the transistor 12 is connected to BL, and the drain of the transistor 12 is connected to the capacitor 11. It should be noted that the source of the transistor 12 may also be connected to the capacitor 11, and correspondingly, the drain of the transistor 12 is connected to the bit line BL.
[0054] In some embodiments, when the signal on WL turns on transistor 12, BL can write a high-level signal "1" to capacitor 11. When the signal on WL turns off transistor 12, the charge on capacitor 11 gradually leaks over time. The time between the capacitor 11 leaking from the high-level signal "1" to the low-level signal "0" is the data retention time of the corresponding storage unit. The data retention time of the storage unit needs to be greater than the preset time length to realize the dynamic storage function of the dynamic random access memory.
[0055] In order to prevent the loss of data stored in the memory, the memory needs to refresh all the data stored in it within a limited time. During the refresh process, the memory first reads the original data, compares the level of the capacitor with the reference level, determines the 1 / 0 value of the data, and then writes the original data back. During the writing process, the capacitor is fully charged (if the data is 1), which is like a charging operation.
[0056] Among them, when the data retention time of weak memory cells in the memory is less than the refresh interval of the memory, these weak memory cells will have data reading errors, which will affect the product quality of the memory. Therefore, accurately testing whether there are these weak memory cells in the memory is of great significance to improving the product quality of the memory.
[0057] At present, a burn-in test is usually performed on the memory to determine whether there are weak memory cells in the memory. However, how to expose the weak memory cells in the memory as early as possible during the burn-in test is a technical problem that needs to be solved urgently.
[0058] In view of the above technical problems, a test method is provided in an embodiment of the present disclosure. When some word lines in a memory are activated, different voltages are applied to any two adjacent bit lines, thereby generating a stronger stress effect, so that weaker memory cells fail in the early test stage, and thus preventing memories containing such weak memory cells from entering the market, thereby improving the product quality of the memory. The following is a detailed description using an embodiment.
[0059] Reference Figure 3 , Figure 3 The following is a flow chart of steps of a test method provided in an embodiment of the present disclosure. In some embodiments, the test method is applied to a memory, the memory comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each memory cell being connected to a corresponding word line and a bit line; the method comprising:
[0060] S301 , traversing the test programs in the test program set, and generating an activation signal and a voltage control signal according to the traversed test programs.
[0061] Among them, the above-mentioned test program set includes at least one test program.
[0062] In some embodiments, the embodiments of the present disclosure may be applied to a burn-in test of a DRAM chip at a high temperature of 125°C.
[0063] Among them, the aging test of memory is to accelerate the aging of memory at high temperature, so that the defective memory cells are exposed as early as possible, mainly because the electron migration speed increases at high temperature and the atomic barrier effect is more obvious. For example, a memory cell that may have defects after 3 years of use may have defects after 10 days of use at high temperature.
[0064] In some implementations, multiple test programs may be pre-set and stored in a test program set, wherein different test programs may control word lines or bit lines in different ways.
[0065] In some embodiments, the above test program may also be referred to as a test mode code (Test-Mode Code, TM).
[0066] In some embodiments, when performing an aging test on a memory, each test program in the above test program set can be traversed, and an activation signal and a voltage control signal can be generated according to the traversed test program. The activation signal is used to control the opening and closing of the word line, and the voltage control signal is used to control the voltage applied to the bit line.
[0067] S302, using an activation signal to activate some of the multiple word lines, and using a voltage control signal to apply voltage to the multiple bit lines; wherein there is at least one unactivated word line between two adjacent activated word lines, and there is a voltage difference between the voltages applied to any two adjacent bit lines.
[0068] In some embodiments, the activation signal may be used to activate some of the multiple word lines, for example, only WL0, WL2, WL3, WL4, ..., WL2n may be activated, or only WL1, WL3, WL5, WL7, ..., WL2n-1 may be activated, so that there is an unactivated word line between two adjacent activated word lines, where n is a positive integer.
[0069] In some embodiments, the voltage control signal may be used to apply voltage to the plurality of bit lines so that there is a voltage difference between the voltages applied to any two adjacent bit lines. For example, a high voltage may be applied to BL0, BL2, BL3, BL4, ..., BL2n, and a low voltage may be applied to BL1, BL3, BL5, BL7, ..., BL2n-1; or a high voltage may be applied to BL1, BL3, BL5, BL7, ..., BL2n-1, and a low voltage may be applied to BL0, BL2, BL3, BL4, ..., BL2n.
[0070] It is understandable that when some word lines in the memory are activated, different voltages are applied to any two adjacent bit lines, thereby generating a stronger stress effect, thereby making weaker memory cells more susceptible to failure.
[0071] Specifically, when some word lines in the memory are activated, different voltages are applied to any two adjacent bit lines, which can apply stress to adjacent memory cells (i.e., double bits) on the same BL, and can also make hidden double bit failures more easily exposed at an early stage, which helps to detect relatively weak defects between adjacent memory cells at an early stage.
[0072] S303: After traversing the test programs in the test program set, detect whether there is a target storage unit with defects in the multiple storage units.
[0073] In some embodiments, after traversing the test programs in the test program set, the memory can be cooled down to keep the memory in a normal temperature working environment. In the normal temperature working environment, it is detected whether there is a target memory cell among the multiple memory cells, and the target memory cell is a defective weak memory cell.
[0074] The test method provided by the embodiment of the present disclosure applies different voltages to any two adjacent bit lines when activating some word lines in the memory, thereby producing a stronger stress effect, causing weaker memory cells to fail in the early testing stage, thereby preventing memories containing such weak memory cells from entering the market and improving the product quality of the memories.
[0075] Based on the contents described in the above embodiments, in some embodiments of the present disclosure, the above test program set may include a first test program, a second test program, a third test program, and a fourth test program, wherein:
[0076] The first test procedure is used to activate even-numbered word lines, apply a first voltage to even-numbered bit lines, and apply a second voltage to odd-numbered bit lines.
[0077] The second test procedure is used to activate the even-numbered word lines, apply the second voltage to the even-numbered bit lines, and apply the first voltage to the odd-numbered bit lines.
[0078] The third test procedure is used to activate odd-numbered word lines, and to apply a first voltage to even-numbered bit lines and a second voltage to odd-numbered bit lines.
[0079] The fourth test procedure is used to activate odd-numbered word lines, apply the second voltage to even-numbered bit lines, and apply the first voltage to odd-numbered bit lines.
[0080] Among them, the even-numbered word lines may be WL0, WL2, WL4, ..., WL2n, and the odd-numbered word lines may be WL1, WL3, WL5, ..., WL2n-1; or, according to the arrangement order of the word lines, the even-numbered word lines may be WL1, WL3, WL5, ..., WL2n-1, and the odd-numbered word lines may be WL0, WL2, WL4, ..., WL2n, which is not limited in the embodiments of the present disclosure.
[0081] Similarly, the even-numbered bit lines may be BL0, BL2, BL4, ..., BL2n, and the odd-numbered bit lines may be BL1, BL3, BL5, ..., BL2n-1; or, in the arrangement order of the bit lines, the even-numbered bit lines may be BL1, BL3, BL5, ..., BL2n-1, and the odd-numbered bit lines may be BL0, BL2, BL4, ..., BL2n, which is not limited in the embodiments of the present disclosure.
[0082] The first voltage is a high voltage and the second voltage is a low voltage. Alternatively, the first voltage can also be a low voltage and the second voltage can be a high voltage, which is not limited in the disclosed embodiment as long as there is a voltage difference between the first voltage and the second voltage.
[0083] In some implementations, after the activation signal and the voltage control signal are maintained for a time period equal to a preset time period, the currently activated word line is turned off.
[0084] In some embodiments, before generating the activation signal and the voltage control signal according to the traversed test program, the first data or the second data may be written into each storage unit. The first data is different from the second data. For example, the first data may be "0" and the second data may be "1".
[0085] In some embodiments, based on the first test procedure, the even-numbered WLs can be activated, a high voltage is applied to the even-numbered BLs, a low voltage is applied to the odd-numbered BLs, and after holding for 1 second, the activated even-numbered WLs are turned off; based on the second test procedure, the even-numbered WLs can be activated, a low voltage is applied to the even-numbered BLs, a high voltage is applied to the odd-numbered BLs, and after also holding for 1 second, the activated even-numbered WLs are turned off. Wherein, when the even-numbered WLs are turned on, the memory cells on the even-numbered BLs and the memory cells on the odd-numbered BLs store a high level and a low level respectively, so that the adjacent memory cells (double bit) have a stronger stress effect due to the voltage difference. Similarly, when the even-numbered WLs are turned on, the memory cells on the even-numbered BLs and the memory cells on the odd-numbered BLs store a low level and a high level respectively, so that stress can be applied bidirectionally between the adjacent memory cells on the even-numbered WLs, so that the adjacent weak memory cells can be more easily exposed.
[0086] Furthermore, based on the third test procedure, the odd-numbered WLs can be activated, a high voltage is applied to the even-numbered BLs, a low voltage is applied to the odd-numbered BLs, and after holding for 1 second, the activated even-numbered WLs are turned off; based on the fourth test procedure, the odd-numbered WLs are activated, a low voltage is applied to the even-numbered BLs, a high voltage is applied to the odd-numbered BLs, and after holding for 1 second, the activated even-numbered WLs are turned off. Wherein, when the odd-numbered WLs are turned on, the storage cells on the even-numbered BLs and the storage cells on the odd-numbered BLs store a high level and a low level respectively, so that the adjacent storage cells (double bit) have a stronger stress effect due to the voltage difference. Similarly, when the odd-numbered WLs are turned on, the storage cells on the even-numbered BLs and the storage cells on the odd-numbered BLs store a low level and a high level respectively, so that stress can be applied bidirectionally between the adjacent storage cells on the even-numbered WLs, so that the adjacent weak storage cells can be more easily exposed.
[0087] Exemplarily, when performing an aging test on a memory, the above test method may include the following steps:
[0088] Step 1: Write the first data "0" into each storage unit.
[0089] For details, please refer to Figure 4 , Figure 4 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 1 .exist Figure 4 In FIG. 1 , the hollow circle indicates that the storage cell connected to the WL and BL is currently at a low potential.
[0090] Step 2: Traverse the first test program in the test program set, and generate a first activation signal and a first voltage control signal according to the traversed first test program; wherein the first activation signal is used to activate even-numbered word lines, and the first voltage control signal is used to apply a high voltage to even-numbered bit lines and a low voltage to odd-numbered bit lines.
[0091] For details, please refer to Figure 5 , Figure 5 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 2 .exist Figure 5 In the figure, the hollow circle indicates that the storage unit connected to the WL and BL is currently at a low potential, and the solid circle indicates that the storage unit connected to the WL and BL is currently at a high potential.
[0092] In some implementations, after the first activation signal and the first voltage control signal are maintained for a time equal to a preset time (eg, 1 s), the currently activated word line is turned off.
[0093] Step 3: Write the second data "1" into each storage unit.
[0094] For details, please refer to Figure 6 , Figure 6 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 3 .exist Figure 6 In FIG. 1 , the solid circle indicates that the memory cell connected to the WL and BL is currently at a high potential.
[0095] Step 4: Traverse the second test program in the test program set, and generate a second activation signal and a second voltage control signal according to the traversed second test program; wherein the second activation signal is used to activate even-numbered word lines, and the second voltage control signal is used to apply a low voltage to even-numbered bit lines and a high voltage to odd-numbered bit lines.
[0096] For details, please refer to Figure 7 , Figure 7 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 4 .exist Figure 7 In the figure, the hollow circle indicates that the storage unit connected to the WL and BL is currently at a low potential, and the solid circle indicates that the storage unit connected to the WL and BL is currently at a high potential.
[0097] In some implementations, after the second activation signal and the second voltage control signal are maintained for a predetermined time period (eg, 1 s), the currently activated word line is turned off.
[0098] Step 5: Write the first data "0" into each storage unit. Figure 4 , which will not be described in detail in the embodiments of this disclosure.
[0099] Step six: traverse the third test program in the test program set, and generate a third activation signal and a third voltage control signal according to the traversed third test program; wherein the third activation signal is used to activate odd-numbered word lines, and the third voltage control signal is used to apply a high voltage to even-numbered bit lines and a low voltage to odd-numbered bit lines.
[0100] For details, please refer to Figure 8 , Figure 8 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 5 .exist Figure 8 In the figure, the hollow circle indicates that the storage unit connected to the WL and BL is currently at a low potential, and the solid circle indicates that the storage unit connected to the WL and BL is currently at a high potential.
[0101] In some implementations, after the third activation signal and the third voltage control signal are maintained for a predetermined time period (eg, 1 s), the currently activated word line is turned off.
[0102] Step 7: Write the second data "1" into each storage unit. For details, please refer to Figure 6 , which will not be described in detail in the embodiments of this disclosure.
[0103] Step 8: Traverse the fourth test program in the test program set, and generate a fourth activation signal and a fourth voltage control signal according to the traversed fourth test program; wherein the fourth activation signal is used to activate odd-numbered word lines, and the fourth voltage control signal is used to apply a low voltage to even-numbered bit lines and a high voltage to odd-numbered bit lines.
[0104] For details, please refer to Fig. 9 , Fig. 9 Schematic diagram of the storage potential of each storage unit in the embodiment of the present disclosure Figure 5 .exist Fig. 9 In the figure, the hollow circle indicates that the storage unit connected to the WL and BL is currently at a low potential, and the solid circle indicates that the storage unit connected to the WL and BL is currently at a high potential.
[0105] In some implementations, after the fourth activation signal and the fourth voltage control signal are maintained for a predetermined time period (eg, 1 s), the currently activated word line is turned off.
[0106] In the embodiment of the present disclosure, during the aging test phase, the test programs in the test program set are traversed, and different voltages are applied to two adjacent BLs when the even (or odd) WLs are activated. In this way, the voltage difference between each pair of even BL storage cells and odd BL storage cells can evolve a stronger aging effect, which can expose hidden double bit fails at an early stage.
[0107] In some embodiments, after traversing the test programs in the test program set, the memory can be cooled down to put the memory in a normal temperature working environment. In the normal temperature working environment, test data is written into multiple storage units of the memory; after a preset time, the storage data is read from the multiple storage units, and based on the test data and the storage data, it is determined whether there is a target storage unit with a defect in the multiple storage units.
[0108] In some embodiments, if the above-mentioned storage data is the same as the test data, it is determined that there is no target storage unit in the above-mentioned multiple storage units; if the above-mentioned storage data is different from the test data, the storage unit corresponding to the bit position where there is a difference between the above-mentioned storage data and the test data is determined as the target storage unit.
[0109] The test data may be a high level signal "1".
[0110] It is understandable that after writing the test data in the above-mentioned multiple storage cells, if there are weak storage cells among the above-mentioned multiple storage cells, these weak storage cells will quickly leak charges, causing the high-level signal "1" to become a low-level signal "0", so the data read from these weak storage cells will become "0", resulting in a read error.
[0111] In the embodiment of the present disclosure, during the aging test of the memory, by writing test data in multiple storage cells, reading storage data from the multiple storage cells, and comparing the test data with the storage data, it is possible to accurately determine whether there are weak storage cells among the multiple storage cells.
[0112] Based on the contents described in the above embodiments, a testing device is also provided in the embodiments of the present disclosure, which is applied to a memory, wherein the memory includes multiple word lines, multiple bit lines and multiple storage cells, each storage cell is connected to a corresponding word line and a bit line.
[0113] Reference Fig.10 , Fig.10 Schematic diagram of a program module of a test device provided in an embodiment of the present disclosure. The test device 100 includes:
[0114] The signal generating module 1001 is used to traverse the test programs in the test program set, and generate an activation signal and a voltage control signal according to the traversed test programs; the test program set includes at least one test program.
[0115] The processing module 1002 is used to activate some of the multiple word lines using the activation signal, and to apply voltage to the multiple bit lines using the voltage control signal; wherein there is at least one unactivated word line between two adjacent activated word lines, and there is a voltage difference between the voltages applied between any two adjacent bit lines.
[0116] The detection module 1003 is used to detect whether there is a target storage unit with defects in the multiple storage units after traversing the test programs in the test program set.
[0117] The test device provided in the embodiment of the present disclosure applies different voltages to any two adjacent bit lines when activating some word lines in the memory, thereby producing a stronger stress effect, causing weaker memory cells to fail in the early testing stage, and preventing memories containing such weak memory cells from entering the market, thereby improving the product quality of the memory.
[0118] In some embodiments, the test program set includes a first test program, and the signal generating module 1001 is used to:
[0119] A first activation signal and a first voltage control signal are generated according to the traversed first test program; the first activation signal is used to activate even-numbered word lines among the multiple word lines, and the first voltage control signal is used to apply a first voltage to even-numbered bit lines among the multiple bit lines, and to apply a second voltage to odd-numbered bit lines among the multiple bit lines; there is a voltage difference between the first voltage and the second voltage.
[0120] In some embodiments, the test program set further includes a second test program, and the signal generating module 1001 is used to:
[0121] A second activation signal and a second voltage control signal are generated according to the traversed second test program; the second activation signal is used to activate the even-numbered word lines among the multiple word lines, and the second voltage control signal is used to apply the second voltage to the even-numbered bit lines among the multiple bit lines, and to apply the first voltage to the odd-numbered bit lines among the multiple bit lines.
[0122] In some embodiments, the test program set further includes a third test program, and the signal generating module 1001 is used to:
[0123] A third activation signal and a third voltage control signal are generated according to the traversed third test program; the third activation signal is used to activate odd-numbered word lines among the multiple word lines, and the third voltage control signal is used to apply the first voltage to even-numbered bit lines among the multiple bit lines, and to apply the second voltage to odd-numbered bit lines among the multiple bit lines.
[0124] In some embodiments, the test program set further includes a fourth test program, and the signal generating module 1001 is used to:
[0125] A fourth activation signal and a fourth voltage control signal are generated according to the traversed fourth test program; the fourth activation signal is used to activate odd-numbered word lines among the multiple word lines, and the fourth voltage control signal is used to apply the second voltage to even-numbered bit lines among the multiple bit lines, and to apply the first voltage to odd-numbered bit lines among the multiple bit lines.
[0126] In some embodiments, the first voltage is a high voltage and the second voltage is a low voltage.
[0127] In some embodiments, the processing module 1002 is further configured to:
[0128] After the holding time of the activation signal and the voltage control signal is equal to the preset time, the currently activated word line is turned off.
[0129] In some embodiments, the above device further comprises a pre-processing module, which is used to:
[0130] Before generating an activation signal and a voltage control signal according to the traversed test program, first data or second data is written into each of the storage cells; the first data is different from the second data.
[0131] In some embodiments, the detection module 1003 is used to:
[0132] Writing test data into the plurality of storage cells;
[0133] Storage data is read from the plurality of storage cells, and whether the target storage cell exists in the plurality of storage cells is determined according to the test data and the storage data.
[0134] In some embodiments, the detection module 1003 is used to:
[0135] If the storage data is the same as the test data, determining that the target storage unit does not exist in the plurality of storage units;
[0136] If the stored data is different from the test data, a storage unit corresponding to a bit position where the stored data and the test data are different is determined as the target storage unit.
[0137] It should be noted that the specific implementation contents of the signal generating module 1001, the processing module 1002 and the detecting module 1003 in the embodiment of the present disclosure can be referred to in Figures 1 to 9 The relevant contents in the illustrated embodiment will not be described in detail here.
[0138] It should be understood that in the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.
[0139] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0140] In addition, each functional module in each embodiment of the present disclosure may be integrated into one processing unit, each module may exist physically separately, or two or more modules may be integrated into one unit. The above modules may be implemented in the form of hardware or hardware plus software functional units.
[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A testing method, characterized in that: Applied to a memory, the memory comprises a plurality of word lines, a plurality of bit lines and a plurality of storage cells, each of the storage cells is connected to a corresponding one of the word lines and one of the bit lines; the method comprises: Traversing the test programs in the test program set, and generating an activation signal and a voltage control signal according to the traversed test programs; the test program set includes at least one test program; Activating some of the word lines in the plurality of word lines using the activation signal, and applying voltage to the plurality of bit lines using the voltage control signal; wherein there is at least one unactivated word line between two adjacent activated word lines, and there is a voltage difference between the voltages applied to any two adjacent bit lines; After traversing the test programs in the test program set, it is detected whether there is a target memory cell with a defect in the plurality of memory cells.
2. The method according to claim 1, characterized in that The test program set includes a first test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes: A first activation signal and a first voltage control signal are generated according to the traversed first test program; the first activation signal is used to activate even-numbered word lines among the multiple word lines, and the first voltage control signal is used to apply a first voltage to even-numbered bit lines among the multiple bit lines, and to apply a second voltage to odd-numbered bit lines among the multiple bit lines; there is a voltage difference between the first voltage and the second voltage.
3. The method according to claim 2, characterized in that The test program set also includes a second test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes: A second activation signal and a second voltage control signal are generated according to the traversed second test program; the second activation signal is used to activate the even-numbered word lines among the multiple word lines, and the second voltage control signal is used to apply the second voltage to the even-numbered bit lines among the multiple bit lines, and to apply the first voltage to the odd-numbered bit lines among the multiple bit lines.
4. The method according to claim 3, characterized in that The test program set also includes a third test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes: A third activation signal and a third voltage control signal are generated according to the traversed third test program; the third activation signal is used to activate odd-numbered word lines among the multiple word lines, and the third voltage control signal is used to apply the first voltage to even-numbered bit lines among the multiple bit lines, and to apply the second voltage to odd-numbered bit lines among the multiple bit lines.
5. The method according to claim 4, characterized in that The test program set also includes a fourth test program, and the generating of the activation signal and the voltage control signal according to the traversed test program includes: A fourth activation signal and a fourth voltage control signal are generated according to the traversed fourth test program; the fourth activation signal is used to activate odd-numbered word lines among the multiple word lines, and the fourth voltage control signal is used to apply the second voltage to even-numbered bit lines among the multiple bit lines, and to apply the first voltage to odd-numbered bit lines among the multiple bit lines.
6. The method according to any one of claims 2 to 5, characterized in that: The first voltage is a high voltage, and the second voltage is a low voltage.
7. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: After the holding time of the activation signal and the voltage control signal is equal to the preset time, the currently activated word line is turned off.
8. The method according to any one of claims 1 to 5, characterized in that: Before generating the activation signal and the voltage control signal according to the traversed test program, the method further includes: First data or second data is written into each of the storage units; the first data is different from the second data.
9. The method according to claim 1, characterized in that: The detecting whether there is a target memory cell with a defect in the plurality of memory cells comprises: Writing test data into the plurality of storage cells; Storage data is read from the plurality of storage cells, and whether the target storage cell exists in the plurality of storage cells is determined according to the test data and the storage data.
10. The method according to claim 9, characterized in that The determining, according to the test data and the storage data, whether the target storage unit exists in the plurality of storage units comprises: If the storage data is the same as the test data, determining that the target storage unit does not exist in the plurality of storage units; If the stored data is different from the test data, a storage unit corresponding to a bit position where the stored data and the test data are different is determined as the target storage unit.