Integrated circuit structure and manufacturing method thereof

Abstract

The present disclosure provides an integrated circuit (IC) structure comprising: a substrate having a circuit region and a chip corner region; an IC device formed on the substrate in the circuit region; a passivation layer formed over the IC device; and a polyimide layer formed over the passivation layer, in which the passivation layer and the polyimide layer include a stress relief pattern formed in the chip corner region. The embodiment of the invention also provides a method for manufacturing the integrated circuit structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit structures and methods for manufacturing the same. Background Art

[0002] In the semiconductor industry, integrated circuits (ICs) are formed on semiconductor substrates and sawn into IC chips. Each IC chip is further bonded to a circuit board, such as another IC chip, a carrier substrate, a plug-in, or a printed circuit board in an electronic product. The integrated circuits are then packaged using suitable packaging materials. However, the various materials of the IC chips and packaging components have different coefficients of thermal expansion (CTE), which may cause stress, die delamination, bump cracks, circuit failures, and other quality and reliability issues associated with CTE mismatch. Therefore, the present disclosure provides an IC structure and a method for manufacturing the same to address the above problems. Summary of the invention

[0003] According to one aspect of an embodiment of the present disclosure, an integrated circuit structure is provided, comprising: a substrate having a circuit area and a chip corner area; an integrated circuit device formed on the substrate within the circuit area; a passivation layer formed above the integrated circuit device; and a polyimide layer formed above the passivation layer, wherein the passivation layer and the polyimide layer include a stress release pattern formed in the chip corner area.

[0004] According to another aspect of an embodiment of the present disclosure, an integrated circuit structure is provided, comprising: a substrate; a plurality of semiconductor chips connected to the substrate and electrically connected to the substrate; and a bottom filling material filling the space between the semiconductor chips and the substrate, wherein the plurality of semiconductor chips include a first semiconductor chip, and wherein the first semiconductor chip includes: a semiconductor substrate having a circuit area and a chip corner area; an integrated circuit device formed on the semiconductor substrate within the circuit area; and a passivation layer formed above the integrated circuit device, wherein the passivation layer includes a stress release passivation pattern formed in the chip corner area.

[0005] According to another aspect of an embodiment of the present disclosure, a method for manufacturing an integrated circuit structure is provided, comprising: receiving a semiconductor substrate having a circuit area and a chip corner area; forming an integrated circuit device on the semiconductor substrate in the circuit area, and forming an interconnect structure above the integrated circuit device; forming a passivation layer above the interconnect structure; patterning the passivation layer to form a stress release passivation pattern in the chip corner area; forming a polyimide layer on the passivation layer; and patterning the polyimide layer to form a stress release polyimide pattern in the chip corner area, wherein the stress release passivation pattern is different from the stress release polyimide pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a cross-sectional view of an integrated circuit (IC) structure constructed according to various aspects of the present disclosure in some embodiments;

[0008] Figure 2A , Figure 2B ,and Figure 2C is a cross-sectional view of an IC structure at various stages of fabrication constructed in accordance with various aspects of the present disclosure in some embodiments;

[0009] Figure 3 is a flow chart of a method of manufacturing an IC structure according to some embodiments;

[0010] Figure 4 and Figure 5 is a top view of a portion of an IC structure constructed according to some embodiments;

[0011] Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A ,and Fig.14A is a top view of an IC structure during various stages of fabrication constructed in accordance with some embodiments;

[0012] Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B ,and Fig. 14B According to some embodiments, Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A ,and Fig.14A A cross-sectional view of an IC structure;

[0013] Fig.15 is a top view of a portion of an IC structure constructed in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. It should be understood that the following disclosure provides many different embodiments or examples for realizing the different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive.

[0015] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to easily describe the relationship of one element or component to another (or other) elements or components as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is flipped, elements described as "under" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "under" can cover both above and below directions. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0016] The disclosed device structure and the method for manufacturing the same relate to an integrated circuit (IC) structure, and in particular to a package structure having a design pattern for relieving stress and improving the yield of the package. The disclosed device structure includes various structural features and manufacturing steps for providing an overall structure for reducing stress and delamination in the package structure, in particular in a system-on-chip (SoC) flip-chip structure.

[0017] In the present disclosure, the IC structure is configured to add grooves or opening patterns to the packaging material, such as polyimide or silicon nitride of the passivation layer in the corner area, to release the corner stress, thereby improving the yield of the SoC flip chip (FC) package. These grooves or openings are called stress release patterns. The stress release pattern is arranged in the chip corner area (blocking zone, KOZ). The stress release pattern is defined on the photomask and transferred to the packaging material by photolithography and etching.

[0018] Figure 11 is a partial cross-sectional view of a portion or the whole of an IC structure 100 constructed according to some embodiments. The IC structure 100 includes a three-dimensional (3D) IC structure having multiple chips integrated in the same package. The IC structure 100 includes various IC chips integrated together in the package, such as a system on chip (SoC), a memory chip, other suitable chips, or a combination thereof. One or more chips of the IC structure include: a passivation structure having various components, parts, and materials, such as a passivation structure having one or more passivation layers; a bonding pad formed on the passivation layer; a redistribution layer (RDL) embedded in the RDL to redistribute the bonding pad; and a polyimide layer disposed on the passivation layer to provide a suitable sealing function. In addition, an underfill (UF) layer is formed to fill the gap between the chips. In some embodiments, the passivation structure includes a first passivation layer of silicon nitride, and a second passivation layer of silicon nitride having a silicon oxide layer (e.g., undoped silicon glass, USG). Polyimide is further formed on top and patterned to have an opening for bonding pads. These different materials typically have different coefficients of thermal expansion (CTE), which can introduce stress and cause delamination problems and IC structure failure. In the disclosed structure, a passivation layer, such as a second passivation layer of silicon nitride, is patterned in the chip corner area to have various grooves, openings, or a combination thereof to release stress and eliminate delamination. The polyimide layer can be further patterned in the chip corner area to have various grooves, openings, or a combination thereof to release stress and eliminate delamination. The chip corner area is an area in the chip corner where there is no integrated circuit, also known as a blocking zone (KOZ), which will be further described later.

[0019] refer to Figure 1According to various aspects of the present disclosure, an IC structure 100 is provided by arranging a chipset using a combination of multi-chip packaging technologies such as chip-on-wafer-on-substrate (CoWoS) packaging technology, system-on-integrated-chip (SoIC) multi-chip packaging technology, and integrated fan-out (InFO) packaging. The IC structure 100, which may be referred to as a 3D IC package and / or a 3D IC module, includes a CoW structure 102 connected to a substrate 104 (e.g., a packaging substrate). The CoW structure 102 includes a chipset (e.g., a memory chip 112-1, a memory chip 112-2, a system-on-chip (SOC) 114, which are electrically connected to each other and integrated together) connected to the substrate 104. In some embodiments, the chipset is arranged into one or more chip stacks, in which one chip is stacked on another chip. In the depicted embodiment, the chips are directly bonded face-to-face and / or face-to-back to provide a multi-chip packaged SoIC package. In some embodiments, the chip stack of the multi-chip package includes a combination of chip types, such as a core chip having one or more memory chips disposed thereon. For clarity, the Figure 1 , to better understand the inventive concept of the present disclosure. Additional features may be added to the multi-chip package, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multi-chip package.

[0020] Memory chip 112-1 and memory chip 112-2 are high bandwidth memory (HBM) chips, GDDR memory chips, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, magnetoresistive random access memory (MRAM) chips, resistive random access memory (RRAM) chips, other suitable memory chips, or combinations thereof. In some embodiments, memory chip 112-1 and memory chip 112-2 are HBM chips that form at least a portion of a memory device. In some embodiments, memory chip 112-1 and memory chip 112-2 are graphic double data rate (GDDR) memory chips that form at least a portion of a memory device. In some embodiments, memory chip 112-1 is an HBM chip, and memory chip 112-2 is a GDDR memory chip, or vice versa, which forms at least a portion of a memory device. In some embodiments, memory chip 112-1 and / or memory chip 112-2 represent a stack of memory dies that can be bonded and / or sealed in a manner that provides a memory package and / or a memory-based SoIC package. The memory package may be an HBM package (also referred to as an HBM cube) or a GDDR memory package.

[0021] SOC 104 is an integrated circuit chip that integrates all or part of the components of a computer or other electronic system. These components may include a central processing unit (CPU), memory interfaces, on-chip input / output devices, input / output interfaces, and auxiliary storage interfaces, radio modems, graphics processing units (GPUs), or combinations thereof on a single substrate. SOCs may contain digital, analog, mixed signal, radio frequency signal processing functions, or combinations thereof.

[0022] SOC chip 114, memory chip 112-1, and memory chip 112-2 are connected and / or interconnected to substrate 104. In some embodiments, substrate 104 is a plug-in. In a further implementation of the embodiment, the plug-in is connected and / or interconnected to the substrate below, such as a semiconductor substrate, a printed circuit board, or other suitable substrates. Various bonding mechanisms can be implemented in a multi-chip package, such as conductive bumps 116 (e.g., metal bumps), through-semiconductor vias (TSVs), bonding pads 118, or combinations thereof. For example, conductive bumps 116 physically and / or electrically connect memory chip 112-1 and memory chip 112-2 to substrate 104. In another example, bonding pads 118 physically and / or electrically connect SOC chip 114 to substrate 104. In some embodiments, the conductive bumps 116 connecting the chip and / or the chip stack can be micro-bumps, controlled collapse chip connections (referred to as C4 bonding) (e.g., solder bumps and / or solder balls), other suitable connection mechanisms, or combinations thereof.

[0023] The bottom fill material (or simply referred to as underfill or UF) 119 is further filled in the gap between the chip and the substrate, with a suitable sealing effect and mechanical strength. For example, UF 119 is distributed on the substrate 104 and drawn into the gap by capillary force. UF 119 may include one or more suitable bottom fill materials, such as curable polymer materials. An additional amount of bottom fill material can be applied along the edge of the chip to form a uniform fillet extending beyond the edge of the chip. The curable polymer material is then cured by a suitable method such as heating or ultraviolet (UV) energy to form a bottom filler. The bottom filler joins the chip, the support substrate 104 and the solder bumps to strengthen the assembly and protect the solder bumps from being damaged by the environment. In some embodiments, the bottom fill material includes one or more polymerizable monomers, polyurethane prepolymers, block copolymer components, radial copolymer components, initiators, catalysts, crosslinking agents, stabilizers, or combinations thereof.

[0024] In some embodiments, substrate 104 is a package substrate, such as a coreless substrate or a substrate with a core, which can be physically and / or electrically connected to another component through an electrical connector 120. Electrical connector 120 is electrically connected to conductive bumps 116 and bonding pads 118 through conductive routing structures (paths) 122 of substrate 104. In some embodiments, substrate 104 is an insert. In some embodiments, substrate 104 is a printed circuit board (PCB).

[0025] In some embodiments, the substrate 104 is a semiconductor substrate, such as a silicon substrate (which may be generally referred to as a silicon insert). In some embodiments, the substrate 104 is a laminate substrate, a core package substrate, a coreless package substrate, etc. In some embodiments, the substrate 104 may include an organic dielectric material, such as a polymer, which may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer-based materials, or a combination thereof. In some embodiments, a redistribution line (layer) (RDL) may be formed in the substrate 104, such as within the organic dielectric material of the substrate 104. The RDL may form a portion of the conductive wiring structure 122 of the substrate 104. In some embodiments, the RDL electrically connects a bonding pad on one side of the substrate 104 (e.g., the top side of the substrate 104 having a chipset connected thereto) to a bonding pad on the other side of the substrate 104 (e.g., the bottom side of the substrate 104). In some embodiments, the RDL electrically connects the bonding pads on the top side of the substrate 104, which may electrically connect the chips of the chipset. In some embodiments, the substrate 104 may be a semiconductor substrate having TSVs formed therein to provide electrical connections from the front side to the back side. The IC structure 100 may also include various active devices, passive devices, or combinations thereof formed on the substrate 104. For example, the IC structure 100 includes one or more large-scale integrated passive devices (LS-IPDs) 124 formed on the substrate 104 and electrically connected and integrated with other devices of the IC structure 100.

[0026] The IC structure 100 also includes other components, assemblies, and materials that are configured to form a package structure with various functions such as heat dissipation, sealing mechanisms, mechanical reinforcement, and / or combinations thereof. In particular, the IC structure 100 includes a cover 126 disposed above the chip (e.g., 112-1, 112-2, and 114). The cover 126 is a structure of a thermally conductive material having a heat dissipation function, and is integrated with the substrate 104 to seal the chip inside. For example, the cover 126 is designed to have a lower surface that conforms to the geometric contour of the chip integrated on the substrate 104, and has a flat top surface. In some embodiments, the cover 126 includes a material with high thermal conductivity, such as a thermally conductive material with a thermal conductivity ranging between 200W / m·K and 400W / m·K. In some embodiments, the cover 126 is made of metal, metal alloy, graphene, carbon nanotube (CNT), other suitable materials, or combinations thereof. In some embodiments, the cover 126 is made of aluminum, steel, copper, or alloys of these metals.

[0027] The cover 126 is fixed to the substrate 104 by a suitable mechanism, such as by one or more thermal interface material (TIM) components 128. In some embodiments, the TIM component 128 includes a polymer with good thermal conductivity, which has a thermal conductivity ranging between 2 W / m·K and 10 W / m·K. In some embodiments, the TIM component 128 has a thickness ranging between 50 μm and 100 μm. In some embodiments, the TIM can be applied to the surface of the cover 126 and / or the surface of the substrate 104 and cured by a suitable method such as ultraviolet (UV), heating, other suitable techniques, or a combination thereof.

[0028] The cover 126 is designed to have a suitable shape to connect to the chip and further fix the chip to the substrate 104. In some embodiments, the cover 126 is connected to the chip through a TIM component 128, other suitable materials, or a combination thereof, by a similar process. For example, the TIM is applied to the surface of the cover 126 and / or the surface of the chip, and is cured by a suitable method, such as UV, heating, other suitable techniques, or a combination thereof. When the cover 126 is fixed to the substrate 104 and the chip is sealed inside, empty spaces can be formed inside the seal, such as between the chips. These can further provide buffer spaces to reduce and release stress.

[0029] In some embodiments, the IC structure 100 may include other components, such as one or more fixtures 130 interposed between the substrate 104 and the cover 126. The fixtures 130 are designed to accommodate the cover 126 and provide more degrees of freedom to release the stress built up between the substrate 104 and the cover 126. In some embodiments, the fixtures 130 may use the same or similar materials as the materials of the cover 126, such as metals, metal alloys, graphene, CNTs, other suitable materials, or combinations thereof.

[0030] In some embodiments, by rearranging the chipset, the multi-chip package can be configured as a 2.5D IC package and / or a 2.5D IC module so that the substrate 104 is a plug-in and each chip is bonded and / or connected to the plug-in. In other words, the 2.5D IC module does not include a chip stack, and the chips of the chipset are arranged in a single plane. In some embodiments, by rearranging the chips to form one or more chipsets, the multi-chip package can be configured as a 3D IC package and / or a 3DIC module. In some embodiments, the substrate 104 is a semiconductor substrate on which various devices are formed, and the chips are bonded thereon. In addition, the substrate 104 includes an interconnect structure formed on the front side of the substrate, and may further include an interconnect structure formed on the back side of the substrate, and a TSV formed in the substrate to electrically connect the front interconnect structure and the back interconnect structure.

[0031] IC structure 100 may also include other devices, components, integrated functional units such as high density capacitors (HDP), optical ring resonators (ORR), inductors, imaging sensors, waveguides, other suitable devices, or combinations thereof distributed on substrate 104 and various chips (e.g., 112-1, 112-2, and 114). IC structure 100 may additionally or alternatively include other chips integrated in the same package.

[0032] In particular, the various chips of the IC structure 100 are integrated with suitable packaging structures to reduce and release stress, thereby eliminating delamination and other failure issues. Taking SOC 114 as an example, chip 114 is formed with various grooves and openings formed in the chip corner area, which will be further described below. Please note that all chips (such as chips 112-1, 112-2, and 114) or at least a subset of chips have similar structures to reduce stress.

[0033] Figure 2A and Figure 2B is a cross-sectional view of a portion or all of an IC structure 200 constructed in accordance with various aspects of the present disclosure at various stages of fabrication in one embodiment. Figure 3 is a flow chart of a method 300 of manufacturing an IC structure 200 according to some embodiments. Figure 2A , Figure 2B , Figure 3 , and others Figures 4 to 15 , together describe an IC structure 200 and a method 300 of manufacturing the IC structure 200. In some embodiments, the IC structure 200 is a semiconductor chip, such as the SOC chip 114 or the memory chip 112-1 or 112-2.

[0034] The IC structure 200 may include: a flat active area with various IC devices such as a planar field effect transistor (FET) formed thereon; a fin-shaped active area with various transistors formed thereon; or a plurality of vertically stacked channels with various transistors such as a full-all-around (GAA) FET formed thereon.

[0035] IC structure 200 includes substrate 202. Substrate 202 includes a bulk silicon substrate. Alternatively, substrate 202 may include: a base semiconductor, such as silicon or germanium in a crystal structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or a combination thereof. Possible substrates 102 also include silicon-on-insulator (SOI) substrates. SOI substrates are manufactured using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods.

[0036] The substrate 202 also includes various isolation features, such as an isolation feature 204 formed on the substrate 202, and defines various active areas on the substrate 202, such as an active area 206. The isolation feature 204 uses isolation technology such as shallow trench isolation (STI) to define and electrically isolate various active areas. The isolation feature 204 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof. The isolation feature 204 is formed by any suitable process. As an example, forming the STI feature includes: a photolithography process to expose a portion of the substrate; etching a trench in the exposed portion of the substrate (e.g., by using dry etching and / or wet etching); filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process); and planarizing the substrate by a polishing process such as a chemical mechanical polishing (CMP) process and removing excess portions of the dielectric material. In some examples, the filled trench can have a multi-layer structure, such as a thermal oxide liner layer, and a filling layer of silicon nitride or silicon oxide.

[0037] The active region 206 is a region having a semiconductor surface in which various doped components are formed and configured into one or more devices, such as diodes, transistors, and / or other suitable devices. The active region may include: a semiconductor material, a semiconductor material similar to the bulk semiconductor material of the substrate 202 (e.g., silicon); or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC); or multiple semiconductor material layers (e.g., alternative silicon and silicon germanium layers) formed on the substrate 202 by epitaxial growth for performance enhancement, such as strain effects to increase carrier mobility.

[0038] In some embodiments, the active region 206 is three-dimensional, such as a fin-shaped active region extending above the isolation feature 204. The fin-shaped active region protrudes from the substrate 202 and has a three-dimensional profile for a more efficient connection between the channel region (or simply the channel) and the gate electrode of the FET. The active region 206 can be formed by selectively etching to recess the isolation feature 204, or by selective epitaxial growth to grow an active region having a semiconductor that is the same as or different from the semiconductor of the substrate 202, or by a combination thereof.

[0039] The semiconductor substrate 202 also includes various doped components, such as n-type doped wells, p-type doped wells, sources and drains, other doped components, or combinations thereof, configured to form various devices or components of devices. The IC structure 200 includes various IC devices 210 formed on the semiconductor substrate 202. The IC devices include fin field effect transistors (FinFETs), diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. Figure 2A and Figure 2B In the example, only FET is provided for illustration.

[0040] The IC structure 200 also includes an interconnect structure 220 formed on the semiconductor substrate 202. The interconnect structure 220 includes various conductive components for connecting various IC devices to the integrated circuit. The interconnect structure 220 also includes an interlayer dielectric (ILD) layer 222 for separating and isolating the various conductive components. For example, the interconnect structure 220 includes a contact 224; a metal line 226; and a via 228. The metal line 226 is distributed in multiple metal layers. Figure 2A and Figure 2B, four metal layers are shown. The top metal lines are individually labeled with the number 230. The contact 224 provides a vertical circuit route from the semiconductor substrate 202 to the metal line. The through hole 228 provides a vertical circuit route between adjacent metal layers. Various conductive components are formed by one or more conductive materials such as metals, metal alloys, or silicides. For example, the metal line 226 may include copper, aluminum-copper alloys, other suitable conductive materials, or a combination thereof. The through hole 228 may include copper, aluminum-copper alloys, other suitable conductive materials, or a combination thereof. The contact 224 may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or a combination thereof. In some examples, the various conductive components may further include a barrier layer, such as tantalum and tantalum nitride, titanium and titanium nitride. In the present embodiment, the top metal line 230 includes copper.

[0041] The ILD layer 222 includes one or more dielectric materials to provide isolation functions to various device components (e.g., gates) and various conductive components (e.g., metal lines, contacts, and vias). The ILD layer 222 includes dielectric materials, such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some examples, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide, and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. The formation of the ILD layer 222 includes, for example, deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques, or combinations thereof. The ILD layer 222 may include multiple layers, and various conductive components may be formed together with appropriate procedures (e.g., inlay processes).

[0042] In some embodiments, the interconnect structure 220 or a portion thereof is formed by deposition and patterning. For example, a metal (or metal alloy), such as aluminum copper, is deposited by physical vapor deposition (PVD), and then patterned by photolithography and etching. Then an ILD layer is set thereon by deposition (and CMP). In some embodiments, the interconnect structure 220 uses a damascene process to form metal lines. In the damascene process, the ILD layer is deposited, the ILD layer can be further flattened by CMP, and then the ILD layer is patterned by photolithography and etching to form a groove. One or more conductive materials are deposited to fill the groove, and another CMP process is applied to remove excess conductive materials and flatten the top surface to form a conductive component. The damascene process can be used to form metal lines, vias, and contacts. A dual damascene process can be applied to form a layer of metal lines and vias adjacent to the metal lines. In this case, the ILD layer is deposited and patterned twice to form grooves and via openings, respectively. Then metal is deposited to fill both the grooves and via openings to form metal lines and vias.

[0043] The IC structure 200 also includes a passivation structure 240, which is disposed on the interconnect structure 220 and has a redistribution layer (RDL) for redistributing pads, such as from the edge to the center of the IC chip for flip chip bonding or other suitable packaging technology to integrate the IC chip into another chip (in a chipset) or board (e.g., a printed circuit board).

[0044] The passivation structure 240 includes a passivation member, and an RDL metal component 242 embedded in the passivation member and having a bonding pad 250 in an opening 252 of the passivation member, wherein the opening 252 will be formed at a later manufacturing stage. In the present embodiment, the passivation member includes a first passivation layer 244 and a second passivation layer 246 disposed on the first passivation layer 244. The first passivation layer 244 includes a redistribution via (RV) opening aligned with the top metal line 230, so that a portion 248 of the RDL metal component 242 is formed in the RV opening and directly contacts the top metal line 230. The portion 248 of the RDL metal component 242 is also referred to as the RV pad 248. The RDL metal component 242 extends vertically from the first passivation layer 244 to the second passivation layer 246, and horizontally extends from the RV pad 148 to the bonding pad 250 for pad redistribution.

[0045] In the present embodiment, the first passivation layer 244 includes a first silicon nitride (SiN) layer, and a first undoped silicon glass (USG) layer on the SiN layer; the second passivation layer 246 includes a second USG layer, and a second SiN layer disposed on the second USG layer. The RDL metal component 242 includes a plurality of layers. In the present embodiment, the RDL metal component 242 includes a barrier layer, a diffusion layer disposed on the barrier layer, and an aluminum-copper alloy layer disposed on the diffusion layer. The barrier layer may further include a tantalum film and a tantalum nitride film disposed on the tantalum film. The diffusion layer is a metal oxide. In the present embodiment, the diffusion layer includes tantalum, oxygen, aluminum, and nitrogen. The diffusion layer has a thickness ranging between 5 angstroms and 30 angstroms. The aluminum-copper alloy layer is formed at a high temperature above 300°C. The RDL structure 240, in particular the RDL metal component 242, is further described in the following description. In some embodiments, the first USG layer has a thickness ranging between 2000 angstroms and 4000 angstroms; and the first SiN has a thickness ranging between 2000 angstroms and 6000 angstroms. In some embodiments, the second USG layer has a thickness ranging between 2000 angstroms and 4000 angstroms; and the second SiN has a thickness ranging between 2000 angstroms and 6000 angstroms.

[0046] A polyimide layer 256 is formed on the passivation layer 246. The polyimide layer 256 provides protection for the circuit, such as protection from α-particles. The polyimide layer 256 is coated on the passivation layer 246 by a suitable process such as spin coating. A baking process can be implemented after spin coating. In addition, the polyimide layer 256 is designed to have desired mechanical properties to solve the cracking problem and further have manufacturing efficiency. In the present embodiment, the polyimide layer 256 is designed to have a composition in the final form after coating and patterning to have an enhanced tensile strength greater than 170 MPa, for example, in the range of 170 MPa to 200 MPa; and a Young's modulus greater than 4 GPa, for example, in the range of 4 GPa to 6 GPa. In a further implementation of the embodiment, the polyimide layer 256 includes greater than 40% (volume percentage, the same below) of aliphatic amide (AA) or γ-butyrolactone (GBL); and more than 25% of polyamic acid ester (PAE). In some examples, the polyimide layer 256 includes 50% to 60% AA and 30% to 40% PAE. In some examples, the polyimide includes 40% to 60% and 25% to 35% PAE. The polyimide layer 256 having such a composition can achieve the desired mechanical strength and the desired thickness. In addition, the polyimide also includes a photosensitive chemical substance so that it can be simply patterned by a photolithography process without etching. In some embodiments, the process for forming the polyimide layer 256 also includes pre-treating the passivation layer 246 (especially the silicon nitride layer of the passivation layer 246) using oxygen (O2) ashing to increase the adhesion between the polyimide layer 256 and the passivation layer 246.

[0047] The passivation layer 246 (or additional passivation layer 244) and the polyimide layer 256 are further patterned to form openings 252 for bonding pads, and openings (or trenches) 260 in chip corner regions 262 of the IC structure 200 for relieving and reducing stress. The openings 260 may partially penetrate the passivation structure, for example, through the passivation layer 246 but not through the passivation layer 244. The passivation layers 244, 246, and the polyimide layer 256 are patterned in any suitable order. In some embodiments, the passivation layer is patterned first, and then the polyimide layer 256 is patterned to form the openings 252 and 260. In this case, the passivation layer 246 is deposited and patterned, and then the polyimide layer 256 is deposited and patterned.

[0048] In some embodiments, the polyimide layer 256 is first patterned, and then the passivation layer is patterned to form openings 252 and 260 with continuous sidewalls, thereby improving the conditions for forming the bonding pad. This is because the patterned polyimide layer 256 now acts as an etching mask when the passivation layer is patterned, and the sidewalls of the patterned passivation layer 256 are restricted to be aligned with the sidewalls of the polyimide layer 256. In this case, the passivation layer 246 is deposited and the polyimide layer 256 is sequentially deposited, and then the polyimide layer 256 and the passivation layer 246 are sequentially patterned. In a further implementation of this embodiment, when the passivation layer is patterned, since the patterned polyimide layer 256 acts as an etching mask, the etching process is applied only by an additional photolithography process.

[0049] The process for patterning the passivation layer 246 includes a photolithography process and an etching process. A patterned mask is first formed by a photolithography process having an opening to define the area for the openings 252 and 260. The photolithography process may include photoresist coating, such as by spin coating; exposure process using photoresist sensitive radiation, such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light; and development to form a patterned photoresist layer. The photolithography process may also include other process steps, such as post-exposure baking (PEB) after the exposure process, and hard baking after the development process. The patterned mask may be a soft mask such as a photoresist, or alternatively a hard mask having any suitable composition. An etching process with an etchant is then applied to etch the passivation layer 246 to form openings 252 and 260 in the passivation layer 246. However, as mentioned above, when the polyimide layer 256 is first patterned, the photolithography process can be eliminated and the passivation layer 246 can be directly etched using the patterned polyimide layer 256 as an etching mask. In some embodiments in which the passivation structure includes two passivation layers, both the passivation layers 244 and 246 are patterned to form an opening 260 in the chip corner region 262, wherein the opening 260 penetrates the passivation layers 244 and 246. The etching process can be wet etching, dry etching, or a combination thereof. The etching process can include multiple etching steps, using corresponding etchants to selectively etch corresponding materials of the passivation layer, such as using an etchant containing hydrofluoric acid to selectively etch silicon oxide, and using an etchant containing phosphorous acid to selectively etch silicon nitride.

[0050] The etching process for patterning the polyimide layer 256 may include a photolithography process and an etching process. The photolithography process is similar to the photolithography process applied to the passivation layer. The etching process may be wet etching, dry etching, or a combination thereof. For example, the polyimide layer 256 is etched by using a plasma etching of a chemical gas containing oxygen, fluorine, or both (e.g., a gas containing O2, CF4, and CF6). In some embodiments, the polyimide layer 256 is designed to be photosensitive and patterned directly by a photolithography process. For example, the polyimide layer 256 includes various compositions as described above, and also includes a photosensitive chemical (e.g., a photoacid generator) and a solvent (e.g., an aqueous solvent or an organic solvent) all mixed together. When exposed to radiation energy such as UV, DUV, EUV light, the polyimide layer 256 undergoes a property change. Through a development process, this property change can be used to selectively remove the exposed portion of the polyimide layer, or alternatively remove the unexposed portion.

[0051] Thereafter, a conductive bump 258 is formed on the bonding pad 250 in the opening 252. The formation of the conductive bump 258 includes depositing various conductive materials using a suitable deposition technique to fill the opening 252. In some embodiments, the conductive bump 258 includes an under bump metallization (UBM), a copper layer, and a solder, such as Figure 2B as shown in .

[0052] The openings 260 may have different depths, shapes, sizes, duty cycles, configurations, or combinations thereof to optimize the stress relief effect, for example FIG. 6A to FIG. 14B For example, the opening 260 may extend through the polyimide layer 256, the second passivation layer 246, or through the first passivation layer 244. In other examples, the openings 260 in the polyimide layer 256 and the passivation layers 244, 246 are different in position, size, and shape, such as Figure 2C As shown in . Figure 2C is a top view of a portion of an IC structure 200 constructed in accordance with some embodiments. Figure 2C In FIG. 2 , the openings 260 formed in the polyimide layer 256 and the passivation layers 244 , 246 are different.

[0053] Figure 33 is a flow chart of a method 300 for manufacturing an IC structure 200 according to some embodiments. Some manufacturing details are provided above and are not repeated here. The method 300 includes: operation 301 for receiving or providing a semiconductor substrate having a circuit region and a chip corner region; operation 302 for forming an isolation feature 204 on the semiconductor substrate 202; operation 304 for forming various IC devices (e.g., FETs, diodes, passive devices, imaging sensors, memory cells, other suitable IC devices, or combinations thereof) on the semiconductor substrate 202; operation 306 for forming an interconnect structure 220 (e.g., contacts 224, metal lines 226, vias 228, and top metal lines 230) by a suitable method, such as a damascene process; and operation 308 for forming a passivation structure having an opening 260 (and an opening 252) and a polyimide layer 256. The method 300 may include other operations before, during, or after the above operations. The opening 260 formed in the passivation layer 246 (and the additional passivation layer 244) and the polyimide layer 256 is used below Figure 3 Method 308 in is further described.

[0054] Method 308 includes: operation 312, for forming a passivation layer 246 on semiconductor substrate 202; operation 314, for patterning the passivation layer 246 to form opening 260 (and opening 252); operation 316, for forming a polyimide layer 256; and operation 318, for patterning the polyimide layer 256 to extend the opening 260 (and opening 252). In some embodiments, the opening 252 and the opening 260 can be formed separately. The opening 260 is also referred to as a stress relief pattern. The stress relief patterns formed in the passivation layer and the polyimide layer can be different, and therefore are respectively referred to as a stress relief passivation pattern and a stress relief polyimide pattern. Since operation 314 for patterning the passivation layer 246 and operation 318 for patterning the polyimide layer 256 are implemented by a process including a photolithography process using a photomask and an etching process, the stress relief passivation pattern and the stress relief polyimide pattern can be appropriately adjusted by adjusting the corresponding patterns defined on the corresponding photomasks.

[0055] refer to Figure 4 The opening 260 and the chip corner region 262 are further described. Figure 42 is a top view of a portion of an IC structure 200 constructed according to some embodiments. Chip 200 may include edges along an X direction and a Y direction, respectively. The X direction and the Y direction are perpendicular to each other. In particular, an opening 260 is shown. As mentioned above, IC structure 200 is a chip, such as chip 114, 112-1, or 112-2. IC structure 200 includes a circuit area 266 and a chip corner area 262. Opening 260 is designed to release stress and is formed on chip corner area 262. Chip corner area 262 may have a size Dc ranging between 50 μm and 100 μm. Opening 260 may have any suitable shape, such as a square opening, a circular opening, an elongated groove, or a combination thereof.

[0056] Figure 52 is a top view of a portion of an IC structure 200 constructed according to some embodiments. A chip corner region 262 is also referred to as a blocking zone (KOZ) or a chip corner circuit forbidden (CCCF) region. The chip corner region 262 is located in a corner of the IC structure 200. Devices of the integrated circuit are excluded from the KOZ 262 because it is an area that may experience greater stress during and after back-end processing (e.g., chip sawing and packaging). The chip corner region 262 may include a dummy metal pattern 340 for chip corner stress relief. The dummy metal pattern 340 may include a first corner stress relief (CSR) region 342, and may further include a second CSR region 344. The first CSR region and the second CSR region (342 and 344) may be positioned within the chip corner region 262 to be close to each other, and configured such that the first CSR region 342 is closest to the outline of the chip corner region 262, and the second CSR region 344 is closest to the integrated circuit region 266. An exemplary shape of the first CSR region 342 may be designed to substantially occupy a triangular area, preferably a right triangle, in the chip corner region 262. An exemplary shape of the second CSR region 344 may be designed to substantially occupy a parallelepiped area or a trapezoidal area in the chip corner region 262. Exemplary dimensions of the first CSR region 342 may have profiles L1 and L2 ranging from about 50 μm to about 150 μm. Exemplary dimensions of the second CSR region 344 may have profiles L3 and L4 ranging from about 50 μm to about 200 μm. The chip corner region 262 may further include a portion of a sealing ring 350. For sealing effect and stress release, the sealing ring 350 and the dummy metal pattern 340 are formed in the same level as the interconnect structure 220. The opening 260 is formed in the passivation structure 240 and the polyimide layer 256. In previous designs, the registration features and the chip corner region were designed separately and positioned at different locations of the chip. Therefore, circuit layout and placement are affected by the resulting available chip surface area, and the maximum chip area utilization is limited. In the above described structure, the corner stress relief pattern and the registration features are combined and co-located to maximize the chip effective area available for circuit layout.

[0057] The alignment feature 360 ​​may be formed within the chip corner region 262. This combined structure having the alignment feature 360 ​​co-located with the first CSR region 342, the second CSR region 344, and / or the seal ring 350 may use the chip area more efficiently and save more chip area for the integrated circuit layout. The alignment feature 360 ​​may include a laser fuse mark, such as a commonly used L-shaped mark (L mark). The laser fuse mark may implement a structure having a reverse tone composition, wherein the laser fuse mark includes a first material and the surrounding area includes a second material different from the first material, so that the laser fuse mark has a high contrast for alignment identification. For example, the laser fuse mark may include a dielectric material and the surrounding area includes a metal material. The dielectric material used to form the laser fuse mark may include silicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG), a low-k material, or a combination thereof. The laser fuse mark may be disposed within the top metal layer and, alternatively, may be further extended to the substrate. The dummy metal pattern 340 in the chip corner region 262 may be fabricated simultaneously with the interconnect structure 220 in the circuit region 266 using methods such as a dual damascene process. In one embodiment, the dummy metal pattern 340 may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or a combination thereof. The dummy metal pattern 340 may be formed using a dual damascene process.

[0058] The sealing ring 350 and the dummy metal pattern 340 in the chip corner area 262 are formed in the same layer as the interconnect structure 220 for sealing effect and stress release, while the opening 260 in the chip corner area 262 is formed in the passivation structure 240 and the polyimide layer 256. The opening 260 can have different depths, shapes, sizes, duty cycles, configurations, or combinations thereof to optimize the effect of stress release. For example, the opening 260 can extend through the polyimide layer 256, the second passivation layer 246, or further through the first passivation layer 244. In other examples, the openings 260 in the polyimide layer 256 and the passivation layers 244, 246 are different in position, size, and shape, for example FIG. 6A to FIG. 14B Those shown in .

[0059] FIG. 6A to FIG. 14A is a top view of a portion of the IC structure 200, FIG. 6B to FIG. 14B According to various embodiments, the FIG. 6A to FIG. 14A BB′ is a cross-sectional view of a portion of the IC structure 200 .

[0060] refer to Fig. 6A and Figure 6B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2CIn the embodiment of the present invention, the passivation structure 240 includes a first SiN layer 240A, a USG layer 240B located above the first SiN layer 240A, and a second SiN layer 240C located above the USG layer 240. Various openings are formed in the polyimide layer 256 and the passivation structure 240, and are referred to as 256-O, 240-1, 240-2, and 240-3, respectively. In the Figure 6B In the top views shown above and below, polyimide layer 256 is shown as transparent so that underlying components can be seen in those figures.

[0061] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig. 6A The polyimide layer 256 is composed of Fig. 6A The dashed box in FIG. 2 indicates that the other lower material layers of the passivation structure 240 are Fig. 6A As can be seen in FIG. 2 . The opening 256-O of the polyimide layer 256 is designed to cancel the vertex, and the sharp corner of the polyimide layer 256 is recessed, wherein the inclined edge 268 is not parallel to any chip edge. The inclined edge 268 of the polyimide layer 256 is greater than 10 μm away from the vertex of the second passivation layer 240C. This can effectively reduce the stress between the polyimide layer 256 and the passivation structure 240.

[0062] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1, trenches 240-2 and 240-3. The opening 240-1 of the passivation structure 240 overlaps with the opening 256-O of the polyimide layer 256, but the shapes are different, such as Fig. 6A In particular, the opening 240-1 of the passivation structure 240 includes a vertex spaced apart from the inclined edge 268 of the polyimide layer 256. In particular, the opening 240-1 extends to the USG layer 240B and can reduce the thickness of the USG layer 240B in the edge region, such as Figure 6B as shown in .

[0063] In the present embodiment, the passivation structure 240 is patterned to have grooves 240-2 and 240-3 in the chip corner area 262. The grooves 240-2 and 240-3 are arranged in parallel. Each of the two grooves 240-2 and 240-3 includes three sections, one of which is parallel to the inclined edge 268 of the polyimide layer 256, and the other two sections are parallel to the corresponding chip edges. These three parts are connected to form a continuous groove structure. The grooves 240-2 and 240-3 of the passivation structure 240 extend to the first SiN layer 240A, so that the first SiN layer 240A is exposed together with the grooves 240-2 and 240-3. In some embodiments, the two grooves 240-2 and 240-3 span the same width. In some embodiments, the two grooves 240-2 and 240-3 have a spacing greater than the width of the groove 240-2 (or the groove 240-3).

[0064] These openings are formed to have a suitable size to effectively release stress. In some embodiments, each of these openings has a size greater than 2 μm. For example, grooves 240-2 and 240-3 have a size greater than 2 μm. Each section of grooves 240-2 and 240-3 has a length greater than 10 μm. In another example, opening 240-1 has a width greater than 10 μm. In yet another example, opening 256-O has a width greater than 10 μm.

[0065] refer to Fig. 7A and Figure 7B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig. 7A and Figure 7B The IC structure 200 is similar to Fig. 6A and Figure 6B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-O, 240-1, and 240-O, respectively.

[0066] In this embodiment, the polyimide layer 256 is patterned to have an opening 256-O on the edge of the chip corner region 262, similar to Fig. 6A and Figure 6B For example, the opening 256-O of the polyimide layer 256 is designed to have an inclined edge 268 that is not parallel to any chip edge. The inclined edge 268 of the polyimide layer 256 is spaced apart from the vertex of the second passivation layer 240C by a dimension greater than 10 μm.

[0067] In the present embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a plurality of openings 240-O. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0068] In the present embodiment, instead of forming the grooves 240-2 and 240-3 of the passivation structure 240 in the chip corner region 262, a plurality of openings 240-O may be formed in the passivation structure 240. Those openings 240-O of the passivation structure 240 are different from the grooves 240-2 and 240-3. Each of the openings 240-O includes substantially the same dimensions Dx and Dy along the X and Y directions, or Dx=Dy=D. For example, the openings 240-O are circular, square, or a combination thereof. The openings 240-O are distributed, sized, and configured in a manner that effectively releases stress. In some embodiments, the dimensions D of the openings 240-O are different, for example, where D gradually increases toward the inclined edge 268. In some embodiments, the openings 240-O are regularly configured in terms of size and position. For example, the openings 240-O have the same dimension D and are regularly configured in two lines, emulating Fig. 6A and Figure 6B In a further implementation of this example, the dimension D is equal to the width W of the trenches 240 - 2 and 240 - 3 . In this embodiment, the dimension D is greater than 2 μm.

[0069] refer to Fig. 8A and Figure 8B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig. 8A and Figure 8B The IC structure 200 is similar to Fig. 6A and Figure 6B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-0, 240-1, and 240-4, respectively.

[0070] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig. 8A The opening 256-O of the polyimide layer 256 is similar to Fig. 6A and Figure 6B Opening 256-O in.

[0071] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a groove 240-4. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0072] In the present embodiment, the passivation structure 240 is patterned to have a groove 240-4, which is similar to Fig. 6A and Figure 6B However, the groove 240-4 is wider than Fig. 6A and Figure 6B 2 and 240-3 in the passivation structure 240. The groove 240-4 includes three sections, one of which is parallel to the inclined edge 268 of the polyimide layer 256, and the other two sections are parallel to the corresponding chip edges along the X and Y directions. The three parts are connected to form a continuous groove structure. The groove 240-4 spans laterally between the edge of the polyimide layer 256 (including the inclined edge 268) and the edge of the circuit area 266. The groove 240-4 of the passivation structure 240 extends vertically to the first SiN layer 240A, so that the first SiN layer 240A is exposed together with the groove 240-4. In some embodiments, the groove 240-4 has a size greater than 2μm. For example, the groove 240-4 has a size greater than 20μm from the inclined edge 268 to the edge of the circuit area 266.

[0073] refer to Fig. 9A and Fig. 9B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig. 9A and Fig. 9B The IC structure 200 is similar to Fig. 8A and Figure 8B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-0, 240-1, and 240-5, respectively.

[0074] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig. 9A The opening 256-O of the polyimide layer 256 is similar to Fig. 6A and Figure 6B Opening 256-O in.

[0075] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a groove 240-5. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0076] Groove 240-5 is similar to Fig. 8A and Figure 8B The groove 240-4 in the passivation structure 240 is formed by a groove 240-5. The groove 240-5 includes three sections, one of which is parallel to the inclined edge 268 of the polyimide layer 256, and the other two sections are parallel to the corresponding chip edges along the X and Y directions. The three sections are connected to form a continuous groove structure. The groove 240-5 of the passivation structure 240 extends vertically to the first SiN layer 240A, so that the first SiN layer 240A is exposed together with the groove 240-4. However, the groove 240-5 is narrower than Fig. 8A and Figure 8B 268. In particular, the groove 240-5 extends laterally to the edge of the polyimide layer 256 (including the inclined edge 268), but is spaced apart from the edge of the circuit area 266. In some embodiments, the groove 240-5 of the passivation structure 240 has a uniform width W5 greater than 10 μm. For example, the groove 240-5 has a dimension greater than 20 μm from the inclined edge 268 to the edge of the circuit area 266.

[0077] refer to Fig. 10A and Fig. 10B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262 , and the openings formed therein, which are designed to reduce and release stress. Fig. 10A and Fig. 10B The IC structure 200 is similar to Fig. 6A and Figure 6B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-O, 240-1, 240-2, and 240-3, respectively.

[0078] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig. 10A The opening 256-O of the polyimide layer 256 is similar to Fig. 6A and Figure 6B Opening 256-O in.

[0079] In the present embodiment, the passivation structure 240 is patterned to have an opening 240-1, trenches 240-2 and 240-3. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0080] Grooves 240-2 and 240-3 are similar to Fig. 6A and Figure 6B The trenches 240-2 and 240-3 in FIG. 1 are similar to those in FIG. 1 , but have different widths W2 and W3, and in particular, W3 is greater than W2. In some embodiments, each of W2 and W3 is greater than 10 μm. In some embodiments, the ratio W3 / W2 is greater than 1.2.

[0081] refer to Fig.11A and Fig. 11B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig.11A and Fig. 11B The IC structure 200 is similar to Fig. 8A and Figure 8B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-0, 240-1, and 240-6, respectively.

[0082] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig.11A The opening 256-O of the polyimide layer 256 is similar to Fig. 6A and Figure 6B Opening 256-O in.

[0083] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a groove 240-6. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0084] Groove 240-6 is similar to Fig. 8A and Figure 8B However, groove 240-6 is only Fig. 8A and Figure 8B266. The groove 240-6 includes only a section that spans laterally between the inclined edge 268 of the polyimide layer 256 and the edge of the circuit area 266. The groove 240-6 of the passivation structure 240 extends vertically to the first SiN layer 240A, so that the first SiN layer 240A is exposed together with the groove 240-6. In some embodiments, the groove 240-6 has a size greater than 2 μm. For example, the groove 240-6 has a size greater than 20 μm from the inclined edge 268 to the edge of the circuit area 266.

[0085] refer to Fig. 12A and Fig. 12B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig. 12A and Fig. 12B The IC structure 200 is similar to Fig. 8A and Figure 8B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-0, 240-1, and 240-7, respectively.

[0086] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig. 12A The opening 256-O of the polyimide layer 256 is similar to Fig. 6A and Figure 6B Opening 256-O in.

[0087] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a groove 240-7. The opening 240-1 of the passivation structure 240 is similar to Fig. 6A and Figure 6B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0088] Groove 240-7 is similar to Fig. 6A and Figure 6B2, 240-3 in the circuit area 266. However, the groove 240-7 is configured differently. The groove 240-7 includes a plurality of grooves that are designed to be straight and configured to be parallel to each other. The number, width, length, and spacing between the grooves 240-7 are optimized to maximize the effect of stress release. In the disclosed embodiment, the number of grooves 240-7 is 4, but it can be any suitable number, such as 3 or 5. The lengths of the grooves 240-7 are different. Each of the grooves 240-7 spans between the edge of the polyimide layer 256 (including the inclined edge 268) and the edge of the circuit area 266 (including the inclined edge), so that one of the side ends of the groove 240-7 is aligned and the other side end is not aligned. In some embodiments, the grooves 240-7 are uniformly configured to have the same width W and the same spacing S. In a further implementation of the embodiment, the width W and the spacing S are equal, which is equivalent to W=S. In some embodiments, W or S is greater than 1μm. In some embodiments, the trench 240 - 7 has a length ranging between 5 μm and 20 μm.

[0089] refer to Fig.13A and Fig. 13B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig.13A and Fig. 13B The IC structure 200 is similar to Fig. 12A and Fig. 12B . However, the inclined edge of the polyimide layer 256 is eliminated. Instead, the polyimide layer 256 has an edge along the X or Y direction. For simplicity, similar descriptions are repeated.

[0090] refer to Fig.14A and Fig. 14B , the IC structure 200 only shows the passivation structure 240 and the polyimide layer 256 in the chip corner region 262, and the openings formed therein (in Figure 2A-2C These openings are designed to reduce and release stress. Fig.14A and Fig. 14B The IC structure 200 is similar to Fig. 12A and Fig. 12B 2. The IC structure 200 in FIG. 2 is shown in FIG. 2. For simplicity, similar descriptions are repeated. Various openings 260 are formed in the polyimide layer 256 and the passivation structure 240 and are referred to as 256-0, 240-1, and 240-8, respectively.

[0091] In the present embodiment, the polyimide layer 256 is patterned to have an opening 256 -O on the edge of the chip corner region 262 . At the same time, the polyimide layer 256 is filled with Fig.14A The opening 256-O of the polyimide layer 256 is similar to Fig. 12A and Fig. 12B Opening 256-O in.

[0092] In this embodiment, the passivation structure 240 is patterned to have an opening 240-1 and a groove 240-8. The opening 240-1 of the passivation structure 240 is similar to Fig. 12A and Fig. 12B The opening 240 - 1 of the passivation structure 240 is formed in the vicinity of FIG.

[0093] Groove 240-8 is similar to Fig. 12A and Fig. 12B The groove 240-7 in the polyimide layer 256. The groove 240-8 includes a plurality of grooves that are designed to be straight and configured to be parallel to each other. However, the groove 240-8 is configured differently, specifically, parallel to the inclined edge 268 of the polyimide layer 256. The number, width, length, and spacing between the grooves 240-8 are optimized to maximize the effect of stress release. In the disclosed embodiment, the number of grooves 240-8 is 4, but it can be any suitable number, such as 3 or 5. The lengths of the grooves 240-8 are different. Each of the grooves 240-7 spans between the first edge (along the X direction) and the second edge (along the Y direction) of the polyimide layer 256, so that both ends of the groove 240-8 are not aligned. In some embodiments, the grooves 240-7 are uniformly configured to have the same width W and the same spacing S. In a further implementation of the embodiment, the width W and the spacing S are equal, equivalent to W=S. In some embodiments, W or S is greater than 1μm. In some embodiments, the trench 240 - 7 has a length ranging between 10 μm and 20 μm.

[0094] Fig.15 2 is a top view of a portion of IC structure 200 constructed according to some embodiments. In particular, polyimide layer 256 includes openings 256-O on chip corner regions 262, but also includes openings 256-O in circuit regions 266 for conductive bumps 258 (eg, Figure 2B ) of the opening 280 (as shown in Figure 2A252 in FIG. 25). The opening 280 of the polyimide layer 256 for the conductive bump 258 in the circuit area 266 is also designed to have a suitable shape and size for stress release. In some embodiments, the opening 280 of the polyimide layer 256 in the circuit area 266 can have an adjusted shape, such as a circle, a square, a rectangle, or a rectangle with rounded corners, to reduce stress and effectively release stress. In some embodiments, the ratio of the length Lp to Wp is greater than 2, such as 3, or ranges between 2.2 and 4.

[0095] The polyimide layer 256 has a thickness T p It is also adjusted to reduce stress or release stress, for example, thicker than the thickness T of the bottom filler 119. u In some embodiments, T p / T u The ratio ranges between 4 and 5.

[0096] The present disclosure provides an IC structure and a method for manufacturing the same in various embodiments. In particular, the IC structure includes a packaging structure having a design pattern for releasing stress and improving the yield of the package. The disclosed IC structure includes various structural components and manufacturing steps to provide an overall structure to reduce stress and delamination in the packaging structure in the package, especially in the system-on-chip (SoC) flip chip structure. In the present disclosure, the IC structure is configured to add a groove or opening pattern to the packaging material, such as the polyimide or silicon nitride of the passivation layer in the corner area of ​​the chip, to release the corner stress, thereby improving the yield of the SoC flip chip (FC) package. These grooves or openings are called stress release patterns. The stress release pattern is arranged in the corner area of ​​the chip (blocking zone, KOZ). The stress release pattern is defined on a photomask and transferred to the packaging material by a photolithography process and etching. The disclosed IC structure and the method for manufacturing the same can effectively reduce stress, release stress, and eliminate delamination failure.

[0097] In one example aspect, the present disclosure provides an integrated circuit (IC) structure comprising: a substrate having a circuit area and a chip corner area; an IC device formed on the substrate within the circuit area; a passivation layer formed above the IC device; and a polyimide layer formed above the passivation layer, wherein the passivation layer and the polyimide layer include a stress release pattern formed in the chip corner area.

[0098] In some embodiments, the substrate includes a first edge along a first direction, and a second edge along a second direction perpendicular to the first direction; the chip corner region is defined in a corner between the first edge and the second edge; and the polyimide layer includes an opening in the chip corner region, the opening having an inclined edge that is not parallel to any direction in the first direction and the second direction.

[0099] In some embodiments, the stress relief pattern includes a plurality of trenches formed in the passivation layer, and wherein the passivation layer includes a first silicon nitride layer, an undoped silicon glass layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon glass layer.

[0100] In some embodiments, each of the trenches extends to the first silicon nitride layer.

[0101] In some embodiments, each of the grooves includes a first segment parallel to the sloped edge.

[0102] In some embodiments, each of the trenches includes a second segment parallel to the X direction, and a third segment parallel to the Y direction, and the first segment, the second segment, and the third segment form a continuous trench.

[0103] In some embodiments, the grooves are straight grooves that are parallel to each other.

[0104] In some embodiments, the grooves are parallel to the X-direction.

[0105] In some embodiments, the groove is parallel to the sloped edge.

[0106] In some embodiments, the stress relief pattern includes a plurality of circular holes formed in the passivation layer in the chip corner region.

[0107] In another exemplary aspect, the present disclosure provides an integrated circuit (IC) structure, comprising: a substrate; a plurality of semiconductor chips connected to the substrate and electrically connected to the substrate; and an underfill material filling the space between the semiconductor chip and the substrate. The plurality of semiconductor chips include a first semiconductor chip. The first semiconductor chip includes: a semiconductor substrate having a circuit area and a chip corner area; an IC device formed on the semiconductor substrate in the circuit area; and a passivation layer formed above the IC device, wherein the passivation layer includes a stress release passivation pattern formed in the chip corner area.

[0108] In some embodiments, the integrated circuit structure further includes: a cover portion disposed above the semiconductor chip and fixed to the substrate, wherein the semiconductor chip is surrounded by the cover portion and the substrate.

[0109] In some embodiments, the substrate includes a first surface and a second surface opposite to the first surface, wherein the semiconductor chip is connected to the first surface of the substrate, and wherein the integrated circuit structure further includes a large-scale integrated passive device formed on the second surface of the substrate.

[0110] In some embodiments, the first semiconductor chip further includes: a polyimide layer formed over the passivation layer; and wherein the polyimide layer includes a stress-releasing polyimide pattern formed in a chip corner region.

[0111] In some embodiments, the first semiconductor chip includes a first edge along a first direction, and a second edge along a second direction perpendicular to the first direction; a chip corner region is defined in a corner between the first edge and the second edge; and a stress-releasing polyimide pattern of the polyimide layer includes an opening in the chip corner region, the opening having an inclined edge that is not parallel to any direction in the first direction and the second direction.

[0112] In some embodiments, the stress relief passivation pattern includes a plurality of trenches formed in the passivation layer, and wherein the passivation layer includes a first silicon nitride layer, an undoped silicon glass layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon glass layer.

[0113] In some embodiments, each of the grooves includes: a first segment parallel to the inclined edge; a second segment parallel to the first direction; and a third segment parallel to the second direction, wherein the first segment, the second segment, and the third segment form a continuous groove.

[0114] In some embodiments, the grooves are straight grooves parallel to each other, and wherein the grooves are parallel to the sloped edge.

[0115] In yet another example aspect, the present disclosure provides a method for manufacturing an integrated circuit (IC) structure. The method includes: receiving a semiconductor substrate having a circuit region and a chip corner region; forming an IC device on the semiconductor substrate in the circuit region, and forming an interconnect structure above the IC device; forming a passivation layer above the interconnect structure; patterning the passivation layer to form a stress relief passivation pattern in the chip corner region; forming a polyimide layer on the passivation layer; and patterning the polyimide layer to form a stress relief polyimide pattern in the chip corner region, wherein the stress relief passivation pattern is different from the stress relief polyimide pattern.

[0116] In some embodiments, a semiconductor substrate includes a first edge along a first direction, and a second edge along a second direction perpendicular to the first direction; a chip corner region is defined in a corner between the first edge and the second edge; a patterned polyimide layer includes a patterned polyimide layer to form a stress release polyimide pattern having an opening, the opening having an inclined edge that is not parallel to any direction in the first direction and the second direction; and a patterned passivation layer includes a patterned passivation layer to form a stress release passivation pattern having a plurality of grooves parallel to the inclined edges.

[0117] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit structure, comprising: A substrate having a circuit region and a chip corner region; an integrated circuit device formed on the substrate in the circuit region; a passivation layer formed above the integrated circuit device; as well as A polyimide layer is formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress release pattern formed in the chip corner region.

2. The integrated circuit structure according to claim 1, wherein: The substrate comprises a first edge along a first direction, and a second edge along a second direction perpendicular to the first direction; The chip corner region is defined in a corner between the first edge and the second edge; and The polyimide layer includes an opening in the chip corner region, the opening having an inclined edge that is not parallel to any direction of the first direction and the second direction.

3. The integrated circuit structure according to claim 2, wherein: The stress release pattern includes a plurality of grooves formed in the passivation layer, and wherein the passivation layer includes a first silicon nitride layer, an undoped silicon glass layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon glass layer.

4. The integrated circuit structure according to claim 3, wherein: Each of the trenches extends to the first silicon nitride layer.

5. The integrated circuit structure according to claim 1, wherein: The stress relief pattern includes a plurality of circular holes formed in the passivation layer in the chip corner region.

6. An integrated circuit structure comprising: substrate; a plurality of semiconductor chips connected to the substrate and electrically connected to the substrate; as well as an underfill material filled in a space between the semiconductor chip and the substrate, wherein the plurality of semiconductor chips include a first semiconductor chip, and wherein the first semiconductor chip includes: A semiconductor substrate having a circuit region and a chip corner region; an integrated circuit device formed on the semiconductor substrate in the circuit region; and A passivation layer is formed above the integrated circuit device, wherein the passivation layer includes a stress release passivation pattern formed in the chip corner region.

7. The integrated circuit structure according to claim 6, further comprising: A cover is disposed above the semiconductor chip and fixed to the substrate, wherein the semiconductor chip is surrounded by the cover and the substrate.

8. The integrated circuit structure according to claim 6, wherein: The first semiconductor chip further includes: a polyimide layer formed over the passivation layer; and wherein the polyimide layer includes a stress-releasing polyimide pattern formed in the chip corner region.

9. The integrated circuit structure according to claim 8, wherein: The first semiconductor chip includes a first edge along a first direction, and a second edge along a second direction perpendicular to the first direction; The chip corner region is defined in a corner between the first edge and the second edge; and The stress-relieving polyimide pattern of the polyimide layer includes an opening in the chip corner region, the opening having an inclined edge that is not parallel to any of the first direction and the second direction.

10. A method of manufacturing an integrated circuit structure, comprising: receiving a semiconductor substrate having a circuit region and a chip corner region; forming an integrated circuit device on the semiconductor substrate in the circuit region, and forming an interconnect structure above the integrated circuit device; forming a passivation layer over the interconnect structure; patterning the passivation layer to form a stress-relieving passivation pattern in the chip corner region; forming a polyimide layer on the passivation layer; as well as The polyimide layer is patterned to form a stress-releasing polyimide pattern in the chip corner region, wherein the stress-releasing passivation pattern is different from the stress-releasing polyimide pattern.

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