Chip packaging structure and preparation method thereof

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, and the structure comprises a circuit layer group which comprises a first circuit layer and a second circuit layer which are horizontally disposed, and the second circuit layer is disposed right above the first circuit layer; the first circuit layer and the second circuit layer are electrically connected through the plurality of metal columns; the chipset is arranged between the first circuit layer and the second circuit layer and comprises a first-layer chip and a second-layer chip, the front surface of the first-layer chip is in bonding connection with the upper surface of the first circuit layer, and the back surface of the second-layer chip is stacked on the back surface of the first-layer chip; the front surface of the second-layer chip is electrically connected with the second circuit layer through the exposed metal columns; and the space between the first circuit layer and the second circuit layer is filled with the plastic package structure. According to the chip packaging structure provided by the invention, more chips can be mounted in the packaging space with a specific size, so that the requirement of the market on the mounting quantity of the chips in the chip packaging structure is met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a preparation method thereof. Background Art

[0002] In a traditional chip packaging structure, only a single-layer chip can be set between the upper and lower circuit layers in a packaging structure. However, as the market demand for the number of chips installed in the chip packaging structure increases, the traditional chip packaging structure can no longer meet the needs of installing more chips in a packaging space of a specific size.

[0003] Therefore, the present application develops a chip packaging structure and a preparation method thereof to solve the above problems. Summary of the invention

[0004] The present invention provides a chip packaging structure and a preparation method thereof to solve the problem that the existing chip packaging structure can no longer meet the requirement of installing more chips in a specific packaging space.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions: The present invention provides a chip packaging structure, comprising: A circuit layer group, comprising a first circuit layer and a second circuit layer arranged horizontally, wherein the second circuit layer is arranged directly above the first circuit layer; Metal pillars, the first circuit layer and the second circuit layer are electrically connected through a plurality of the metal pillars; A chipset, the chipset is arranged between the first circuit layer and the second circuit layer, the chipset comprises a first layer chip and a second layer chip, the front surface of the first layer chip is bonded to the upper surface of the first circuit layer, the back surface of the second layer chip is stacked on the back surface of the first layer chip, and the front surface of the second layer chip is electrically connected to the second circuit layer through an exposed metal column; A plastic packaging structure fills the space between the first circuit layer and the second circuit layer.

[0006] Furthermore, the first layer of chips includes at least two first chips arranged in a flat pattern, and the second layer of chips includes at least one second chip, and the back sides of both ends of the second chip are respectively stacked on the front sides of the adjacent ends of two adjacent first chips.

[0007] Furthermore, a BGA packaging device is disposed on the lower surface of the first circuit layer, and the BGA packaging device is electrically connected to the first circuit layer.

[0008] Furthermore, a base layer is electrically connected below the BGA packaged device.

[0009] Furthermore, the chips in the chipset are all functional chips, the upper surface of the second circuit layer is electrically connected to a packaged chip, and the chips in the packaged chip are computing chips.

[0010] Preferably, the metal column is a copper column, and tin, silver or alloy columns can also be used.

[0011] Furthermore, a layer of bare chips is electrically connected to the upper surface of the second circuit layer.

[0012] The present invention also provides a method for preparing a chip packaging structure, comprising: Processing a first circuit layer on the substrate by a redistribution layer process or a substrate bonding process; Processing a plurality of metal pillars electrically connected to the first circuit layer on the upper surface of the first circuit layer by through-molding via technology; Connecting the front surface of the first layer chip to the upper surface of the first circuit layer through a chip bonding process on the first circuit layer; Stacking a second layer of chips on the back side of the first layer of chips, with the first layer of chips and the second layer of chips being arranged back to back; Encapsulating the first circuit layer, the metal pillars, the first layer chips and the second layer chips by using an epoxy resin molding packaging process; Grinding the upper surface of the structure obtained after epoxy resin molding packaging until the metal pillars and the front side of the second layer chip expose the corresponding metal pillars, so that the upper surface of the structure obtained after epoxy resin molding packaging is processed into a metal pillar exposed surface; Processing a second circuit layer on the exposed surface of the metal column by a redistribution layer process or a substrate bonding process, so that the metal column and the front surface of the second layer chip are electrically connected to the second circuit layer; The substrate is removed to obtain a chip packaging structure.

[0013] The beneficial effects of the present invention are: The chip packaging structure proposed in the present invention can install more chips in a packaging space of a specific size, thereby meeting the market demand for the number of chips installed in the chip packaging structure, and is particularly suitable for functional chips with low heat generation and large installation quantity requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is one of the structural schematic diagrams of a chip packaging structure in an embodiment of the present application; Figure 2 This is a second structural schematic diagram of a chip packaging structure in an embodiment of the present application; Figure 3 This is a third structural schematic diagram of a chip packaging structure in an embodiment of the present application; Figure 4 This is a fourth structural diagram of a chip packaging structure in an embodiment of the present application; Figure 5 This is a fifth structural diagram of a chip packaging structure in an embodiment of the present application; Figure 6 This is a flow chart of a method for preparing a chip packaging structure in an embodiment of the present application.

[0015] In the figure: 1-first circuit layer; 2-second circuit layer; 3-metal pillar; 4-base layer; 5-second layer chip; 6-first layer chip; 7-packaged chip; 71-bare chip; 8-BGA packaged device. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0017] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0019] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0020] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0021] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0023] like Figure 1 As shown, embodiment 1 discloses a chip packaging structure, including: A circuit layer group, comprising a first circuit layer 1 and a second circuit layer 2 which are arranged horizontally, wherein the second circuit layer 2 is arranged directly above the first circuit layer 1; Metal pillars 3, the first circuit layer 1 and the second circuit layer 2 are electrically connected through a plurality of the metal pillars 3; A chipset, the chipset is arranged between the first circuit layer 1 and the second circuit layer 2, the chipset comprises a first layer chip 6 and a second layer chip 5, the front surface of the first layer chip 6 is bonded to the upper surface of the first circuit layer 1, the back surface of the second layer chip 5 is stacked on the back surface of the first layer chip 6, and the front surface of the second layer chip 5 is electrically connected to the second circuit layer 2 through an exposed metal column 3; A plastic encapsulation structure fills the space between the first circuit layer 1 and the second circuit layer 2 .

[0024] The specific chipset structure provided in the present application enables the chip packaging structure to install more chips in a packaging space of a specific size, thereby meeting the market demand for the number of chips installed in the chip packaging structure. The two layers of chips are arranged back to back, and then electrically connected to the second circuit layer 2 through the directly exposed metal pillars 3, which is different from the prior art that the circuit layer must be installed before the chip can be installed, thereby achieving the installation of more chips in a specific installation area or space size.

[0025] like Figure 1 As shown, in Embodiment 2, the first layer of chips 6 includes at least two first chips arranged in a flat pattern, and the second layer of chips 5 includes at least one second chip, and the back surfaces of both ends of the second chip are respectively stacked on the front surfaces of the adjacent ends of two adjacent first chips. Figure 1 Only the application scenario of two first chips and one second chip is given. When the number of chips is larger, this structure can be set as a repeating unit, and the setting principle is the same.

[0026] The front side of the chip mentioned in this application refers to the circuit side or BGA side on the chip. The front side of the chip is generally connected to a metal column / BGA packaging device. The back side of the chip refers to the silicon side or EMC side.

[0027] like Figure 2 As shown, in Example 3, a BGA packaging device 8 is arranged on the lower surface of the first circuit layer 1 , and the BGA packaging device 8 is electrically connected to the first circuit layer 1 .

[0028] like Figure 3 As shown, in Example 4, the chips in the chipset are all functional chips, and the upper surface of the second circuit layer 2 is electrically connected with a packaged chip 7, and the chips in the packaged chip 7 are computing chips. The functional chips, such as MCU chips and CIS chips, are different from chips that rely on integration to improve computing power. They generate less heat and require a large number of installations, so they are more suitable for packaging between the first circuit layer 1 and the second circuit layer 2. For some computing chips with high heat generation, it is more suitable to be externally installed on the outer surface of the second circuit layer 2. This makes the layout of the entire chip packaging structure more optimized.

[0029] like Figure 5 As shown, in Example 5, a base layer 4 is electrically connected below the BGA package device 8. In this embodiment, the base layer 4 is provided on the basis of the package chip 7 being electrically connected to the upper surface of the second circuit layer 2. In practical applications, only one base layer 4 may be added on the basis of Example 3.

[0030] In some embodiments, the metal pillar 3 is preferably a copper pillar, as the copper pillar has better electrical conductivity.

[0031] like Figure 4 As shown, in Embodiment 6, a layer of bare chips 71 is electrically connected to the upper surface of the second circuit layer 2 .

[0032] like Figure 6 As shown, a method for preparing a chip packaging structure comprises: Processing a first circuit layer 1 on the substrate by a redistribution layer process or a substrate bonding process; Processing a plurality of metal pillars 3 electrically connected to the first circuit layer 1 on the upper surface of the first circuit layer 1 by through-molding via technology; Connecting the front surface of the first layer chip 6 to the upper surface of the first circuit layer 1 through a chip bonding process on the first circuit layer 1; The second layer chip 5 is stacked on the back side of the first layer chip 6, and the first layer chip 6 and the second layer chip 5 are arranged back to back; The first circuit layer 1, the metal pillar 3, the first layer chip 6 and the second layer chip 5 are packaged by using an epoxy resin molding packaging process; Grinding the upper surface of the structure obtained after epoxy resin molding packaging until the metal pillars 3 and the front side of the second layer chip 5 expose the corresponding metal pillars 3, so that the upper surface of the structure obtained after epoxy resin molding packaging is processed into the exposed surface of the metal pillars 3; The second circuit layer 2 is processed on the exposed surface of the metal pillar 3 by a redistribution layer process or a substrate bonding process, so that the metal pillar 3 and the front surface of the second layer chip 5 are electrically connected to the second circuit layer 2 .

[0033] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A circuit layer group, comprising a first circuit layer and a second circuit layer arranged horizontally, wherein the second circuit layer is arranged directly above the first circuit layer; Metal pillars, the first circuit layer and the second circuit layer are electrically connected through a plurality of the metal pillars; A chipset, the chipset is arranged between the first circuit layer and the second circuit layer, the chipset comprises a first layer chip and a second layer chip, the front surface of the first layer chip is bonded to the upper surface of the first circuit layer, the back surface of the second layer chip is stacked on the back surface of the first layer chip, and the front surface of the second layer chip is electrically connected to the second circuit layer through an exposed metal column; A plastic packaging structure fills the space between the first circuit layer and the second circuit layer.

2. The chip packaging structure according to claim 1, characterized in that: The first layer of chips includes at least two first chips arranged in a flat pattern, and the second layer of chips includes at least one second chip. The back sides of both ends of the second chip are respectively stacked on the front sides of the adjacent ends of two adjacent first chips.

3. The chip packaging structure according to claim 1, characterized in that: A BGA packaging device is arranged on the lower surface of the first circuit layer, and the BGA packaging device is electrically connected to the first circuit layer.

4. The chip packaging structure according to claim 3, characterized in that: A base layer is electrically connected below the BGA packaged device.

5. A chip packaging structure according to claim 1 or 3, characterized in that: The chips in the chipset are all functional chips, the upper surface of the second circuit layer is electrically connected to a packaged chip, and the chips in the packaged chip are computing chips.

6. The chip packaging structure according to claim 1, characterized in that: The metal pillar is a copper pillar.

7. The chip packaging structure according to claim 1, characterized in that: A layer of bare chips is electrically connected to the upper surface of the second circuit layer.

8. A method for preparing a chip packaging structure, characterized in that: include: Processing a first circuit layer on the substrate by a redistribution layer process or a substrate bonding process; Processing a plurality of metal pillars electrically connected to the first circuit layer on the upper surface of the first circuit layer by through-molding via technology; Connecting the front surface of the first layer chip to the upper surface of the first circuit layer through a chip bonding process on the first circuit layer; Stacking a second layer of chips on the back side of the first layer of chips, with the first layer of chips and the second layer of chips being arranged back to back; Encapsulating the first circuit layer, the metal pillars, the first layer chips and the second layer chips by using an epoxy resin molding packaging process; Grinding the upper surface of the structure obtained after epoxy resin molding packaging until the metal pillars and the front side of the second layer chip expose the corresponding metal pillars, so that the upper surface of the structure obtained after epoxy resin molding packaging is processed into a metal pillar exposed surface; Processing a second circuit layer on the exposed surface of the metal column by a redistribution layer process or a substrate bonding process, so that the metal column and the front surface of the second layer chip are electrically connected to the second circuit layer; The substrate is removed to obtain a chip packaging structure.

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