Photoelectric sensor test structure, formation method and test method

Abstract

A photoelectric sensor test structure, its formation method, and a testing method are disclosed, comprising: a substrate including a first test region, a second test region, and a device region located between the first and second test regions; the substrate including a first surface and a second surface opposite to each other; a plurality of photoelectric doped regions and charge collection regions located within the device region, wherein the plurality of photoelectric doped regions and the charge collection regions and photoelectric doped regions are discrete from each other, and the first surface exposes the photoelectric doped regions; a first test structure located in the first test region; a second test structure located in the second test region; a plurality of isolation structures located between the photoelectric doped regions and between the charge collection regions and photoelectric doped regions, the isolation structures including shielding layers; a first interconnect structure located on the surface of the first surface; a second interconnect structure located on the surface of the first surface; and a third interconnect structure located on the surface of the second surface. The test structure is capable of testing interface state characterization data.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a photoelectric sensor test structure, its formation method, and its testing method. Background Technology

[0002] In the chip manufacturing of direct imaging ranging sensors, backside illumination (BSI) technology is typically employed to enhance overall optical performance. Within this BSI process, the design of the backside-illuminated film structure is crucial for the photoelectric conversion efficiency of the photodiode, thereby affecting the sensor's photon capture capability, imaging quality, and ranging accuracy.

[0003] Backside illumination (BSI) architecture direct imaging ranging sensor products are mainly used in 3D depth imaging. The technical challenge lies in ensuring the photon detection efficiency (PDE) and dark count rate (DRC) performance of the device while reducing pixel size and increasing density.

[0004] Deep trench isolation (DTI) is a widely used structure in direct imaging ranging sensors. It enables electrical and optical crosstalk isolation between single-photon avalanche diodes (SPADs), optimizing device performance. Currently, one of the key technologies in the industry for improving dark count rate while reducing photon detection efficiency is the manipulation of sidewall interface states in deep trench isolation. Specifically, this is achieved through back-side ion implantation or optimization of High-K dielectric material processing to improve relevant parameters.

[0005] However, in the existing technology, there is a lack of effective interface state characterization equipment. Therefore, it is impossible to directly obtain the characterization data of the interface state. The trend of interface state change can only be qualitatively inferred through changes in chip performance, and the reliability of qualitative inference is low. Summary of the Invention

[0006] The technical problem solved by this invention is the inability to accurately test the characterization data of the interface state.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide a photoelectric sensor test structure, comprising: a substrate, the substrate including a first test region, a second test region, and a device region located between the first test region and the second test region, the substrate including a first surface and a second surface opposite to each other; a plurality of photoelectric doped regions and charge collection regions located within the device region, the plurality of photoelectric doped regions being discrete from each other and from each other to each other, and the first surface exposing the photoelectric doped regions; a first test structure located in the first test region; a second test structure located in the second test region; a plurality of isolation structures located between the photoelectric doped regions and from each other to ...

[0008] Optionally, the photoelectric sensor test structure further includes: a first opening located in a first test area, the first opening being recessed relative to the second surface and exposing the first test structure; a second opening located in a second test area, the second opening being recessed relative to the second surface and exposing the second test structure; and a third opening located in a charge collection area, the third opening being recessed relative to the second surface, with a portion of the third interconnect structure located within the third opening.

[0009] Optionally, the photoelectric sensor test structure further includes a contact layer located on the inner wall surface of the third opening.

[0010] Optionally, the first interconnect structure includes: a plurality of first conductive plugs located on the surface of the charge collection region on the first side and a first conductive layer located on the surface of the first conductive plugs; the second interconnect structure includes: a plurality of second conductive plugs located on the surface of the photoelectric doped region on the first side and a second conductive layer located on the surface of the second conductive plugs; the third interconnect structure includes: a plurality of third conductive plugs located on the surface of each shielding layer, a fourth conductive plug located in the third opening, and a third conductive layer located on the surface of the third conductive plugs and the surface of the fourth conductive plugs.

[0011] Optionally, the first test structure includes: a fourth conductive layer located within the first test area, with the first surface exposing the fourth conductive layer; and a first conductive plug located between the fourth conductive layer and the first interconnect structure; the second test structure includes: a fifth conductive layer located within the second test area, with the first surface exposing the fifth conductive layer; and a second conductive plug located between the fifth conductive layer and the second interconnect structure.

[0012] Optionally, the isolation structure includes a first isolation structure and a second isolation structure located on both sides of the photoelectric doped region.

[0013] Optionally, the isolation structure further includes an insulating structure located between the shielding layer and the substrate.

[0014] Optionally, the insulation structure includes: a first insulating layer located on the surface of the shielding layer and a second insulating layer located between the first insulating layer and the shielding layer, wherein the shielding layer, the first insulating layer and the second insulating layer are made of different materials.

[0015] Optionally, the first test area further includes a first insulating dielectric layer located on the surface of the first opening; the second test area further includes a second insulating dielectric layer located on the surface of the second opening.

[0016] Optionally, the photoelectric sensor test structure further includes a passivation structure located on the second surface, the first test structure surface, the charge collection region surface, the third interconnect structure surface, and the second test structure surface.

[0017] The present invention also provides a method for forming a photoelectric sensor test structure, comprising: providing a substrate having a first test region, a second test region, and a device region located between the first test region and the second test region, the substrate including a first surface and a second surface opposite to each other; forming a plurality of photoelectric doped regions and charge collection regions in the device region, the plurality of photoelectric doped regions being discrete from each other and from each other to each other, and the first surface exposing the photoelectric doped regions; forming a first test structure in the first test region, the first surface exposing the first test structure; forming a second test structure in the second test region, the first surface exposing the first test structure; forming a first interconnect structure on the surface of the first surface, the first interconnect structure being electrically connected to the charge collection region and the first test structure respectively; forming a second interconnect structure on the surface of the first surface, the second interconnect structure being electrically connected to the photoelectric doped region and the second test structure respectively; forming a plurality of isolation structures between the photoelectric doped regions and from each other to each other, and forming a shielding layer within the isolation structures; forming a third interconnect structure on the surface of the second surface, the third interconnect structure being electrically connected to the shielding layer and the charge collection region respectively.

[0018] Optionally, the method for forming the photoelectric sensor test structure further includes: etching a second surface of the first test region to form a first opening before or after forming the first test structure, wherein the first opening exposes the first test structure; etching a second surface of the second test region to form a second opening before or after forming the second test structure, wherein the second opening exposes the second test structure; and etching a third opening on the second surface of the charge collection region, wherein a portion of the third interconnect structure is located within the third opening.

[0019] Optionally, the method for forming the photoelectric sensor test structure further includes: forming a contact layer on the inner wall surface of the third opening.

[0020] Optionally, the method of forming a first interconnect structure on the first surface includes: forming a plurality of first conductive plugs on the surface of the charge collection region of the first surface; forming a first conductive layer on the surface of the first conductive plugs; the method of forming a second interconnect structure on the first surface includes: forming a plurality of second conductive plugs on the surface of the photoelectric doped region of the first surface; forming a second conductive layer on the surface of the second conductive plugs; the method of forming a third interconnect structure on the second surface includes: forming a plurality of third conductive plugs on the surface of each shielding layer; forming a third conductive layer on the surface of the third conductive plugs; forming a fourth conductive plug in the third opening, wherein the surface of the fourth conductive plug is connected to the third conductive layer.

[0021] Optionally, the method of forming a first test structure in a first test area includes: forming a fourth conductive layer in the first test area, with the first surface exposing the fourth conductive layer; and a first conductive plug between the fourth conductive layer and a first interconnect structure; the method of forming a second test structure in a second test area includes: forming a fifth conductive layer in the second test area, with the first surface exposing the fifth conductive layer; and a second conductive plug between the fifth conductive layer and the second interconnect structure.

[0022] Optionally, after forming a shielding layer within the isolation structure, the method includes: forming a first insulating layer on the surface of the shielding layer, and forming a second insulating layer between the first insulating layer and the shielding layer.

[0023] Optionally, the method of forming a first opening in the first test area includes: forming a first insulating dielectric layer on the surface of the first opening; the method of forming a second opening in the second test area includes: forming a second insulating dielectric layer on the surface of the second opening.

[0024] Optionally, the method for forming the photoelectric sensor test structure further includes: forming a passivation structure on the second surface, the first test structure surface, the charge collection region surface, the third interconnect structure surface, and the second test structure surface.

[0025] The present invention also provides a testing method for a photoelectric sensor test structure, comprising: applying a first frequency to a first test structure and a second test structure to obtain a first capacitance value Chf; applying a second frequency to the first test structure and the second test structure to obtain a second capacitance value Clf; and obtaining the interface state density based on the first capacitance value and the second capacitance value. Where A is the overlapping area of ​​the photoelectric doped region and the isolation structure, q is the charge amount, and Cox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0026] Optionally, the first frequency is at least 100 times a preset threshold, and the second frequency is less than the preset threshold.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] The photoelectric sensor test structure provided in this invention electrically connects the charge collection region to the first test structure through a first interconnect structure, electrically connects the photoelectric doped region to the second test structure through a second interconnect structure, and electrically connects the shielding layer to the charge collection region through a third interconnect structure. This allows the interface state characterization data of the substrate overlapping with the isolation structure to be converted into the capacitance value of the photoelectric doped region and the isolation structure, which can then be measured. Furthermore, the test structure in this invention can be matched with existing photoelectric sensors, will not damage the photoelectric sensor during testing, ensures the universality of the test structure, and shortens the development cycle.

[0029] Furthermore, a first isolation structure and a second isolation structure are formed on both sides of the photoelectric doped region, which isolates the photoelectric doped region from other regions in the substrate during the test, avoiding the influence of the potential of other regions in the substrate, ensuring the accuracy of the test results, and measuring multiple isolation structures further reduces the error of the test results.

[0030] The testing method for the photoelectric sensor test structure provided in this invention obtains the interface state density by measuring different capacitance values ​​at different frequencies, thereby further ensuring the accuracy of the interface state characterization data. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a photoelectric sensor;

[0032] Figures 2 to 9 This is a schematic diagram of the formation process of the photoelectric sensor test structure in an embodiment of the present invention;

[0033] Figure 10This is a schematic flowchart of the photoelectric sensor test structure test method in an embodiment of the present invention. Detailed Implementation

[0034] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0035] As can be seen from the background technology, existing photoelectric sensors lack effective interface state characterization equipment. Therefore, they cannot directly obtain interface state characterization data and can only qualitatively infer the trend of interface state changes through changes in chip performance. Moreover, the reliability of qualitative inference is low.

[0036] Figure 1 This is a schematic diagram of an embodiment of a photoelectric sensor.

[0037] The photoelectric sensor includes a substrate 100, which includes an isolation structure and a photosensitive structure 104. The isolation structure includes a shielding layer 103, a first insulating layer 102 located between the shielding layer 103 and the substrate, and a second insulating layer 101 located between the substrate and the first insulating layer.

[0038] The interface state between the second insulating layer 101 and the surface of the substrate 100 is an important reference for characterizing the performance of the photoelectric sensor, but there is currently no reasonable way or device to test the characterization data of the interface state.

[0039] To address the aforementioned technical problems, the present invention provides a photoelectric sensor test structure, a formation method, and a testing method. An interconnect structure connects the photoelectric doped region and the isolation structure to the test structure, respectively. The test structure then measures the capacitance values ​​of the photoelectric doped region and the isolation structure, converting these capacitance values ​​into interface state characterization data, which can then be measured. Furthermore, the test structure in this invention is compatible with existing photoelectric sensors, ensuring the universality of the test structure.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 9 This is a schematic diagram of the photoelectric sensor formation process in an embodiment of the present invention.

[0042] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 having a first test area I, a second test area II and a device area III located between the first test area I and the second test area II, the substrate 200 including a first surface a and a second surface b opposite to each other.

[0043] The substrate is used to provide space for the subsequently formed test structures, isolation structures, and photoelectric doped regions.

[0044] In this embodiment, the substrate 200 is made of silicon and is p-type doped.

[0045] In other embodiments, the substrate 200 is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] In this embodiment, a plurality of photoelectric doped regions 201 and charge collection regions are formed in device region III. The plurality of photoelectric doped regions 201 and the charge collection region and photoelectric doped region 201 are mutually independent, and the first surface a exposes the photoelectric doped regions 201.

[0047] The charge collection region is used to collect the charge generated by the isolation structure and transfer the charge generated by the isolation structure to the first test structure through the first interconnect structure.

[0048] The photoelectric doped region 201 is controlled by the second test structure to test the capacitance value of the photoelectric doped region.

[0049] In this embodiment, the doping type of the photoelectric doping region 201 is N-type doping, and the ions implanted in the photoelectric doping region 201 include phosphorus ions or arsenic ions.

[0050] In this embodiment, the method for forming the photoelectric doped region 201 includes: forming a mask layer (not labeled) on the surface of the first surface a, the mask layer exposing a portion of the surface of the first surface a; using the mask layer as a mask, performing ion implantation on the exposed portion of the surface of the first surface a, and finally forming the photoelectric doped region 201.

[0051] Please refer to Figure 3 A first interconnect structure is formed on the first surface a, and the first interconnect structure is electrically connected to the charge collection region and the first test structure, respectively; a second interconnect structure is formed on the first surface a, and the second interconnect structure is electrically connected to the photoelectric doping region 201 and the second test structure, respectively.

[0052] In this embodiment, the method further includes: forming an interlayer dielectric structure 223 on the first surface, wherein the first interconnect structure is located within the interlayer dielectric structure 223.

[0053] Specifically, the first interconnect structure includes: a plurality of first conductive plugs 202 and a first conductive layer 203.

[0054] The interlayer dielectric structure 223 includes: a first interlayer dielectric layer and a second interlayer dielectric layer.

[0055] The first interconnect structure includes: a plurality of first conductive plugs 202 and a first conductive layer 203.

[0056] In this embodiment, the method for forming the first interconnect structure includes: forming a plurality of first conductive plugs 202 on the surface of the charge collection region on the first surface a; and forming a first conductive layer 203 on the surface of the first conductive plugs 202.

[0057] The second interconnect structure includes: a plurality of second conductive plugs 204 and a second conductive layer 205.

[0058] The method for forming the second interconnect structure includes: forming a plurality of second conductive plugs 204 on the surface of the photoelectric doped region 201 on the first surface a; and forming a second conductive layer 205 on the surface of the second conductive plugs 204.

[0059] In this embodiment, the number of the first conductive plug 202 and the second conductive plug 204 ranges from 1 to 5. Specifically, there are two of each of the first conductive plug 202 and the second conductive plug 204. The materials of the first conductive layer 203 and the second conductive layer 205 are conductive metal materials, specifically aluminum.

[0060] The method for forming the first interlayer dielectric layer includes: forming a first interlayer dielectric layer on a first surface, and forming the first conductive plug 202 and the second conductive plug 204 within the first interlayer dielectric layer.

[0061] The method for forming the second interlayer dielectric layer includes: forming the second interlayer dielectric layer on the surface of the first interlayer dielectric layer, wherein the first conductive layer 203 and the second conductive layer 205 are located on the surface of the first interlayer dielectric layer and the first conductive layer 203 and the second conductive layer 205 are located within the second interlayer dielectric layer.

[0062] Please refer to Figure 4 Several isolation structures are formed between the photoelectric doped regions 201 and between the charge collection region and the photoelectric doped region 201.

[0063] The aforementioned isolation structures are used to isolate the photoelectric doped region from other substrate regions.

[0064] In this embodiment, the isolation structure includes: a shielding layer 206, a first insulating layer 207 located on the surface of the shielding layer 206, and a second insulating layer 208 located between the first insulating layer 207 and the shielding layer 206.

[0065] The material of the shielding layer 206 includes tungsten W, the material of the first insulating layer 207 includes a high-K material, and the second insulating layer 208 includes silicon nitride, silicon dioxide, or a combination of silicon nitride and silicon dioxide.

[0066] The thickness of the isolation structure is the same as the thickness of the substrate.

[0067] In this embodiment, any two isolation structures are symmetrically distributed on both sides of the photoelectric doping region 201.

[0068] In this embodiment, the method for forming the isolation structure includes: forming a mask layer (not labeled) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form trenches within the substrate 200; depositing a first initial insulating layer in the trenches and on the substrate surface; depositing a second initial insulating layer on the surface of the first initial insulating layer; depositing an initial shielding layer on the surface of the second initial insulating layer; and planarizing the initial shielding layer, the first initial insulating layer, and the second initial insulating layer until the second surface is exposed, thereby forming the shielding layer 206, the first insulating layer 207, and the second insulating layer 208.

[0069] In other embodiments, before forming the first interconnect structure, the second interconnect structure, and the interlayer dielectric structure, the method for forming the isolation structure includes: forming the shielding layer 206, the first insulating layer 207, and the second insulating layer 208 on the first surface. Specifically: forming a mask layer (not labeled) on the surface of the first surface a, the mask layer exposing a portion of the surface of the first surface a; using the mask layer as a mask, etching the substrate to form trenches in the substrate 200; depositing a first initial insulating layer in the trenches and on the substrate surface; depositing a second initial insulating layer on the surface of the first initial insulating layer; depositing an initial shielding layer on the surface of the second initial insulating layer; planarizing the initial shielding layer, the first initial insulating layer, and the second initial insulating layer until the first surface is exposed, thereby forming the shielding layer 206, the first insulating layer 207, and the second insulating layer 208.

[0070] Etching trenches involves either wet etching or dry etching. Wet etching is a technique that immerses the etching material in an etching solution; it is a purely chemical etching method with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam-assisted etching, and reactive ion beam etching. Dry etching is anisotropic.

[0071] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing (CMP). Specifically, in this embodiment, the planarization method is CMP. Unlike traditional purely mechanical or purely chemical polishing methods, CMP, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. CMP is widely used for high planarization polishing of various materials at the nanoscale.

[0072] Please refer to Figure 5 The second surface b of the first test region is etched to form a first opening 209; the second surface b of the second test region is etched to form a second opening 210; the second surface of the charge collection region is etched to form a third opening 211, and a portion of the third interconnect structure is located within the third opening 211.

[0073] The first opening 209 is used to provide a space for the subsequently formed first test structure, the second opening 210 is used to provide a space for the subsequently formed second test structure, and the third opening 211 is used to provide a space for the subsequently formed contact layer.

[0074] The method for forming the first opening 209 includes: forming a mask layer (not labeled) on the surface of the second side b, the mask layer exposing a portion of the surface of the second side; using the mask layer as a mask, etching the substrate to form the first opening 209 within the substrate 200.

[0075] The method for forming the second opening 210 includes: forming a mask layer (not labeled) on the surface of the second side b, the mask layer exposing a portion of the surface of the second side; using the mask layer as a mask, etching the substrate to form the second opening 210 within the substrate 200.

[0076] The method for forming the third opening 211 includes: forming a mask layer (not labeled) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form the third opening 211 within the substrate 200.

[0077] The depth of the first opening 209 is the same as the depth of the second opening 210, and the depth of the third opening 211 is less than the depth of the first opening 209. The top width of the first opening 209 and the second opening 210 is greater than the bottom width, that is, they are in the shape of an inverted trapezoid.

[0078] Please refer to Figure 6 A contact layer 212 is formed on the inner wall surface of the third opening 211.

[0079] The method for forming the contact layer 212 includes: depositing an initial contact layer on the surface of the third opening 211; planarizing the initial contact layer until the second surface is exposed, thereby forming the contact layer 212.

[0080] The material of the contact layer 212 is the same as that of the shielding layer 206. Specifically, the material of the contact layer 212 is tungsten.

[0081] The thickness of the contact layer 212 is less than the thickness of the isolation structure.

[0082] The contact layer 212 is used to receive the interface state and the charge generated on the isolation structure.

[0083] Please refer to Figure 7 A first insulating dielectric layer 218 is formed on the sidewall and bottom surface of the first opening; a second insulating dielectric layer 219 is formed on the sidewall and bottom surface of the second opening.

[0084] The method for forming the first insulating dielectric layer 218 includes: depositing a first initial insulating dielectric layer on the surface of the first opening; and planarizing the first initial insulating dielectric layer until the second surface is exposed, thereby forming the first insulating dielectric layer 218.

[0085] The method for forming the second insulating dielectric layer 219 includes: depositing a second initial insulating dielectric layer on the surface of the second opening; and planarizing the second initial insulating dielectric layer until the second surface is exposed, thereby forming the second insulating dielectric layer 219.

[0086] The materials of the first insulating dielectric layer 218 and the second insulating dielectric layer 219 include silicon oxide.

[0087] Please refer to Figure 8 A first test structure is formed in the first test area I; a second test structure is formed in the second test area II.

[0088] In this embodiment, the first test structure includes a fourth conductive layer 216 and a first conductive plug 202; the second test structure includes a fifth conductive layer 217 and a second conductive plug 204.

[0089] The method for forming the first test structure includes: etching the bottom surface of the first insulating dielectric layer 218 and the first interlayer dielectric layer to form a fourth opening that exposes the surface of the first conductive layer 203; forming a first conductive plug 202 in the fourth opening, the first conductive plug 202 being located on the surface of the first conductive layer 203; and forming a fourth conductive layer 216 in the fourth opening, the fourth conductive layer 216 being located on the surface of the first conductive plug 202, and a portion of the fourth conductive layer 216 being located within the fourth opening.

[0090] The method for forming the second test structure includes: etching the bottom surface of the second insulating dielectric layer and the first interlayer dielectric layer to form a fifth opening that exposes the surface of the second conductive layer 205; forming a second conductive plug 204 in the fifth opening, the second conductive plug 204 being located on the surface of the second conductive layer 205; and forming a fifth conductive layer 217 in the fifth opening, the fifth conductive layer 217 being located on the surface of the second conductive plug 204, and a portion of the fifth conductive layer 217 being located within the fifth opening.

[0091] The materials of the fourth conductive layer 216 and the fifth conductive layer 217 include silicon or germanium.

[0092] Please refer to Figure 9 A passivation structure 220 and a third interconnection structure located within the passivation structure are formed on the second surface b, the sidewall surface of the first opening 209, and the sidewall surface of the second opening 210. The third interconnection structure is electrically connected to the shielding layer 206 and the charge collection region, respectively.

[0093] The material of the passivation structure 220 includes silicon dioxide.

[0094] In this embodiment, the passivation structure includes a first passivation layer 221 and a second passivation layer 222. The third interconnect structure includes: a fourth conductive plug 215 located within a third opening, a third conductive plug 213 located on the surface of the shielding layer, and a third conductive layer 214 located on the surfaces of the third conductive plug 213 and the fourth conductive plug 215. The fourth conductive plug 215 and the third conductive plug 213 are located within the first passivation layer 221, and the third conductive layer 214 is located within the second passivation layer 222.

[0095] The material of the third conductive layer 214 is a conductive metallic material, specifically aluminum.

[0096] The thickness of the second passivation layer 222 is greater than the thickness of the third conductive layer 214, and the first passivation layer is flush with the third conductive plug 213 and the fourth conductive plug 215.

[0097] The method for forming the first passivation layer 221, the fourth conductive plug 215, and the third conductive plug 213 includes: depositing a first initial passivation layer on the surface of the second surface b, the sidewall surface of the first opening 209, and the sidewall surface of the second opening 210; etching the first initial passivation layer located on the surface of the shielding layer 206 to form a sixth opening (not shown in the figure) exposing the surface of the shielding layer 206, and forming a plurality of third conductive plugs 213 in the sixth opening; etching the first initial passivation layer located on the surface of the contact layer 212 to form a seventh opening (not shown in the figure) exposing the surface of the contact layer 212, and forming a plurality of fourth conductive plugs 215 in the seventh opening; and planarizing the first initial passivation layer until the surfaces of the third conductive plugs 213 and the fourth conductive plugs 215 are exposed, thereby forming the first passivation layer 221.

[0098] The method for forming the second passivation layer 222 and the third conductive layer 214 includes: depositing a second initial passivation layer on the surface of the second surface b; etching the second initial passivation layer located on the device region to form an eighth opening that exposes the surface of the first passivation layer 221, the surface of the third conductive plug 213, and the surface of the fourth conductive plug 215; forming the third conductive layer 214 in the eighth opening; and planarizing the second initial passivation layer to form the second passivation layer 222.

[0099] In this embodiment, the number of the third conductive plug 213 and the fourth conductive plug 215 ranges from 1 to 5. Specifically, there are 2 third conductive plugs 213 and 1 fourth conductive plug; wherein, the number of the third conductive plugs 213 is the same as the number of the shielding layer 206.

[0100] In other embodiments, the method for forming the fourth conductive layer 216 further includes: after forming the first passivation layer 221, etching the bottom surface of the first passivation layer 221 located on the sidewall surface of the first opening to form a ninth opening that exposes the first surface, and forming the fourth conductive layer 216 in the ninth opening.

[0101] In other embodiments, the method for forming the fifth conductive layer 217 further includes: after forming the first passivation layer 221, etching the bottom surface of the first passivation layer 221 located on the sidewall surface of the second opening to form a tenth opening that exposes the first surface, and forming the fifth conductive layer 217 in the tenth opening.

[0102] Accordingly, please continue to refer to Figure 9 The present invention also provides a photoelectric sensor testing structure, comprising:

[0103] Substrate 200, the substrate 200 includes a first test area I, a second test area II and a device area III located between the first test area I and the second test area II, the substrate 200 includes a first surface a and a second surface b opposite to each other;

[0104] A plurality of photoelectric doped regions 201 and a charge collection region are located in device region III. The plurality of photoelectric doped regions 201 are separated from each other as are the charge collection region and the photoelectric doped region 201. The first surface a exposes the photoelectric doped region 201.

[0105] The first test structure located in the first test area I;

[0106] The second test structure is located in the second test area II;

[0107] Several isolation structures are located between the photoelectric doping regions 201 and between the charge collection region and the photoelectric doping region 201, the isolation structures including a shielding layer 206;

[0108] A first interconnect structure located on the surface of the first surface a, the first interconnect structure being electrically connected to the charge collection region and the first test structure respectively;

[0109] A second interconnect structure is located on the surface of the first surface a, and the second interconnect structure is electrically connected to the photoelectric doping region 201 and the second test structure, respectively.

[0110] A third interconnect structure is located on the surface of the second surface b, and the third interconnect structure is electrically connected to the shielding layer 206 and the charge collection region, respectively.

[0111] The following will be described in detail with reference to the accompanying drawings.

[0112] Please continue to refer to Figure 9 The photoelectric sensor test structure further includes: a first opening 209 located in the first test area I, the first opening 209 being recessed relative to the second surface b, and the first opening 209 exposing the first test structure; a second opening 210 located in the second test area II, the second opening 210 being recessed relative to the second surface b, and the second opening 210 exposing the second test structure; and a third opening located in the charge collection area, the third opening being recessed relative to the second surface b, and a portion of the third interconnect structure being located within the third opening.

[0113] In this embodiment, the photoelectric sensor test structure further includes a contact layer 212 located on the inner wall surface of the third opening.

[0114] In this embodiment, the first interconnect structure includes: a plurality of first conductive plugs 202 respectively located on the surface of the charge collection region on the first surface a, and a first conductive layer 203 located on the surface of the first conductive plugs 202; the second interconnect structure includes: a plurality of second conductive plugs 204 respectively located on the surface of the photoelectric doping region 201 on the first surface a, and a second conductive layer 205 located on the surface of the second conductive plugs 204; the third interconnect structure includes: a plurality of third conductive plugs 213 located on the surface of each shielding layer 206, a fourth conductive plug 215 located in the third opening, and a third conductive layer 214 located on the surface of the third conductive plugs 213 and the surface of the fourth conductive plugs 215.

[0115] In this embodiment, the first test structure includes: a fourth conductive layer 216 located in the first test area I, with the first surface a exposing the fourth conductive layer 216; and a first conductive plug 202 located between the fourth conductive layer 216 and the first interconnect structure; the second test structure includes: a fifth conductive layer 217 located in the second test area II, with the first surface a exposing the fifth conductive layer 217; and a second conductive plug 204 located between the fifth conductive layer 217 and the second interconnect structure.

[0116] In this embodiment, the isolation structure includes a first isolation structure and a second isolation structure located on both sides of the photoelectric doping region 201.

[0117] In this embodiment, the isolation structure further includes an insulating structure located between the shielding layer 206 and the substrate 200.

[0118] In this embodiment, the insulation structure includes: a first insulating layer 207 located on the surface of the shielding layer 206 and a second insulating layer 208 located between the first insulating layer 207 and the shielding layer 206, wherein the shielding layer 206, the first insulating layer 207 and the second insulating layer 208 are made of different materials.

[0119] In this embodiment, the first test area I further includes a first insulating dielectric layer 218 located on the surface of the first opening 209; the second test area II further includes a second insulating dielectric layer 219 located on the surface of the second opening 210.

[0120] In this embodiment, the photoelectric sensor test structure further includes a passivation structure 220 located on the second surface b, the first test structure surface, the charge collection region surface, the third interconnect structure surface, and the second test structure surface.

[0121] In other embodiments, the first test structure and the second test structure include a test socket kit (TSK), which consists of a base and test pins. The test socket kit can be inserted into the photoelectric sensor to test the interface state density of the photoelectric sensor. The test pins are connected to the fourth and fifth conductive layers in the photoelectric sensor to test the capacitance value, thereby testing the interface state density.

[0122] On the one hand, the photoelectric sensor test structure in the above scheme can fit well with the existing photoelectric sensor manufacturing process. At the same time, it can realize the measurement during the manufacturing process, or the measurement after the manufacturing process or after the manufacturing is completed. Compared with some destructive characterization methods, the above photoelectric sensor test structure does not need to leave the production environment, will not introduce other pollution or affect chip performance, and is suitable for mass production environment.

[0123] On the other hand, existing optical characterization techniques all need to consider the influence of the insulating layer structure above the characterization structure on the signal. Therefore, they need to be optimized separately for different structures, which greatly increases the development cycle and implementation difficulty. However, the photoelectric sensor test structure of the present invention is not affected by the chip design or the thin film structure of the process itself, and has the advantage of universality. Moreover, the photoelectric sensor test structure of the present invention is simple, less affected by external environmental interference, has repeatability, and has high reliability.

[0124] Accordingly, please refer to Figure 10 The present invention also provides a testing method for a photoelectric sensor test structure, comprising:

[0125] S1: Apply a first frequency to the first test structure and the second test structure to obtain the first capacitance value Chf;

[0126] S2: Apply a second frequency to the first test structure and the second test structure to obtain the second capacitance value Clf;

[0127] S3: Obtain the interface state density based on the first capacitance value and the second capacitance value. Where A is the overlap area between the photoelectric doped region and the isolation structure, q is the charge amount, and C ox This represents the capacitance value corresponding to the first and second insulating layers.

[0128] The following combination Figure 9 as well as Figure 10 The working principle of the test method for the photoelectric sensor test structure in the technical solution of this invention is explained as follows:

[0129] Since interface state defects are generally described using donor-like and acceptor-like theories, taking N-type semiconductors as an example, they can be divided into acceptor-like and donor-like states according to the intermediate performance level. When there is no external bias voltage, the acceptor-like state has no electrons occupied, while the donor-like state has electrons occupied, and both are electrically neutral. When the external bias voltage is positive, the Fermi level is higher than all interface states, and both the acceptor-like and donor states are occupied by electrons, resulting in the overall interface state being negatively charged.

[0130] When the applied bias voltage is negative, if the bias voltage is small, the semiconductor is in the depletion region. The acceptor-like state is occupied by electrons and is electrically neutral, while the donor-like state is not occupied by electrons and is electrically neutral. This results in the overall interface state being negatively charged. When the applied negative bias voltage is large, the semiconductor is in the inversion region. Neither the acceptor-like nor the donor-like state is occupied by electrons. The donor-like state is electrically neutral, while the donor-like state is positively charged. This results in the overall interface state being positively charged.

[0131] It can be seen that the interface state will exhibit different charge accumulation under different bias voltages. Therefore, the technical solution of this invention utilizes this principle to characterize and calculate the interface state by measuring the capacitance value.

[0132] Please refer to Figure 9 as well as Figure 10 In S1: A first frequency is applied to the first test structure and the second test structure to obtain the first capacitance value C corresponding to the photoelectric doped region, the first insulating layer, and the second insulating layer. hf .

[0133] In a specific embodiment, the first capacitance value is first measured at a high frequency (i.e., the first frequency). The first capacitance value is characterized by the CV curve of the capacitor structure at the first frequency. Since the interface state defects cannot respond to changes in the high-frequency signal in time at a high frequency (i.e., the first frequency), the first capacitance value is mainly composed of the following formula: Among them, C s C is the capacitance value of the photoelectric doped region. ox This represents the capacitance value corresponding to the first and second insulating layers.

[0134] Please continue to refer to Figure 9 as well as Figure 10 In S2: A second frequency is applied to the first test structure and the second test structure to obtain the second capacitance value C corresponding to the photoelectric doped region, the first insulating layer, the second insulating layer, and the interface state. lf .

[0135] Specifically, the second capacitance value is measured at a low frequency (i.e., the second frequency). This second capacitance value is characterized by the CV curve of the capacitor structure at the second frequency. Since the interface state defects respond to changes in high-frequency signals at low frequencies (i.e., the second frequency), the second capacitance value is mainly composed of the following formula: Among them, C it It is the capacitance value corresponding to the interface state.

[0136] In this embodiment, the first frequency is at least 100 times a preset threshold, and the second frequency is less than the preset threshold.

[0137] Preferably, the first frequency is 100 to 1000 times a preset threshold, and the preset threshold is 100 to 1000 times a second frequency.

[0138] In a specific embodiment, the preset threshold is 10KHz, the first frequency is 1MHz, and the second frequency is 100Hz.

[0139] In this embodiment, before testing the interface state density, the preset threshold is measured. Specifically, a high frequency is first applied to the photoelectric sensor to obtain a first CV curve corresponding to the high frequency. Then, the high frequency is continuously reduced, and the CV curves corresponding to different frequencies are compared with the first CV curve during the reduction process. When the CV curve does not coincide with the first CV curve, the frequency corresponding to the CV curve at this time is determined to be the preset threshold.

[0140] Please continue to refer to Figure 9 as well as Figure 10 In S3: the interface state density is obtained based on the first capacitance value and the second capacitance value. Where A is the overlapping area of ​​the photoelectric doped region and the isolation structure, q is the charge amount, and Cox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0141] The interface state density is characterized as the interface state density of the substrate overlapping with the isolation structure.

[0142] Specifically, in the interface state density In the formula, the second capacitance value is subtracted from C. ox Then, the sum of the capacitance values ​​of the photoelectric doped region and the corresponding capacitance values ​​of the interface states, C, is obtained. s +C it Subtract C from the first capacitance value ox The capacitance value C of the photoelectric doped region was then obtained. s Finally, regarding C s +C it and C s The capacitance value C corresponding to the interface state is obtained by subtraction. it This allows us to calculate the interface state density.

[0143] In other embodiments, when there are N isolation structures in the photoelectric sensor test structure, the capacitance value measured at the first frequency or the second frequency is the sum of the capacitance values ​​of the N isolation structures. Therefore, when calculating the interface state density, the measured capacitance value needs to be divided by N to take the average value. The interface state density at this time is the interface state density of one isolation structure. Taking the average of the test results can reduce the influence of measurement error factors.

[0144] Furthermore, since the N isolation structures are symmetrically distributed in the substrate, the obtained interface state density can characterize the interface state density of any isolation structure.

[0145] In other embodiments, the testing method of the photoelectric sensor test structure further includes: measurement using the quasi-static method or the conductivity method. The technical solution of the present invention is not limited to this, and other calculation methods that can characterize the interface state density are all within the protection scope of the technical solution of the present invention.

[0146] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photoelectric sensor testing structure, characterized in that, include: A substrate, the substrate including a first test area, a second test area and a device area located between the first test area and the second test area, the substrate including a first surface and a second surface opposite to each other; The device region contains several photoelectric doped regions and charge collection regions, which are separated from each other as well as from each other, and the first surface exposes the photoelectric doped regions. The first test structure located in the first test area; The second test structure is located in the second test area; Several isolation structures located between the photoelectric doped regions and between the charge collection region and the photoelectric doped region, the isolation structures including a shielding layer; A first interconnect structure located on the first surface, the first interconnect structure being electrically connected to the charge collection region and the first test structure respectively; A second interconnect structure is located on the surface of the first surface, and the second interconnect structure is electrically connected to the photoelectric doping region and the second test structure, respectively. A third interconnect structure is located on the second surface, and the third interconnect structure is electrically connected to the shielding layer and the charge collection region, respectively.

2. The photoelectric sensor test structure as described in claim 1, characterized in that, Also includes: A first opening is located in the first test area, the first opening is recessed relative to the second surface, and the first opening exposes the first test structure; A second opening is located in the second test area, the second opening is recessed relative to the second surface, and the second opening exposes the second test structure; A third opening is located in the charge collection region, the third opening being recessed relative to the second surface, and a portion of the third interconnect structure is located within the third opening.

3. The photoelectric sensor test structure as described in claim 2, characterized in that, Also includes: The contact layer located on the inner wall surface of the third opening.

4. The photoelectric sensor test structure as described in claim 2, characterized in that, The first interconnect structure includes: a plurality of first conductive plugs located on the surface of the charge collection region on the first surface, and a first conductive layer located on the surface of the first conductive plugs; The second interconnect structure includes: a plurality of second conductive plugs located on the surface of the photoelectric doped region on the first side, and a second conductive layer located on the surface of the second conductive plugs; The third interconnect structure includes: a plurality of third conductive plugs located on the surface of each shielding layer, a fourth conductive plug located in the third opening, and a third conductive layer located on the surface of the third conductive plug and the surface of the fourth conductive plug.

5. The photoelectric sensor test structure as described in claim 1, characterized in that, The first test structure includes: a fourth conductive layer located within the first test area, the first surface exposing the fourth conductive layer; and a first conductive plug located between the fourth conductive layer and the first interconnect structure. The second test structure includes: a fifth conductive layer located within the second test area, wherein the first surface exposes the fifth conductive layer; and a second conductive plug located between the fifth conductive layer and the second interconnect structure.

6. The photoelectric sensor test structure as described in claim 1, characterized in that, The isolation structure includes a first isolation structure and a second isolation structure located on both sides of the photoelectric doped region.

7. The photoelectric sensor test structure as described in claim 1, characterized in that, The isolation structure further includes an insulating structure located between the shielding layer and the substrate.

8. The photoelectric sensor test structure as described in claim 7, characterized in that, The insulation structure includes: a first insulating layer located on the surface of the shielding layer and a second insulating layer located between the first insulating layer and the shielding layer, wherein the shielding layer, the first insulating layer and the second insulating layer are made of different materials.

9. The photoelectric sensor test structure as described in claim 2, characterized in that, The first test area further includes: a first insulating dielectric layer located on the surface of the first opening; The second test area also includes a second insulating dielectric layer located on the surface of the second opening.

10. The photoelectric sensor test structure as described in claim 1, characterized in that, The photoelectric sensor test structure further includes a passivation structure located on the second surface, the first test structure surface, the charge collection region surface, the third interconnect structure surface, and the second test structure surface.

11. A method for forming a photoelectric sensor test structure, characterized in that, include: A substrate is provided, the substrate having a first test region, a second test region, and a device region located between the first test region and the second test region, the substrate including opposing first and second surfaces; A plurality of photoelectric doped regions and charge collection regions are formed within the device region. The plurality of photoelectric doped regions and the charge collection regions and photoelectric doped regions are mutually independent, and the first surface exposes the photoelectric doped regions. A first test structure is formed within a first test area, and the first surface exposes the first test structure. A second test structure is formed in the second test area, and the first test structure is exposed on the first surface; a first interconnect structure is formed on the surface of the first surface, and the first interconnect structure is electrically connected to the charge collection area and the first test structure respectively. A second interconnect structure is formed on the first surface, and the second interconnect structure is electrically connected to the photoelectric doping region and the second test structure, respectively. Several isolation structures are formed between the photoelectric doped regions and between the charge collection region and the photoelectric doped region, and a shielding layer is formed within the isolation structures; A third interconnect structure is formed on the second surface, and the third interconnect structure is electrically connected to the shielding layer and the charge collection region, respectively.

12. The method for forming the photoelectric sensor test structure as described in claim 11, characterized in that, Also includes: Before or after the formation of the first test structure, the second surface of the first test area is etched to form a first opening, and the first opening exposes the first test structure. Before or after forming the second test structure, etching is performed on the second side of the second test region to form a second opening, and the second opening exposes the second test structure; etching is performed on the second side of the charge collection region to form a third opening, and a portion of the third interconnect structure is located within the third opening.

13. The method for forming the photoelectric sensor test structure as described in claim 12, characterized in that, Also includes: A contact layer is formed on the inner wall surface of the third opening.

14. The method for forming the photoelectric sensor test structure as described in claim 11, characterized in that, A method for forming a first interconnect structure on the surface of the first surface includes: forming a plurality of first conductive plugs on the surface of the charge collection region of the first surface; forming a first conductive layer on the surface of the first conductive plugs; a method for forming a second interconnect structure on the surface of the first surface includes: forming a plurality of second conductive plugs on the surface of the photoelectric doped region of the first surface; forming a second conductive layer on the surface of the second conductive plugs; The method of forming a third interconnect structure on the second surface includes: forming a plurality of third conductive plugs on the surface of each shielding layer; forming a third conductive layer on the surface of the third conductive plugs; and forming a fourth conductive plug in a third opening, wherein the surface of the fourth conductive plug is connected to the third conductive layer.

15. The method for forming the photoelectric sensor test structure as described in claim 11, characterized in that, A method for forming a first test structure within a first test area includes: forming a fourth conductive layer within the first test area, wherein the first surface exposes the fourth conductive layer; and a first conductive plug between the fourth conductive layer and a first interconnect structure. A method for forming a second test structure within a second test area includes: forming a fifth conductive layer within the second test area, wherein the first surface exposes the fifth conductive layer; and a second conductive plug between the fifth conductive layer and the second interconnect structure.

16. The method for forming the photoelectric sensor test structure as described in claim 11, characterized in that, After forming a shielding layer within the isolation structure, the process includes: forming a first insulating layer on the surface of the shielding layer, and forming a second insulating layer between the first insulating layer and the shielding layer.

17. The method for forming the photoelectric sensor test structure as described in claim 12, characterized in that, The method for forming a first opening in a first test area includes: forming a first insulating dielectric layer on the surface of the first opening; The method for forming a second opening in the second test area includes forming a second insulating dielectric layer on the surface of the second opening.

18. The method for forming the photoelectric sensor test structure as described in claim 11, characterized in that, Also includes: A passivation structure is formed on the second surface, the first test structure surface, the charge collection region surface, the third interconnect structure surface, and the second test structure surface.

19. A testing method for the photoelectric sensor test structure as described in claim 1, characterized in that, include: A first frequency is applied to the first test structure and the second test structure to obtain a first capacitance value C. hf ; A second frequency is applied to the first test structure and the second test structure to obtain a second capacitance value C. lf ; Based on the first capacitance value and the second capacitance value, obtain the interface state density. Where A is the overlap area between the photoelectric doped region and the isolation structure, q is the charge amount, and C ox This represents the capacitance value corresponding to the first and second insulating layers.

20. The testing method for the photoelectric sensor test structure as described in claim 19, characterized in that, The first frequency is at least 100 times the preset threshold, and the second frequency is less than the preset threshold.

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