Semiconductor structure and manufacturing method thereof, and bubble defect detection method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and a bubble defect detection method of the semiconductor structure, the semiconductor structure comprises a plurality of chip regions and cutting channel regions connected between the adjacent chip regions, and a bubble mark is formed in the cutting channel region at the periphery of each chip region; detecting the semiconductor structure to obtain a detection image containing the bubble mark; according to a design distance between the bubble mark and the chip area, disassembling the detection image to obtain an image of each chip area; and identifying the image of each chip area so as to judge whether the chip area has a bubble defect or not. According to the technical scheme, the bubble defect detection efficiency is improved, and the omission ratio is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof, and a bubble defect detection method for the semiconductor structure. Background Art

[0002] C-SAM (ultrasonic testing) technology can display the internal defects of the chip in the form of images. It is a commonly used chip failure analysis method. When it is applied to the bubble defect detection of the bonding interface of wafer-level stacked products, it is limited by the characteristics of small interface defect size and high interference noise after wafer stacking. The use of manual identification of chip ultrasonic detection images has disadvantages such as low efficiency and high error recognition rate.

[0003] Therefore, it is necessary to improve the bubble defect detection method to improve the bubble defect detection efficiency and reduce the missed detection rate. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, and a bubble defect detection method for the semiconductor structure, so as to improve the bubble defect detection efficiency and reduce the missed detection rate.

[0005] To achieve the above objective, the present invention provides a semiconductor structure, comprising a plurality of chip regions and a cutting path region connecting adjacent chip regions, wherein a bubble mark is formed on the cutting path region outside each chip region.

[0006] Optionally, the semiconductor structure includes an upper wafer and a lower wafer bonded to each other, and the bubble mark is located in the upper wafer and / or the lower wafer.

[0007] Optionally, the bubble mark is located at a dicing area at a corner and / or an edge of each chip area.

[0008] Optionally, the bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

[0009] Optionally, a bonding mark is formed in the semiconductor structure, and the bonding mark and the bubble mark are located in the same film layer.

[0010] The present invention also provides a method for manufacturing a semiconductor structure, comprising:

[0011] Providing an upper wafer and a lower wafer, wherein each of the upper wafer and the lower wafer comprises a plurality of chip regions and a dicing road region connecting adjacent chip regions;

[0012] Forming bubble marks on the scribe line area around each chip area of ​​the upper wafer and / or the lower wafer;

[0013] The upper wafer is bonded to the lower wafer, and the bubble mark is located on a side of the upper wafer and / or the lower wafer close to the bonding interface.

[0014] Optionally, the bubble mark is located at a dicing area at a corner and / or an edge of each chip area.

[0015] Optionally, the bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

[0016] Optionally, a bonding mark is formed in the upper wafer and / or the lower wafer, and the bonding mark and the bubble mark are made using the same mask.

[0017] The present invention also provides a method for detecting bubble defects in a semiconductor structure, comprising:

[0018] A semiconductor structure is provided, the semiconductor structure comprising a plurality of chip regions and a cutting path region connecting adjacent chip regions, wherein a bubble mark is formed on the cutting path region outside each chip region;

[0019] Detecting the semiconductor structure to obtain a detection image including the bubble mark;

[0020] According to the designed distance between the bubble mark and the chip area, images of each chip area are obtained by disassembling the detection image;

[0021] The image of each chip area is identified to determine whether there is a bubble defect in the chip area.

[0022] Optionally, the semiconductor structure includes an upper wafer and a lower wafer bonded to each other, and the bubble mark is located in the upper wafer and / or the lower wafer.

[0023] Optionally, the bubble defect is located at the bonding interface between the upper wafer and the lower wafer, and / or the bubble defect is located inside the upper wafer and / or inside the lower wafer.

[0024] Optionally, the bubble mark is located at a dicing area at a corner and / or an edge of each chip area.

[0025] Optionally, the bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

[0026] Optionally, an ultrasonic testing machine is used to detect the semiconductor structure.

[0027] Optionally, a bonding mark is formed in the semiconductor structure, and the bonding mark and the bubble mark are made using the same mask.

[0028] Optionally, the step of identifying the image of each chip area to determine whether there is a bubble defect in the chip area includes:

[0029] Adjusting the grayscale value of the image of each chip area to reduce the grayscale value of the area outside the bubble defect in the image of each chip area to the same value, thereby increasing the grayscale value difference between the area where the bubble defect is located and the area outside the bubble defect in the image of each chip area;

[0030] Define a grayscale threshold, where the grayscale threshold is smaller than the grayscale value of the area where the bubble defect is located and larger than the grayscale value of the area outside the bubble defect;

[0031] It is determined whether there is a region in the image of each chip region where the grayscale value is greater than the grayscale threshold. If so, there is a bubble defect in the chip region where the region where the grayscale value is greater than the grayscale threshold is located.

[0032] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0033] 1. The semiconductor structure of the present invention includes a plurality of chip areas and a cutting path area connecting adjacent chip areas. The cutting path area outside each chip area is formed with a bubble mark, so that the bubble defect detection efficiency can be improved and the missed detection rate can be reduced.

[0034] 2. The manufacturing method of the semiconductor structure of the present invention includes: providing an upper wafer and a lower wafer, each of the upper wafer and the lower wafer includes a plurality of chip areas and a cutting path area connecting adjacent chip areas; forming a bubble mark on the cutting path area outside each chip area of ​​the upper wafer and / or the lower wafer; bonding the upper wafer to the lower wafer, the bubble mark being located on one side of the upper wafer and / or the lower wafer close to the bonding interface, so as to improve the efficiency of bubble defect detection and reduce the missed detection rate.

[0035] 3. The bubble defect detection method of the semiconductor structure of the present invention comprises: providing a semiconductor structure, wherein the semiconductor structure comprises a plurality of chip areas and a cutting path area connecting adjacent chip areas, wherein the cutting path area outside each chip area is formed with a bubble mark; detecting the semiconductor structure to obtain a detection image including the bubble mark; disassembling the image of each chip area from the detection image according to a designed distance between the bubble mark and the chip area; identifying the image of each chip area to determine whether there is a bubble defect in the chip area, thereby improving the efficiency of bubble defect detection and reducing the missed detection rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0037] Figure 2a to Figure 2e is a schematic diagram of a device in a semiconductor structure manufacturing process according to an embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of the position of a bubble mark on a semiconductor structure according to an embodiment of the present invention;

[0039] Figure 4a to Figure 4b is a schematic structural diagram of a bubble mark according to an embodiment of the present invention;

[0040] Figure 5 The flowchart of the bubble defect detection method of the semiconductor structure according to one embodiment of the present invention.

[0041] Among them, Figure 1 to Figure 5 The reference numerals are described as follows:

[0042] 10 - upper wafer; 11 - upper substrate; 12 - first insulating dielectric layer; 13 - bubble mark; 14 - second insulating dielectric layer; 20 - lower wafer; 21 - lower substrate; 22 - third insulating dielectric layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, advantages and features of the present invention clearer, the semiconductor structure and its manufacturing method, and the bubble defect detection method of the semiconductor structure proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] An embodiment of the present invention provides a semiconductor structure, including a plurality of chip regions and a scribe line region connecting adjacent chip regions, wherein a bubble mark is formed on the scribe line region outside each chip region.

[0045] See below Figure 2e , Figure 3 , Figure 4a to Figure 4b The semiconductor structure provided by this embodiment is described in more detail, wherein: Figure 2e and Figure 4a It is a cross-sectional view. Figure 3 and Figure 4b It is a top view.

[0046] The semiconductor structure includes a plurality of chip areas A1 and a scribe line area A2 connecting adjacent chip areas A1 . A bubble mark 13 is formed on the scribe line area A2 outside each chip area A1 .

[0047] The semiconductor structure includes an upper wafer 10 and a lower wafer 20 bonded to each other, and the bubble mark 13 is located in the upper wafer 10 and / or the lower wafer 20 .

[0048] The upper wafer 10 may be a carrier wafer or a device wafer, and the lower wafer 20 may be a carrier wafer or a device wafer. The device wafer may be formed with at least one of the device structures such as transistors, capacitors, resistors, etc., and the carrier wafer may be formed with a device structure or may not be formed with a device structure. It should be noted that the present invention does not limit the structure of the upper wafer 10 and the lower wafer 20, and the upper wafer 10 and the lower wafer 20 may be selected appropriately according to the device to be formed.

[0049] The upper wafer 10 may include an upper substrate 11 and a first insulating dielectric layer 12 formed on the upper substrate 11, and the lower wafer 20 may include a lower substrate 21 and a third insulating dielectric layer 22 formed on the lower substrate 21, and a side of the first insulating dielectric layer 12 away from the upper substrate 11 is bonded to a side of the third insulating dielectric layer 22 away from the lower substrate 21.

[0050] In one embodiment, the second insulating dielectric layer 14 may be formed between the first insulating dielectric layer 12 and the third insulating dielectric layer 22, and the second insulating dielectric layer 14 is used to seal the bubble mark 13. In other embodiments, the second insulating dielectric layer 14 may not be formed between the first insulating dielectric layer 12 and the third insulating dielectric layer 22.

[0051] The depth of the bubble mark 13 in the upper wafer 10 and / or the lower wafer 20 is not limited, as long as it can be detected by the ultrasonic detection machine. For example, when the bubble mark 13 is located in the upper wafer 10, the bubble mark 13 can be located only in the first insulating dielectric layer 12, or the bubble mark 13 can extend from the first insulating dielectric layer 12 into the upper substrate 11.

[0052] The bubble marks 13 are located at the corners and / or edges of each chip area A1 in the scribe line area A2.

[0053] When the bubble mark 13 is located at the cutting path area A2 at the corner of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at the corner on at least one diagonal line of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0054] When the bubble mark 13 is located at the cutting path area A2 at the edge of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at each edge of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0055] The shape of the bubble mark 13 in a direction parallel to the surface of the semiconductor structure is L-shaped, cross-shaped, mitre-shaped, circular or polygonal.

[0056] exist Figure 3 In the illustrated embodiment, the L-shaped bubble mark 13 is located at the scribe line area A2 outside each chip area A1, and the bubble mark 13 is located at two corners on a diagonal line of each chip area A1.

[0057] One or more bubble marks 13 may be formed at a single corner and / or a single edge of each chip area A1. Figure 2c and Figure 3 The embodiment of forming the bubble mark 13 is shown. Figure 4a to Figure 4b The illustrated embodiment is one in which a plurality of bubble marks 13 are formed. Figure 4a to Figure 4b The opening width of the bubble mark 13 shown is less than Figure 2c and Figure 3 The opening width of the bubble mark 13 shown is such that Figure 4a to Figure 4b The bubble mark 13 shown can be more easily sealed to form a hollow structure.

[0058] The distance between the bubble mark 13 and the chip area A1 has been determined during the design, such as Figure 3 As shown, the distance D1 between the bubble mark 13 and the chip area A1 in the X direction and the distance D2 between the bubble mark 13 and the chip area A1 in the Y direction have been determined during the design, that is, the design distance D1 and the design distance D2 are known.

[0059] A bonding mark (not shown) is formed in the semiconductor structure for alignment during the bonding process of the upper wafer 10 and the lower wafer 20 .

[0060] The bonding mark and the bubble mark 13 are located in the same film layer.

[0061] The bonding mark is formed in the upper wafer 10 and / or the lower wafer 20. The bonding mark and the bubble mark 13 are located in the same wafer. The bonding mark and the bubble mark 13 can be made using the same mask, so there is no need for additional mask plates, thereby simplifying the process and reducing costs.

[0062] During the process of manufacturing the upper wafer 10 and / or the lower wafer 20, bubble defects may be generated inside the upper wafer 10 and / or inside the lower wafer 20; and / or during the process of bonding the upper wafer 10 and the lower wafer 20, bubble defects may be generated at the bonding interface between the upper wafer 10 and the lower wafer 20. The bubble defects may affect the reliability and other performance of the chip, so it is necessary to detect and screen out the chip area where the bubble defects are formed.

[0063] Since the bubble mark 13 is formed on the cutting path area A2 outside each chip area A1 in the semiconductor structure, the bubble mark 13 can be included in the detection image obtained by subsequently detecting the semiconductor structure with an ultrasonic detection machine, so that the image of each chip area A1 can be disassembled from the detection image according to the designed distance between the bubble mark 13 and the chip area A1, thereby eliminating the noise influence of the cutting path area A2 on the chip area A1, and only need to identify the image of each chip area A1, so that it is possible to more accurately judge whether there is a bubble defect in the chip area A1, thereby reducing the missed detection rate; and, since the interference of the cutting path area A2 with poor repeatability is eliminated, only the image of each repeated chip area A1 needs to be identified, so that the image of each chip area A1 can be automatically identified by automatic technology, thereby improving the efficiency of bubble defect detection.

[0064] In summary, the semiconductor structure provided by the present invention comprises a plurality of chip regions and a cutting path region connecting adjacent chip regions, wherein the cutting path region outside each chip region is formed with a bubble mark. The semiconductor structure provided by the present invention can improve the efficiency of bubble defect detection and reduce the missed detection rate.

[0065] An embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figure 1 , Figure 1 A method for manufacturing a semiconductor structure according to an embodiment of the present invention comprises:

[0066] Step S11, providing an upper wafer and a lower wafer, wherein each of the upper wafer and the lower wafer comprises a plurality of chip regions and a dicing road region connecting adjacent chip regions;

[0067] Step S12, forming bubble marks on the scribe line area around each chip area of ​​the upper wafer and / or the lower wafer;

[0068] Step S13, bonding the upper wafer to the lower wafer, wherein the bubble mark is located on a side of the upper wafer and / or the lower wafer close to the bonding interface.

[0069] See below Figure 2a to Figure 2e , Figure 3 , Figure 4a to Figure 4b The method for manufacturing the semiconductor structure provided by this embodiment is described in more detail, wherein: Figure 2a to Figure 2e and Figure 4a It is a cross-sectional view. Figure 3 and Figure 4b It is a top view.

[0070] According to step S11, Figure 2a and Figure 2d As shown, an upper wafer 10 and a lower wafer 20 are provided, and each of the upper wafer 10 and the lower wafer 20 includes a plurality of chip areas A1 and a scribe line area A2 connecting adjacent chip areas A1.

[0071] The upper wafer 10 may be a carrier wafer or a device wafer, and the lower wafer 20 may be a carrier wafer or a device wafer. The device wafer may be formed with at least one of the device structures such as transistors, capacitors, resistors, etc., and the carrier wafer may be formed with a device structure or may not be formed with a device structure. It should be noted that the present invention does not limit the structure of the upper wafer 10 and the lower wafer 20, and the upper wafer 10 and the lower wafer 20 may be selected appropriately according to the device to be formed.

[0072] like Figure 2a As shown, the upper wafer 10 includes an upper substrate 11 and a first insulating dielectric layer 12 formed on the upper substrate 11; Figure 2d As shown, the lower wafer 20 includes a lower substrate 21 and a third insulating dielectric layer 22 formed on the lower substrate 21 .

[0073] According to step S12 , bubble marks 13 are formed on the scribe line area A2 around each chip area A1 of the upper wafer 10 and / or the lower wafer 20 .

[0074] Taking forming the bubble mark 13 in the upper wafer 10 as an example, the steps of forming the bubble mark 13 may include: Figure 2b As shown, the first insulating dielectric layer 12 and a portion of the thickness of the upper substrate 11 are etched to form a bubble mark 13; then, as shown Figure 2c As shown, a second insulating dielectric layer 14 is formed on the first insulating dielectric layer 12 , and the second insulating dielectric layer 14 seals the bubble mark 13 ; then, the second insulating dielectric layer 14 is planarized by a chemical mechanical polishing process.

[0075] In other embodiments, in the above steps, the second insulating dielectric layer 14 may not be formed.

[0076] It should be noted that the depth of the bubble mark 13 in the upper wafer 10 and / or the lower wafer 20 is not limited, as long as it can be detected by the ultrasonic detection machine. For example, in the above steps, the bubble mark 13 can be located only in the first insulating dielectric layer 12, or the bubble mark 13 can extend from the first insulating dielectric layer 12 into the upper substrate 11.

[0077] The bubble marks 13 are located at the corners and / or edges of each chip area A1 in the scribe line area A2.

[0078] When the bubble mark 13 is located at the cutting path area A2 at the corner of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at the corner on at least one diagonal line of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0079] When the bubble mark 13 is located at the cutting path area A2 at the edge of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at each edge of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0080] The shape of the bubble mark 13 in a direction parallel to the surface of the semiconductor structure is L-shaped, cross-shaped, mitre-shaped, circular or polygonal.

[0081] exist Figure 3 In the illustrated embodiment, the L-shaped bubble mark 13 is located at the scribe line area A2 outside each chip area A1, and the bubble mark 13 is located at two corners on a diagonal line of each chip area A1.

[0082] One or more bubble marks 13 may be formed at a single corner and / or a single edge of each chip area A1. Figure 2c and Figure 3 The embodiment of forming the bubble mark 13 is shown. Figure 4a to Figure 4bThe illustrated embodiment is one in which a plurality of bubble marks 13 are formed. Figure 4a to Figure 4b The opening width of the bubble mark 13 shown is less than Figure 2c and Figure 3 The opening width of the bubble mark 13 shown is such that Figure 4a to Figure 4b The bubble mark 13 shown can be more easily sealed to form a hollow structure.

[0083] The distance between the bubble mark 13 and the chip area A1 has been determined during the design, such as Figure 3 As shown, the distance D1 between the bubble mark 13 and the chip area A1 in the X direction and the distance D2 between the bubble mark 13 and the chip area A1 in the Y direction have been determined during the design, that is, the design distance D1 and the design distance D2 are known.

[0084] Bonding marks (not shown) may be formed in the upper wafer 10 and / or the lower wafer 20 for subsequent alignment during the bonding process of the upper wafer 10 and the lower wafer 20 .

[0085] Preferably, the bonding mark and the bubble mark 13 are located in the same wafer, and the bonding mark and the bubble mark 13 are made using the same mask, so that no additional mask is needed, thereby simplifying the process and reducing costs.

[0086] According to step S13 , the upper wafer 10 and the lower wafer 20 are bonded to obtain a semiconductor structure, and the bubble mark 13 is located on a side of the upper wafer 10 and / or the lower wafer 20 close to the bonding interface.

[0087] like Figure 2e As shown, a surface of the second insulating dielectric layer 14 away from the upper substrate 11 is bonded to a surface of the third insulating dielectric layer 22 away from the lower substrate 21 .

[0088] During the process of manufacturing the upper wafer 10 and / or the lower wafer 20, bubble defects may be generated inside the upper wafer 10 and / or inside the lower wafer 20; and / or during the process of bonding the upper wafer 10 and the lower wafer 20, bubble defects may be generated at the bonding interface between the upper wafer 10 and the lower wafer 20. The bubble defects may affect the reliability and other performance of the chip, so it is necessary to detect and screen out the chip area where the bubble defects are formed.

[0089] By forming the bubble mark 13 in the cutting path area A2 outside each chip area A1 of the upper wafer 10 and / or the lower wafer 20, the bubble mark 13 can be included in the detection image obtained by subsequently detecting the semiconductor structure using an ultrasonic detection machine, so that the image of each chip area A1 can be disassembled from the detection image according to the designed distance between the bubble mark 13 and the chip area A1, thereby eliminating the noise influence of the cutting path area A2 on the chip area A1, and only need to identify the image of each chip area A1, so that it is possible to more accurately judge whether there is a bubble defect in the chip area A1, thereby reducing the missed detection rate; and, since the interference of the cutting path area A2 with poor repeatability is eliminated, only the image of each repeated chip area A1 needs to be identified, so that the image of each chip area A1 can be automatically identified by automatic technology, thereby improving the efficiency of bubble defect detection.

[0090] In summary, the manufacturing method of the semiconductor structure provided by the present invention comprises: providing an upper wafer and a lower wafer, each of which comprises a plurality of chip areas and a cutting road area connecting adjacent chip areas; forming a bubble mark on the cutting road area outside each chip area of ​​the upper wafer and / or the lower wafer; bonding the upper wafer to the lower wafer, and the bubble mark is located on one side of the upper wafer and / or the lower wafer close to the bonding interface. The manufacturing method of the semiconductor structure provided by the present invention makes it possible to improve the efficiency of bubble defect detection and reduce the missed detection rate.

[0091] An embodiment of the present invention provides a method for detecting bubble defects in a semiconductor structure. Figure 5 , Figure 5 1 is a flow chart of a method for detecting bubble defects in a semiconductor structure according to an embodiment of the present invention. The method for detecting bubble defects in a semiconductor structure comprises:

[0092] Step S21, providing a semiconductor structure, wherein the semiconductor structure comprises a plurality of chip regions and a scribe line region connecting adjacent chip regions, wherein a bubble mark is formed on the scribe line region outside each chip region;

[0093] Step S22, detecting the semiconductor structure to obtain a detection image including the bubble mark;

[0094] Step S23, according to the designed distance between the bubble mark and the chip area, disassemble the detection image to obtain images of each chip area;

[0095] Step S24, identifying the image of each chip area to determine whether there is a bubble defect in the chip area.

[0096] See below Figure 2a to Figure 4b The bubble defect detection method of the semiconductor structure provided by this embodiment is described in more detail, wherein: Figure 2a to Figure 2e and Figure 4a It is a cross-sectional view. Figure 3 and Figure 4b It is a top view.

[0097] According to step S21 , a semiconductor structure is provided. The semiconductor structure includes a plurality of chip areas A1 and a scribe line area A2 connecting adjacent chip areas A1 . A bubble mark 13 is formed on the scribe line area A2 outside each chip area A1 .

[0098] The semiconductor structure includes an upper wafer 10 and a lower wafer 20 bonded to each other, and the bubble mark 13 is located in the upper wafer 10 and / or the lower wafer 20 .

[0099] The upper wafer 10 may be a carrier wafer or a device wafer, and the lower wafer 20 may be a carrier wafer or a device wafer. The device wafer may be formed with at least one of the device structures such as transistors, capacitors, resistors, etc., and the carrier wafer may be formed with a device structure or may not be formed with a device structure. It should be noted that the present invention does not limit the structure of the upper wafer 10 and the lower wafer 20, and the upper wafer 10 and the lower wafer 20 may be selected appropriately according to the device to be formed.

[0100] Taking the bubble mark 13 located in the upper wafer 10 as an example, the steps of manufacturing the semiconductor structure may include: first, Figure 2a As shown, an upper wafer 10 is provided, wherein the upper wafer 10 includes an upper substrate 11 and a first insulating dielectric layer 12 formed on the upper substrate 11; then, as shown in Figure 2b As shown, the first insulating dielectric layer 12 and a portion of the thickness of the upper substrate 11 are etched to form a bubble mark 13; then, as shown Figure 2c As shown, a second insulating dielectric layer 14 is formed on the first insulating dielectric layer 12, and the second insulating dielectric layer 14 seals the bubble mark 13; then, the second insulating dielectric layer 14 is planarized by a chemical mechanical polishing process; then, as shown Figure 2d As shown, a lower wafer 20 is provided, wherein the lower wafer 20 includes a lower substrate 21 and a third insulating dielectric layer 22 formed on the lower substrate 21; then, as shown in Figure 2e As shown, a surface of the second insulating dielectric layer 14 away from the upper substrate 11 is bonded to a surface of the third insulating dielectric layer 22 away from the lower substrate 21 .

[0101] In the above steps, the second insulating dielectric layer 14 may not be formed, and the surface of the first insulating dielectric layer 12 away from the upper substrate 11 is bonded to the surface of the third insulating dielectric layer 22 away from the lower substrate 21 .

[0102] It should be noted that the depth of the bubble mark 13 in the upper wafer 10 and / or the lower wafer 20 is not limited, as long as it can be detected by the subsequent ultrasonic detection machine. For example, in the above steps, the bubble mark 13 can be located only in the first insulating dielectric layer 12, or the bubble mark 13 can extend from the first insulating dielectric layer 12 into the upper substrate 11.

[0103] During the process of manufacturing the upper wafer 10 and / or the lower wafer 20, bubble defects may be generated inside the upper wafer 10 and / or inside the lower wafer 20; and / or during the process of bonding the upper wafer 10 and the lower wafer 20, bubble defects may be generated at the bonding interface between the upper wafer 10 and the lower wafer 20. The bubble defects may affect the reliability and other performance of the chip, so it is necessary to screen out the chip area where the bubble defects are formed.

[0104] The bubble marks 13 are located at the corners and / or edges of each chip area A1 in the scribe line area A2.

[0105] When the bubble mark 13 is located at the cutting path area A2 at the corner of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at the corner on at least one diagonal line of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0106] When the bubble mark 13 is located at the cutting path area A2 at the edge of each chip area A1, it is preferred that the bubble mark 13 is located at the cutting path area A2 at each edge of each chip area A1, so that the range of the image of each chip area A1 obtained by subsequent disassembly is more accurate.

[0107] The shape of the bubble mark 13 in a direction parallel to the surface of the semiconductor structure is L-shaped, cross-shaped, mitre-shaped, circular or polygonal.

[0108] exist Figure 3 In the illustrated embodiment, the L-shaped bubble mark 13 is located at the scribe line area A2 outside each chip area A1, and the bubble mark 13 is located at two corners on a diagonal line of each chip area A1.

[0109] One or more bubble marks 13 may be formed at a single corner and / or a single edge of each chip area A1. Figure 2c and Figure 3 The embodiment of forming the bubble mark 13 is shown. Figure 4a to Figure 4b The illustrated embodiment is one in which a plurality of bubble marks 13 are formed. Figure 4a to Figure 4b The opening width of the bubble mark 13 shown is less than Figure 2c and Figure 3 The opening width of the bubble mark 13 shown is such that Figure 4a to Figure 4b The bubble mark 13 shown can be more easily sealed to form a hollow structure.

[0110] The distance between the bubble mark 13 and the chip area A1 has been determined during the design, such as Figure 3 As shown, the distance D1 between the bubble mark 13 and the chip area A1 in the X direction and the distance D2 between the bubble mark 13 and the chip area A1 in the Y direction have been determined during the design, that is, the design distance D1 and the design distance D2 are known.

[0111] A bonding mark (not shown) may be formed in the semiconductor structure for alignment during the bonding process of the upper wafer 10 and the lower wafer 20 .

[0112] The bonding mark is located in the upper wafer 10 and / or the lower wafer 20 .

[0113] Preferably, the bonding mark and the bubble mark 13 are located in the same wafer, and the bonding mark and the bubble mark 13 are made using the same mask, so that no additional mask is needed, thereby simplifying the process and reducing costs.

[0114] Step S22 , detecting the semiconductor structure to obtain a detection image including the bubble mark 13 .

[0115] The semiconductor structure may be inspected by an ultrasonic inspection machine.

[0116] Since ultrasound has strong reflectivity at the interface between solid and gas, the bubble mark 13 can be detected by collecting the reflected signal, and the bubble defect can also be detected, that is, the bubble mark 13 and the bubble defect can be displayed on the detection image.

[0117] The size (eg, length and width) of the bubble mark 13 is larger than the minimum pixel size that can be recognized by the ultrasonic detection machine, so that the bubble mark 13 can be detected by the ultrasonic detection machine.

[0118] Step S23 , according to the designed distance between the bubble mark 13 and the chip area A1 , images of each chip area A1 are obtained from the detection image.

[0119] Due to the large difference in acoustic impedance between the air in the bubble mark 13 and the materials of other structures around the bubble mark 13, there is a large grayscale difference between the area where the bubble mark 13 on the detection image is located and the area outside the bubble mark 13, so that the position of the bubble mark 13 on the detection image can be accurately identified; and since the design distance between the bubble mark 13 and the chip area A1 is known, then, according to the identified position of the bubble mark 13 on the detection image, the area surrounded by the bubble mark 13 is reduced by the design distance to accurately obtain the range of the chip area A1 on the detection image, so that the chip area A1 can be disassembled from the detection image to obtain images of each chip area A1.

[0120] When detecting the semiconductor structure, the material difference of each area of ​​the semiconductor structure causes the acoustic impedance to be different, which is reflected in the grayscale difference of each area on the detection image. Since the cutting road area A2 is provided with a large number of metal layers (such as test pads, etc.), the brightness of the cutting road area A2 on the detection image is very high, and its brightness is close to the brightness of the area where the bubble defect is located, that is, the grayscale value of the cutting road area A2 on the detection image is close to the grayscale value of the area where the bubble defect is located, which leads to the cutting road area A2 being identified when the bubble defect on the detection image is identified, that is, the noise of the cutting road area A2 affects the identification of the bubble defect of the chip area A1 on the detection image, thereby making it impossible to accurately identify the location of the bubble defect; and the film layer structure inside the cutting road area A2 in different areas is different, and the repeatability is poor. Even if an algorithm is used to reduce the noise of the cutting road area A2, the noise influence of the cutting road area A2 in all areas cannot be eliminated.

[0121] Therefore, in the present invention, by disassembling the chip area A1 from the detection image, the noise influence of the cutting road area A2 on the chip area A1 can be eliminated, so that the location of the bubble defect can be accurately identified by only identifying the image of the disassembled chip area A1, thereby realizing noise reduction processing of the detection image.

[0122] Step S24 , identifying the image of each chip area A1 to determine whether there is a bubble defect in the chip area A1 .

[0123] The steps may include:

[0124] Step S241, adjusting the grayscale value of each image of the chip area A1, so as to reduce the grayscale value of the area outside the bubble defect in the image of each chip area A1 to the same value, thereby increasing the grayscale value difference between the area where the bubble defect is located and the area outside the bubble defect in the image of each chip area A1;

[0125] Step S242, defining a grayscale threshold, wherein the grayscale threshold is smaller than the grayscale value of the area where the bubble defect is located and larger than the grayscale value of the area outside the bubble defect;

[0126] Step S243, identifying the grayscale value of each area of ​​the image of each chip area A1, and determining whether there is an area in the image of each chip area A1 where the grayscale value is greater than the grayscale threshold. If so, the chip area A1 where the area with the grayscale value greater than the grayscale threshold is located has a bubble defect; if not, the identified chip area A1 does not have a bubble defect.

[0127] Although there is a metal layer (such as metal interconnects or electrode plates, etc.) in the chip area A1, the area of ​​the metal layer in the chip area A1 is very small, and the internal structure of the chip area A1 is repetitive. Therefore, in step S241, an algorithm (such as Fourier transform) can be used to uniformly reduce the repeated noise effects of each chip area A1, that is, the grayscale values ​​of the areas outside the bubble defects in the images of each chip area A1 are uniformly reduced to the same value, so as to increase the difference in grayscale values ​​between the areas where the bubble defects are located and the areas outside the bubble defects in the images of each chip area A1, thereby augmenting the image of the chip area A1, thereby making it easier to identify the bubble defects in the future and to screen out the chip area A1 with the bubble defects.

[0128] From the above content, it can be known that by forming a bubble mark 13 in the cutting road area A1 outside each chip area A1 of the semiconductor structure, and after detecting the semiconductor structure to obtain a detection image containing the bubble mark 13, according to the designed distance between the bubble mark 13 and the chip area A1, the image of each chip area A1 is disassembled from the detection image, so that the noise influence of the cutting road area A2 on the chip area A1 can be eliminated, and only the image of each chip area A1 needs to be identified, so that it is possible to more accurately judge whether there is a bubble defect in the chip area A1; and, since the interference of the cutting road area A2 with poor repeatability is eliminated, only the image of each repeated chip area A1 needs to be identified, so that the image of each chip area A1 can be automatically identified by automatic technology. Therefore, compared with manual identification of the detection image, the present invention improves the efficiency of bubble defect detection and reduces the missed detection rate.

[0129] In summary, the bubble defect detection method of the semiconductor structure provided by the present invention comprises: providing a semiconductor structure, the semiconductor structure comprising a plurality of chip areas and a cutting road area connecting adjacent chip areas, the cutting road area outside each chip area being formed with a bubble mark; detecting the semiconductor structure to obtain a detection image containing the bubble mark; disassembling the image of each chip area from the detection image according to the designed distance between the bubble mark and the chip area; identifying the image of each chip area to determine whether there is a bubble defect in the chip area. The bubble defect detection method of the semiconductor structure provided by the present invention improves the efficiency of bubble defect detection and reduces the missed detection rate.

[0130] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: It comprises a plurality of chip areas and a cutting road area connecting adjacent chip areas, and a bubble mark is formed on the cutting road area outside each chip area.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure comprises an upper wafer and a lower wafer bonded to each other, and the bubble mark is located in the upper wafer and / or the lower wafer.

3. The semiconductor structure according to claim 1, wherein: The bubble marks are located at the corners and / or edges of each chip region in the dicing lane area.

4. The semiconductor structure according to claim 1, wherein: The bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

5. The semiconductor structure according to claim 1, wherein: A bonding mark is formed in the semiconductor structure, and the bonding mark and the bubble mark are located in the same film layer.

6. A method for manufacturing a semiconductor structure, characterized in that: include: Providing an upper wafer and a lower wafer, wherein each of the upper wafer and the lower wafer comprises a plurality of chip regions and a dicing road region connecting adjacent chip regions; Forming bubble marks on the scribe line area around each chip area of ​​the upper wafer and / or the lower wafer; The upper wafer is bonded to the lower wafer, and the bubble mark is located on a side of the upper wafer and / or the lower wafer close to the bonding interface.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The bubble marks are located at the corners and / or edges of each chip region in the dicing lane area.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

9. The method for manufacturing a semiconductor structure according to claim 6, wherein: A bonding mark is formed in the upper wafer and / or the lower wafer, and the bonding mark and the bubble mark are made using the same mask.

10. A method for detecting bubble defects in a semiconductor structure, characterized in that: include: A semiconductor structure is provided, the semiconductor structure comprising a plurality of chip regions and a cutting path region connecting adjacent chip regions, wherein a bubble mark is formed on the cutting path region outside each chip region; Detecting the semiconductor structure to obtain a detection image including the bubble mark; According to the designed distance between the bubble mark and the chip area, images of each chip area are obtained by disassembling the detection image; The image of each chip area is identified to determine whether there is a bubble defect in the chip area.

11. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: The semiconductor structure comprises an upper wafer and a lower wafer bonded to each other, and the bubble mark is located in the upper wafer and / or the lower wafer.

12. The method for detecting bubble defects in a semiconductor structure according to claim 11, wherein: The bubble defect is located at the bonding interface between the upper wafer and the lower wafer, and / or the bubble defect is located inside the upper wafer and / or inside the lower wafer.

13. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: The bubble marks are located at the corners and / or edges of each chip region in the dicing lane area.

14. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: The bubble mark has an L-shape, a cross-shape, a mitre-shape, a circle or a polygon in a direction parallel to the surface of the semiconductor structure.

15. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: An ultrasonic testing machine is used to test the semiconductor structure.

16. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: A bonding mark is formed in the semiconductor structure, and the bonding mark and the bubble mark are made using the same mask.

17. The method for detecting bubble defects in a semiconductor structure according to claim 10, wherein: The step of identifying the image of each chip area to determine whether there is a bubble defect in the chip area includes: Adjusting the grayscale value of the image of each chip area to reduce the grayscale value of the area outside the bubble defect in the image of each chip area to the same value, thereby increasing the grayscale value difference between the area where the bubble defect is located and the area outside the bubble defect in the image of each chip area; Define a grayscale threshold, where the grayscale threshold is smaller than the grayscale value of the area where the bubble defect is located and larger than the grayscale value of the area outside the bubble defect; It is determined whether there is a region in the image of each chip region where the grayscale value is greater than the grayscale threshold. If so, there is a bubble defect in the chip region where the region where the grayscale value is greater than the grayscale threshold is located.

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