Integrated device and packaging method thereof
By stacking the second transistor on the first transistor and electrically connecting it through the insulated electrode plate on the substrate, the problems of large package area and high line resistance of the integrated device are solved, and circuit miniaturization and performance improvement of the integrated device are achieved.
Patent Information
- Application Number
- CN202411292526.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-02-07
AI Technical Summary
The package area of existing integrated devices is large, and there are more wires when connecting HEMT and Si MOSFET during the packaging process, introducing more wire resistances, affecting the performance of integrated devices.
By stacking the second transistor on the first transistor and electrically connecting it through the insulating electrode plate on the substrate, the number of metal wires is reduced and the package wire resistance is reduced.
It effectively reduces the package area of integrated devices, reduces the package line resistance, and avoids additional introduced capacitance and inductance, thereby improving the performance of integrated devices.
Smart Images
Figure CN119400784A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of power electronics, and in particular to an integrated device and a packaging method thereof. Background Art
[0002] The cascode structure is an integrated device formed by cascading a depletion-mode high electron mobility transistor (HEMT) and an enhancement-mode Si MOSFET (Si Metal-Oxide-Semiconductor Field-Effect Transistor), which uses Si MOSFET to control the HEMT.
[0003] In the related art, the HEMT and Si MOSFET of the integrated device are arranged side by side on a substrate, and the electrodes of the HEMT and Si MOSFET are connected to corresponding components through metal wires.
[0004] However, the package area of the integrated device is large, and a large number of wires are bonded when connecting the HEMT and Si MOSFET during the packaging process, which introduces more wire resistance and affects the performance of the integrated device. Summary of the invention
[0005] The embodiment of the present disclosure provides an integrated device and a packaging method thereof, which can reduce the area of the integrated device and improve the performance of the integrated device. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides an integrated device, which includes: a first transistor, a second transistor and a substrate, the first transistor having a first source, a first drain and a first gate, the second transistor having a second source, a second drain and a second gate, the substrate including a source plate, a drain plate and a gate plate insulated from each other, the first transistor including a depletion-type high electron mobility transistor, and the second transistor including a silicon-based metal oxide semiconductor field effect transistor; the second transistor is stacked on the first transistor, the first transistor is located on the substrate, the first source is electrically connected to the second drain, the first drain is electrically connected to the drain plate, the first gate is electrically connected to the second source, the second source is also electrically connected to the source plate, and the second gate is electrically connected to the gate plate.
[0007] Optionally, the first source and the first gate are located on the same surface of the first transistor, and the first drain and the first source are respectively located on two opposite surfaces of the first transistor; the second source and the second gate are located on the same surface of the second transistor, and the second drain and the second source are respectively located on two opposite surfaces of the second transistor; the surface of the second transistor provided with the second drain is connected to the surface of the first transistor provided with the first source, and the surface of the first transistor provided with the first drain is connected to the drain plate.
[0008] Optionally, the orthographic projection of the second transistor on the surface of the substrate is located within the orthographic projection of the first source on the surface of the substrate.
[0009] Optionally, the gate plate and the source plate are located in the same plane, and the gate plate and the source plate are arranged at intervals, the drain plate is located on the surface of the source plate, and the drain plate is insulated from the source plate.
[0010] Optionally, the integrated device further comprises a metal wire, and the first gate and the second source, the second source and the source plate, and the second gate and the gate plate are all electrically connected via the metal wire.
[0011] Optionally, the first transistor further includes: a channel layer, a barrier layer, a first dielectric layer and a second dielectric layer; the second dielectric layer, the first dielectric layer, the barrier layer and the channel layer are stacked in sequence, and the surface of the channel layer away from the second dielectric layer has a first groove and a second groove; the first source and the first gate are both located on a side of the channel layer away from the second dielectric layer, and the first source and the first gate are both insulated from the channel layer, the first source is electrically connected to a surface of the channel layer close to the second dielectric layer through the first groove, and the first gate extends to the second dielectric layer through the second groove; the second dielectric layer has a third groove exposing the channel layer, the first drain is located on a side of the second dielectric layer away from the channel layer, and is electrically connected to a surface of the channel layer close to the second dielectric layer through the third groove.
[0012] Optionally, the first transistor further includes a source metal, the source metal is located in the first groove, the source metal is electrically connected to a surface of the channel layer close to the second dielectric layer, and the first source electrode is electrically connected to the source metal through the first groove.
[0013] Optionally, the first groove includes a first groove body and a second groove body connected to each other, the first groove body at least penetrates the channel layer, and the second groove body at least penetrates the barrier layer and the first dielectric layer; the source metal is located in the second groove body, and the end surface of the source metal close to the first groove body includes a first area and a second area surrounding the first area, the first area is opposite to the first groove body, the second area is electrically connected to the channel layer, and the first source is electrically connected to the source metal through the first groove body.
[0014] On the other hand, an embodiment of the present disclosure provides a packaging method for an integrated device, the packaging method comprising: providing a first transistor, a second transistor and a substrate, the first transistor having a first source, a first drain and a first gate, the second transistor having a second source, a second drain and a second gate, the substrate comprising a source plate, a drain plate and a gate plate insulated from each other, the first transistor comprising a depletion-type high electron mobility transistor, and the second transistor comprising a silicon-based metal oxide semiconductor field effect transistor; fixing the first transistor on the substrate so that the first drain is electrically connected to the drain plate; stacking the second transistor on the first transistor so that the first source is electrically connected to the second drain; and connecting the first gate and the second source, the second source and the source plate, and the second gate and the gate plate using metal wires.
[0015] Optionally, fixing the first transistor on the substrate includes: fixing the first drain electrode on the surface of the drain electrode plate by using solder paste or silver glue.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0017] In the integrated device provided by the embodiment of the present disclosure, the first transistor is arranged on the substrate, and the second transistor is stacked on the first transistor. Compared with the related art in which the transistors are arranged side by side on the substrate, the packaging area of the integrated device after packaging can be effectively reduced, and the circuit miniaturization of the integrated device can be achieved. In addition, the second transistor is stacked on the surface of the first transistor, and the electrodes on the opposite surfaces of the two transistors can be directly connected, so there is no need to set up metal wires separately, thereby reducing the number of metal wires set, effectively reducing the package line resistance, and avoiding the additional introduction of capacitance and inductance. At the same time, stacking the two transistors makes the distance between the two transistors shorter. When it is necessary to set a metal wire, the length of the metal wire can also be shortened to further reduce the package line resistance, avoid the additional introduction of capacitance and inductance, thereby improving the performance of the integrated device. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a schematic diagram of the structure of an integrated device provided by an embodiment of the present disclosure;
[0020] Figure 2 is a top view of an integrated device provided by an embodiment of the present disclosure;
[0021] Figure 3 yes Figure 2 An AA cross-sectional view is provided;
[0022] Figure 4 is a schematic structural diagram of a first transistor provided by an embodiment of the present disclosure;
[0023] Figure 5 is a structural schematic diagram of a second transistor provided by an embodiment of the present disclosure;
[0024] Figure 6 is a schematic structural diagram of a first transistor provided by an embodiment of the present disclosure;
[0025] Figure 7 It is a flow chart of a packaging method of an integrated device provided in an embodiment of the present disclosure.
[0026] The descriptions of the marks in the figure are as follows:
[0027] 11. a first transistor;
[0028] 12. a second transistor; 121. a second source; 122. a second drain; 123. a second gate;
[0029] 13. substrate; 131. source plate; 132. drain plate; 133. gate plate;
[0030] 14. Metal wire;
[0031] 21. channel layer; 22. barrier layer;
[0032] 210, first groove; 2101, first groove body; 2102, second groove body;
[0033] 211, second groove; 2111, third groove body; 2112, fourth groove body;
[0034] 31. a first dielectric layer; 32. a second dielectric layer;
[0035] 320, third groove; 3201, fifth groove body; 3202, sixth groove body;
[0036] 41. a first source electrode; 42. a first drain electrode; 43. a first gate electrode;
[0037] 51. Source metal; 52. Drain metal; 53. Gate metal;
[0038] 60. Bonding metal;
[0039] 70. Silicon substrate. DETAILED DESCRIPTION
[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0041] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity restriction, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0042] Figure 1 It is a schematic diagram of the structure of an integrated device provided in an embodiment of the present disclosure. Figure 2 It is a top view of an integrated device provided by an embodiment of the present disclosure. Figure 3 yes Figure 2 An AA cross-section diagram is provided. Figures 1 to 3 As shown, the integrated device includes: a first transistor 11, a second transistor 12 and a substrate 13.
[0043] Figure 4 is a schematic diagram of the structure of a first transistor 11 provided in an embodiment of the present disclosure. Figure 3 , 4 As shown, the first transistor 11 has a first source 41 , a first drain 42 and a first gate 43 .
[0044] The first transistor 11 includes a depletion-type high electron mobility transistor.
[0045] Figure 5 is a schematic diagram of the structure of a second transistor 12 provided in an embodiment of the present disclosure. Figure 3 , 5 As shown, the second transistor 12 has a second source 121 , a second drain 122 and a second gate 123 .
[0046] The second transistor 12 includes a silicon-based metal oxide semiconductor field effect transistor.
[0047] like Figure 1 , 2 As shown, the substrate 13 includes a source plate 131 , a drain plate 132 and a gate plate 133 which are insulated from each other.
[0048] like Figures 1 to 3 As shown, the second transistor 12 is stacked on the first transistor 11, the first transistor 11 is located on the substrate 13, the first source 41 is electrically connected to the second drain 122, the first drain 42 is electrically connected to the drain plate 132, the first gate 43 is electrically connected to the second source 121, the second source 121 is also electrically connected to the source plate 131, and the second gate 123 is electrically connected to the gate plate 133.
[0049] In the integrated device provided by the embodiment of the present disclosure, the first transistor 11 is arranged on the substrate 13, and the second transistor 12 is stacked on the first transistor 11. Compared with the related art in which the transistors are arranged side by side on the substrate 13, the packaging area of the integrated device after packaging can be effectively reduced, and the circuit miniaturization of the integrated device can be achieved. In addition, the second transistor 12 is stacked on the surface of the first transistor 11, and the electrodes on the opposite surfaces of the two transistors can be directly connected, so that there is no need to set up a metal wire 14 separately, thereby reducing the number of metal wires 14, effectively reducing the package line resistance, and avoiding the additional introduction of capacitance and inductance. At the same time, stacking the two transistors makes the distance between the two transistors shorter. When the metal wire 14 needs to be set, the length of the metal wire 14 can also be shortened to further reduce the package line resistance, avoid the additional introduction of capacitance and inductance, thereby improving the performance of the integrated device.
[0050] Alternatively, if Figure 4 As shown, the first source 41 and the first gate 43 are located on the same surface of the first transistor 11 , and the first drain 42 and the first source 41 are located on two opposite surfaces of the first transistor 11 , respectively.
[0051] like Figure 5As shown, the second source 121 and the second gate 123 are located on the same surface of the second transistor 12 , and the second drain 122 and the second source 121 are located on two opposite surfaces of the second transistor 12 , respectively.
[0052] like Figure 1 , 3 As shown, the surface of the second transistor 12 provided with the second drain 122 is connected to the surface of the first transistor 11 provided with the first source 41 , and the surface of the first transistor 11 provided with the first drain 42 is connected to the drain plate 132 .
[0053] In the implementation of the present disclosure, the first transistor 11 and the second transistor 12 are both vertical structures. In this way, when the second transistor 12 is stacked on the first transistor 11, the second drain 122 and the first source 41 on the two opposite surfaces of the first transistor 11 and the second transistor 12 can be in direct contact, thereby realizing the electrical connection between the second drain 122 and the first source 41, thereby reducing the setting of the metal wire 14 and effectively reducing the packaging line resistance.
[0054] Alternatively, if Figure 2 , 3 As shown, the orthographic projection of the second transistor 12 on the surface of the substrate 13 is located within the orthographic projection of the first source 41 on the surface of the substrate 13 .
[0055] In the above implementation, since the second drain 122 of the second transistor 12 entirely covers the surface of the second transistor 12 close to the first transistor 11, the outer contour of the second transistor 12 is not allowed to exceed the positive projection of the first source 41 on the substrate 13, and the second drain 122 is prevented from extending to the area on the first transistor 11 other than the first source 41, and the second drain 122 is prevented from being short-circuited with other components on the first transistor 11, thereby improving the reliability of the integrated device.
[0056] Alternatively, if Figure 1 , 2 As shown, the gate plate 133 and the source plate 131 are located in the same plane, and the gate plate 133 and the source plate 131 are arranged alternately, the drain plate 132 is located on the surface of the source plate 131, and the drain plate 132 is insulated from the source plate 131.
[0057] By configuring the substrate 13 to be three mutually insulated electrode plates, an external power source and the substrate 13 are electrically connected, so that the external power source can directly energize each electrode plate to achieve the purpose of injecting current into the transistor.
[0058] For example, Figure 1 , 2As shown, the gate plate 133 is disposed on the substrate 13 in a region close to the second gate 123 , which can shorten the length of the metal wire 14 connecting the second gate 123 and the gate plate 133 , and effectively reduce the package line resistance.
[0059] Optionally, an insulating layer may be disposed between the source plate 131 and the drain plate 132 to achieve insulation between the drain plate 132 and the source plate 131 .
[0060] Exemplarily, the insulating layer may be a silicon oxide layer.
[0061] Alternatively, if Figure 1 , 2 As shown, the integrated device further includes a metal line 14 , and the first gate 43 and the second source 121 , the second source 121 and the source plate 131 , and the second gate 123 and the gate plate 133 are all electrically connected through the metal line 14 .
[0062] For example, Figure 1 , 2 As shown, the first gate 43 and the second source 121 are electrically connected by two metal wires 14. Since the first gate 43 is in a long strip shape and the second source 121 extends along the side of the second transistor 12, the lengths of the first gate 43 and the second source 121 are both relatively long. Thus, providing a plurality of metal wires 14 to connect the first gate 43 and the second source 121 can effectively improve the connection reliability between the first gate 43 and the second source 121.
[0063] For example, Figure 1 , 2 As shown, four metal wires 14 are used to electrically connect the second source 121 and the source plate 131. Since the area of the source plate 131 is the largest electrode plate on the substrate 13, providing a large number of metal wires 14 is conducive to injecting current into the second source 121 from different directions, making the current injection more uniform.
[0064] For example, Figure 1 , 2 As shown, the second gate 123 and the gate plate 133 are electrically connected by a metal wire 14. Since the second gate 123 and the gate plate 133 are both block-shaped, the purpose of current transmission can be met by connecting the first gate 43 and the gate plate 133 by a metal wire 14, which can reduce the number of metal wires 14, thereby reducing the package line resistance.
[0065] Figure 6 is a schematic diagram of the structure of a first transistor provided by an embodiment of the present disclosure. Figure 6 As shown, the first transistor further includes: a channel layer 21 , a barrier layer 22 , a first dielectric layer 31 and a second dielectric layer 32 .
[0066] like Figure 6 As shown, the second dielectric layer 32 , the first dielectric layer 31 , the barrier layer 22 and the channel layer 21 are stacked in sequence, and the surface of the channel layer 21 away from the second dielectric layer 32 has a first groove 210 and a second groove 211 .
[0067] like Figure 6 As shown, the first source 41 and the first gate 43 are both located on the side of the channel layer 21 away from the second dielectric layer 32, and the first source 41 and the first gate 43 are both insulated from the channel layer 21, the first source 41 is electrically connected to the surface of the channel layer 21 close to the second dielectric layer 32 through the first groove 210, and the first gate 43 extends to the second dielectric layer 32 through the second groove 211.
[0068] like Figure 6 As shown, the second dielectric layer 32 has a third groove 320 exposing the channel layer 21 , and the first drain 42 is located on a side of the second dielectric layer 32 away from the channel layer 21 , and is electrically connected to a surface of the channel layer 21 close to the second dielectric layer 32 through the third groove 320 .
[0069] In the first transistor provided by the embodiment of the present disclosure, the first source 41 and the first gate 43 are arranged on the side of the channel layer 21 away from the second dielectric layer 32, and the first drain 42 is arranged on the side of the second dielectric layer 32 away from the channel layer 21, so as to form a transistor with a vertical structure.
[0070] At the same time, the first source 41 and the first gate 43 are insulated from the channel layer 21 on the channel layer 21, wherein the first source 41 extends to the side of the channel layer 21 close to the second dielectric layer 32 through the first groove 210 and is electrically connected to the channel layer 21, so that the current of the first source 41 can be injected from the surface of the channel layer 21 close to the second dielectric layer 32, and the first gate 43 enters the dielectric layer through the second groove 211 and is still insulated from the channel layer 21. The first drain 42 is located on the side of the second dielectric layer 32 away from the channel layer 21, and is electrically connected to the surface of the channel layer 21 close to the second dielectric layer 32 through the third groove 320, so that the current of the first drain 42 is directly injected from the surface of the channel layer 21 close to the second dielectric layer 32. Since the first source 41 and the first drain 42 are both injected from the same surface of the channel layer 21, rather than from the opposite sides of the channel layer 21, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface between the channel layer 21 and the barrier layer 22, so that the transistor can take advantage of the two-dimensional electron gas channel. In this way, the transistor not only takes advantage of the two-dimensional electron gas channel, but also forms a transistor with a vertical structure, thereby reducing the difficulty of transistor application.
[0071] Alternatively, if Figure 6As shown, the first transistor further includes a source metal 51 , which is located in the first groove 210 , and is electrically connected to a surface of the channel layer 21 close to the second dielectric layer 32 . The first source electrode 41 is electrically connected to the source metal 51 through the first groove 210 .
[0072] By forming the source metal 51 in the first groove 210, the source metal 51 can make ohmic contact with the surface of the channel layer 21 close to the second dielectric layer 32 in the first groove 210, so that the source metal 51 and the channel layer 21 are electrically connected, so that the current injected from the first source 41 can be injected into the channel layer 21 from the surface of the channel layer 21 close to the second dielectric layer 32 through the source metal 51.
[0073] Alternatively, if Figure 6 As shown, the first groove 210 includes a first groove body 2101 and a second groove body 2102 connected to each other. The first groove body 2101 at least penetrates the channel layer 21 , and the second groove body 2102 at least penetrates the barrier layer 22 and the first dielectric layer 31 .
[0074] like Figure 6 As shown, the source metal 51 is located in the second groove body 2102, and the end surface of the source metal 51 close to the first groove body 2101 includes a first area and a second area surrounding the first area, the first area is opposite to the first groove body 2101, the second area is electrically connected to the channel layer 21, and the first source electrode 41 is electrically connected to the source metal 51 through the first groove body 2101.
[0075] In the above implementation, the first groove body 2101 will not completely expose the source metal 51, so that the second area of the end surface of the source metal 51 can be electrically connected to the channel layer 21, so that the current input by the first source electrode 41 can be injected into the channel layer 21 from the surface of the channel layer 21 close to the second dielectric layer 32 through the source metal 51.
[0076] Optionally, at least part of the source metal 51 is located at the peripheral edge of the barrier layer 22 and the first dielectric layer 31. By arranging the source metal 51 at the peripheral edge of the first dielectric layer 31 and keeping the source metal 51 away from the central area of the channel layer 21, it is possible to avoid the source metal 51 contacting other metals and causing a short circuit problem.
[0077] Exemplarily, the cross section of the source metal 51 is U-shaped.
[0078] The cross section of the source metal 51 is a cross section of the source metal 51 parallel to the surface of the second dielectric layer 32 .
[0079] By setting the cross-section of the source metal 51 to be U-shaped, the source metal 51 can cover most of the peripheral edges of the channel layer 21, so that current can be injected into the channel layer 21 from a larger area of the channel layer 21, thereby improving the efficiency of the first source electrode 41 injecting current into the channel layer 21.
[0080] Alternatively, if Figure 6 As shown, the first transistor further includes a gate metal 53 , which is located in the second groove 211 , the gate metal 53 is insulated from the channel layer 21 , and the first gate 43 is electrically connected to the gate metal 53 through the second groove 211 .
[0081] like Figure 2 As shown, the second groove 211 includes a third groove body 2111 and a fourth groove body 2112 connected to each other. The third groove body 2111 at least penetrates the channel layer 21 , the barrier layer 22 and the first dielectric layer 31 , and the fourth groove body 2112 is located in the second dielectric layer 32 .
[0082] The depth of the fourth slot body 2112 is less than the thickness of the second dielectric layer 32 , that is, the fourth slot body 2112 does not penetrate the second dielectric layer 32 .
[0083] like Figure 6 As shown, the gate metal 53 is located in the fourth groove body 2112 , and the first gate 43 is electrically connected to the gate metal 53 through the third groove body 2111 .
[0084] In the above implementation, the first gate 43 is arranged on the side of the channel layer 21 away from the second dielectric layer 32, and the first gate 43 can be electrically connected to the gate metal 53 through the second groove 211, thereby also transferring the first gate 43 to the side of the channel layer 21 close to the second dielectric layer 32.
[0085] Optionally, the transistor further includes a drain metal 52 , which is located in the third groove 320 , electrically connected to a surface of the channel layer 21 close to the second dielectric layer 32 , and the first drain electrode 42 is electrically connected to the drain metal 52 through the third groove 320 .
[0086] By forming a drain metal 52 in the third groove 320, the drain metal 52 is in ohmic contact with the channel layer 21. When the first drain electrode 42 is subsequently prepared, the first drain electrode 42 and the drain metal 52 are connected to achieve electrical connection between the first drain electrode 42 and the channel layer 21, thereby improving the connection reliability between the first drain electrode 42 and the channel layer 21.
[0087] Alternatively, if Figure 6 As shown, the third groove 320 includes a fifth groove body 3201 and a sixth groove body 3202 connected to each other. The fifth groove body 3201 at least extends into the second dielectric layer 32 , and the sixth groove body 3202 exposes the channel layer 21 .
[0088] like Figure 6 As shown, the drain metal 52 is located in the sixth groove 3202 , and the drain metal 52 is electrically connected to the channel layer 21 .
[0089] In the above implementation, the drain metal 52 can make ohmic contact with the surface of the channel layer 21 close to the second dielectric layer 32 in the sixth groove 3202, so that the drain metal 52 and the channel layer 21 are electrically connected. In this way, the first drain 42 and the first source 41 both inject current into the surface of the channel layer 21 close to the second dielectric layer 32, so that a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface between the channel layer 21 and the barrier layer 22, so that the transistor can take advantage of the two-dimensional electron gas channel.
[0090] Alternatively, if Figure 6 As shown, the first transistor also includes a bonding metal 60, which is located on the surface of the second dielectric layer 32 away from the channel layer 21, and the bonding metal 60 is electrically connected to the drain metal 52 through the fifth groove body 3201. The first drain 42 is located on the side of the bonding metal 60 away from the channel layer 21, and the first drain 42 is electrically connected to the bonding metal 60.
[0091] By providing the bonding metal 60 and electrically connecting the bonding metal 60 to the drain metal 52 through the third groove 320 , the first drain electrode 42 can be directly electrically connected to the drain metal 52 through the bonding metal 60 , thereby reducing the difficulty of preparing the first drain electrode 42 .
[0092] Alternatively, if Figure 6 As shown, the transistor further includes a silicon substrate 70 . The silicon substrate 70 is located on a surface of the bonding metal 60 away from the channel layer 21 . The first drain 42 is located on a surface of the silicon substrate 70 away from the channel layer 21 .
[0093] The silicon substrate 70 is a conductive substrate, the bonding metal 60 is used to connect the silicon substrate 70 and the drain metal 52 , and the first drain electrode 42 is arranged on the surface of the silicon substrate 70 , so that the first drain electrode 42 can be electrically connected to the drain metal 52 through the silicon substrate 70 .
[0094] Optionally, the orthographic projection of the gate metal 53 on the surface of the second dielectric layer 32 away from the channel layer 21 is U-shaped, and the orthographic projection of the gate metal 53 on the surface of the second dielectric layer 32 away from the channel layer 21 surrounds the orthographic projection of the first drain 42 on the surface of the second dielectric layer 32 away from the channel layer 21.
[0095] Figure 7 FIG. 1 is a flow chart of a packaging method for an integrated device provided by an embodiment of the present disclosure. Figure 7 As shown, the preparation method comprises:
[0096] S11: providing a first transistor, a second transistor and a substrate.
[0097] Among them, the first transistor has a first source, a first drain and a first gate, the second transistor has a second source, a second drain and a second gate, the substrate includes a source plate, a drain plate and a gate plate insulated from each other, the first transistor includes a depletion-type high electron mobility transistor, and the second transistor includes a silicon-based metal oxide semiconductor field effect transistor.
[0098] S12: Fix the first transistor on the substrate so that the first drain is electrically connected to the drain plate.
[0099] S13: stacking the second transistor on the first transistor so that the first source is electrically connected to the second drain.
[0100] S14: using metal wires to connect the first gate and the second source, the second source and the source plate, and the second gate and the gate plate.
[0101] In the integrated device obtained by the packaging method, the first transistor is arranged on the substrate, and the second transistor is stacked on the first transistor. Compared with the related art in which the transistors are arranged side by side on the substrate, the packaging area of the integrated device after packaging can be effectively reduced, and the circuit miniaturization of the integrated device can be realized. In addition, the second transistor is stacked on the surface of the first transistor, and the electrodes on the opposite surfaces of the two transistors can be directly connected, so there is no need to set up metal wires separately, thereby reducing the number of metal wires set, effectively reducing the package line resistance, and avoiding the additional introduction of capacitance and inductance. At the same time, the two transistors are stacked, so that the distance between the two transistors is shorter, and when it is necessary to set a metal wire, the length of the metal wire can also be shortened to further reduce the package line resistance, avoid the additional introduction of capacitance and inductance, thereby improving the performance of the integrated device.
[0102] Step S12 may include: fixing the first drain electrode on the surface of the drain electrode plate by using solder paste or silver glue.
[0103] Exemplarily, the first drain electrode and the drain plate may be fixed by eutectic welding.
[0104] In step S13, a bonding metal layer may be disposed between the first source and the second drain to bond the first source and the second drain together.
[0105] Step S14 may include: using a wire bonding machine to connect the first gate and the second source, the second source and the source plate, and the second gate and the gate plate with metal wires.
[0106] Exemplarily, two metal wires are used to electrically connect the first gate and the second source. Since the first gate is in the shape of a long strip, and the second source extends along the side of the second transistor, the lengths of the first gate and the second source are both relatively long, so that multiple metal wires are provided to connect the first gate and the second source, which can effectively improve the connection reliability of the first gate and the second source.
[0107] Exemplarily, four metal wires are used to electrically connect the second source electrode and the source plate. Since the area of the source plate is the largest electrode plate on the substrate, providing a large number of metal wires is conducive to injecting current into the second source electrode from different directions, making the current injection more uniform.
[0108] Exemplarily, the second gate and the gate plate are electrically connected by a metal wire. Since the second gate and the gate plate are both block-shaped, the purpose of current transmission can be met by connecting the first gate and the gate plate by a metal wire, which can reduce the number of metal wires and thus reduce the package line resistance.
[0109] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. An integrated device, characterized in that: The integrated device comprises: a first transistor (11), a second transistor (12) and a substrate (13); the first transistor (11) has a first source (41), a first drain (42) and a first gate (43); the second transistor (12) has a second source (121), a second drain (122) and a second gate (123); the substrate (13) comprises a source plate (131), a drain plate (132) and a gate plate (133) which are insulated from each other; the first transistor (11) comprises a depletion-type high electron mobility transistor; and the second transistor (12) comprises a silicon-based metal oxide semiconductor field effect transistor; The second transistor (12) is stacked on the first transistor (11), the first transistor (11) is located on the substrate (13), the first source (41) is electrically connected to the second drain (122), the first drain (42) is electrically connected to the drain plate (132), the first gate (43) is electrically connected to the second source (121), the second source (121) is also electrically connected to the source plate (131), and the second gate (123) is electrically connected to the gate plate (133).
2. The integrated device according to claim 1, characterized in that: The first source (41) and the first gate (43) are located on the same surface of the first transistor (11), and the first drain (42) and the first source (41) are respectively located on two opposite surfaces of the first transistor (11); The second source (121) and the second gate (123) are located on the same surface of the second transistor (12), and the second drain (122) and the second source (121) are respectively located on two opposite surfaces of the second transistor (12); The surface of the second transistor (12) provided with the second drain (122) is connected to the surface of the first transistor (11) provided with the first source (41), and the surface of the first transistor (11) provided with the first drain (42) is connected to the drain plate (132).
3. The integrated device according to claim 2, characterized in that: The orthographic projection of the second transistor (12) on the surface of the substrate (13) is located within the orthographic projection of the first source (41) on the surface of the substrate (13).
4. The integrated device according to any one of claims 1 to 3, characterized in that: The gate plate (133) and the source plate (131) are located on the same plane, and the gate plate (133) and the source plate (131) are arranged at intervals, the drain plate (132) is located on the surface of the source plate (131), and the drain plate (132) is insulated from the source plate (131).
5. The integrated device according to any one of claims 1 to 3, characterized in that: The integrated device further comprises a metal wire (14), and the first gate (43) and the second source (121), the second source (121) and the source plate (131), and the second gate (123) and the gate plate (133) are all electrically connected via the metal wire (14).
6. The integrated device according to any one of claims 1 to 3, characterized in that: The first transistor further comprises: a channel layer (21), a barrier layer (22), a first dielectric layer (31) and a second dielectric layer (32); The second dielectric layer (32), the first dielectric layer (31), the barrier layer (22) and the channel layer (21) are stacked in sequence, and a surface of the channel layer (21) away from the second dielectric layer (32) has a first groove (210) and a second groove (211); The first source electrode (41) and the first gate electrode (43) are both located on a side of the channel layer (21) away from the second dielectric layer (32), and the first source electrode (41) and the first gate electrode (43) are both insulated from the channel layer (21); the first source electrode (41) is electrically connected to a surface of the channel layer (21) close to the second dielectric layer (32) through the first groove (210); and the first gate electrode (43) extends to the second dielectric layer (32) through the second groove (211); The second dielectric layer (32) has a third groove (320) exposing the channel layer (21); the first drain (42) is located on a side of the second dielectric layer (32) away from the channel layer (21), and is electrically connected to a surface of the channel layer (21) close to the second dielectric layer (32) through the third groove (320).
7. The integrated device according to claim 6, characterized in that: The first transistor further comprises a source metal (51), the source metal (51) being located in the first groove (210), the source metal (51) being electrically connected to a surface of the channel layer (21) close to the second dielectric layer (32), and the first source electrode (41) being electrically connected to the source metal (51) via the first groove (210).
8. The integrated device according to claim 7, characterized in that: The first groove (210) comprises a first groove body (2101) and a second groove body (2102) which are connected to each other, the first groove body (2101) at least passes through the channel layer (21), and the second groove body (2102) at least passes through the barrier layer (22) and the first dielectric layer (31); The source metal (51) is located in the second groove body (2102), and the end surface of the source metal (51) close to the first groove body (2101) includes a first region and a second region surrounding the first region, the first region is opposite to the first groove body (2101), the second region is electrically connected to the channel layer (21), and the first source electrode (41) is electrically connected to the source metal (51) through the first groove body (2101).
9. A packaging method for an integrated device, characterized in that: The packaging method comprises: A first transistor, a second transistor and a substrate are provided, wherein the first transistor has a first source, a first drain and a first gate, the second transistor has a second source, a second drain and a second gate, the substrate comprises a source plate, a drain plate and a gate plate insulated from each other, the first transistor comprises a depletion-mode high electron mobility transistor, and the second transistor comprises a silicon-based metal oxide semiconductor field effect transistor; Fixing the first transistor on the substrate so that the first drain is electrically connected to the drain plate; stacking the second transistor on the first transistor so that the first source is electrically connected to the second drain; The first gate and the second source, the second source and the source plate, and the second gate and the gate plate are connected by metal wires.
10. The packaging method according to claim 9, characterized in that: Fixing the first transistor on the substrate includes: The first drain electrode is fixed on the surface of the drain electrode plate by using solder paste or silver glue.