Nonlinear error compensation method for inverter of permanent magnet synchronous motor

Abstract

The invention discloses a permanent magnet synchronous motor inverter nonlinear error compensation method, which comprises the following steps of: inputting an input capacitor of an insulated gate bipolar transistor (IGBT) and an output capacitor of the insulated gate bipolar transistor (IGBT) into a voltage error mathematical model; estimating a first coefficient, a second coefficient, a third coefficient and a fourth coefficient in the voltage error mathematical model by using an algorithm of a linear neural network; the first coefficient, the second coefficient, the third coefficient and the fourth coefficient in the voltage error mathematical model obtained through estimation are input into the voltage error mathematical model, and the nonlinear voltage error of the permanent magnet synchronous motor inverter is obtained through output of the voltage error mathematical model. According to the invention, the dead zone effect, the switch tube turn-on delay, the switch tube turn-off delay, the switch tube and diode turn-on voltage drop and the stray capacitance effect are comprehensively considered, an accurate voltage error mathematical model is established, and accurate voltage compensation can be realized.

Description

Technical Field

[0001] The invention relates to a nonlinear error compensation method for a permanent magnet synchronous motor inverter, and belongs to the technical field of voltage error compensation. Background Art

[0002] With the continuous progress of permanent magnet synchronous motor control systems, pulse width modulation technology has been widely used in AC speed control. In AC speed control systems, pulse width modulation technology (PWM) is often used in inverters to convert DC power into adjustable AC power, thereby realizing speed control of AC motors. The advantage of PWM technology is that it can provide efficient energy conversion and precise power control. By adjusting the width and frequency of the pulse, fine control of the output waveform can be achieved to meet the needs of different applications. In a dual closed-loop FOC control system, the on and off of the switch tube is usually controlled by a high-frequency PWM wave, and the fixed DC power is inverted into a continuously changing AC power using the volt-second balance principle. However, due to the inherent characteristics of IGBT, the on and off of the IGBT is not instantaneous, but has a certain delay time. In order to prevent the upper and lower switches of the same bridge arm of the inverter from being turned on at the same time to form a short circuit of the power supply and cause damage to the device, it is necessary to add a delay time to the drive signal of the upper and lower switches of the same bridge arm. During this period of time, both switches are in the off state, which is called the dead time. The existence of dead time realizes the function of protecting the hardware circuit, but it will cause an error between the actual output voltage and the ideal output voltage, thereby causing current harmonics and torque pulsation, which brings challenges to the high-performance control of the motor. In addition, there will be a conduction voltage drop between the IGBT and the freewheeling diode, and the parasitic capacitance inside the IGBT will also affect the turn-on and turn-off delay of the IGBT. The above effects are collectively referred to as the nonlinear factors of the inverter.

[0003] In the initial research on nonlinear error compensation of inverter, most of them only considered the impact of dead time on inverter output. As the research deepened, more and more nonlinear factors were taken into account. There are two main types of traditional compensation strategies: one is based on time pulse compensation, and the other is based on error voltage compensation.

[0004] In traditional time compensation schemes, the on and off delays of the switch tube are regarded as fixed values, and the equivalent dead time is calculated by measurement, and then compensated in the control algorithm. This type of compensation scheme has certain limitations. Due to the accuracy and cost of hardware measurement, the hardware measurement method is not suitable for actual engineering practice.

[0005] The solution based on error voltage compensation abandons the characteristic of over-reliance on hardware detection. Starting from control theory, it fully considers the influence of parasitic capacitance on the inverter output voltage, accurately models the error voltage, and tabulates the nonlinear relationship between the error voltage and input current through offline measurement. It is then compensated in the control system by looking up a table. The compensation process is somewhat complex. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a method for compensating the nonlinear error of a permanent magnet synchronous motor inverter. The online compensation strategy proposed by the present invention can avoid the offline measurement and tabulation link and simplify the compensation scheme. The adaptive compensation strategy proposed by the present invention makes the compensation scheme adaptive and meets the needs of inverters of different models. The present invention proposes to obtain an accurate compensation voltage by updating the weights of the neural network, thereby reducing the voltage error and current harmonics of the inverter output and improving the control performance of the motor.

[0007] Preferably, the present invention provides a method for compensating a nonlinear error of a permanent magnet synchronous motor inverter, comprising:

[0008] Inputting the input capacitance of the insulated gate bipolar transistor IGBT and the output capacitance of the insulated gate bipolar transistor IGBT into the voltage error mathematical model, and using a linear neural network algorithm to estimate the first coefficient k1, the second coefficient k2, the third coefficient k3 and the fourth coefficient k4 in the voltage error mathematical model;

[0009] The first coefficient k1, the second coefficient k2, the third coefficient k3 and the fourth coefficient k4 in the estimated voltage error mathematical model are input into the voltage error mathematical model, and the nonlinear voltage error of the permanent magnet synchronous motor inverter is obtained by using the output of the voltage error mathematical model.

[0010] Preferably, the voltage error mathematical model is expressed as:

[0011]

[0012] Where V err (i a ) is the nonlinear voltage error of the permanent magnet synchronous motor inverter, k1 is the first coefficient, k2 is the second coefficient, k3 is the third coefficient, k4 is the fourth coefficient, i a is the A-phase current, and the current flowing from the inverter to the motor is defined as the positive direction; I thres is the threshold current; T sp is the inverter switching cycle; C p is the parasitic capacitance value; V dc is the DC bus voltage; V ce is the conduction voltage drop of the power tube, V dis the diode conduction voltage drop, T d is the inverter dead time; S a is the A phase voltage duty cycle.

[0013] Preferably, the expressions of the first coefficient, the second coefficient, the third coefficient and the fourth coefficient are:

[0014]

[0015] In the formula, k i (n) is the weight value at the current moment; k i (n-1) is the weight value at the previous moment; μ is the learning rate, x i (n) is the input value; is the expected value of current harmonics, i h (n) is the current harmonic extraction.

[0016] Preferably, the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any one of the methods described in the first aspect when executing the program.

[0017] Preferably, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect.

[0018] The beneficial effects achieved by the present invention are:

[0019] 1. The present invention comprehensively considers the dead zone effect, switch tube turn-on delay, switch tube turn-off delay, switch tube and diode conduction voltage drop and parasitic capacitance effect, establishes an accurate voltage error mathematical model, and can achieve accurate voltage compensation.

[0020] 2. The adaptive compensation strategy proposed in the present invention can realize online compensation, does not rely on cumbersome compensation methods such as offline measurement and tabulation, and can meet different actual working conditions.

[0021] 3. The present invention proposes to obtain accurate compensation voltage by updating the neural network weights, thereby reducing the voltage error and current harmonics output by the inverter and improving the control performance of the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 is a flow chart of an embodiment of the present invention.

[0024] Figure 2 FIG. 4 is a simplified schematic diagram of an internal circuit of an IGBT according to an embodiment of the present invention.

[0025] Figure 3 Schematic diagram of a Miller platform according to an embodiment of the present invention.

[0026] Figure 4 Schematic diagram of an equivalent parasitic capacitor inverter according to an embodiment of the present invention.

[0027] Figure 5 It is a schematic diagram of voltage distortion caused by parasitic capacitance of an inverter according to an embodiment of the present invention.

[0028] Figure 6 It is a schematic diagram of the error voltage when the current is greater than 0 according to an embodiment of the present invention.

[0029] Figure 7 It is a schematic diagram of the error voltage when the current is less than 0 according to an embodiment of the present invention.

[0030] Figure 8 Schematic diagram of a harmonic extraction module according to an embodiment of the present invention.

[0031] Fig. 9 Schematic diagram of an adaptive linear neural network according to an embodiment of the present invention.

[0032] Fig.10 Schematic diagram of neural network weight update according to an embodiment of the present invention.

[0033] Fig.11 It is a nonlinear error compensation control block diagram based on an adaptive linear neural network algorithm according to an embodiment of the present invention.

[0034] Fig.12 4 is a compensation voltage waveform diagram using the proposed nonlinear error compensation solution according to an embodiment of the present invention.

[0035] Fig.13 is a comparison diagram of inverter output currents of an uncompensated solution according to an embodiment of the present invention;

[0036] Fig.14 4 is a comparison diagram of inverter output currents of the compensation solution proposed in the embodiment of the present invention. DETAILED DESCRIPTION

[0037] See also Figure 1 The present application discloses a method for compensating a nonlinear error of a permanent magnet synchronous motor inverter based on an adaptive linear neural network algorithm, the method comprising the following steps:

[0038] S1: The influence of the parasitic capacitance of the inverter insulated gate bipolar transistor (IGBT) on the nonlinear voltage error of the inverter is analyzed.

[0039] S2: Comprehensively consider the dead zone effect, switch turn-on delay, switch turn-off delay, switch and diode conduction voltage drop and parasitic effects to establish an accurate voltage error mathematical model.

[0040] S3: A voltage error mathematical model based on an adaptive linear neural network algorithm is proposed to achieve accurate compensation of nonlinear voltage errors.

[0041] Comprehensively consider the dead zone effect, switch tube turn-on delay, switch tube turn-on delay, switch tube and diode conduction voltage drop and parasitic effects, and establish an accurate voltage error mathematical model, including:

[0042] Parasitic capacitance is an inherent characteristic of the insulated gate bipolar transistor (IGBT), and plays an important role in the gate drive voltage during the switching process of the insulated gate bipolar transistor (IGBT). When analyzing nonlinear factors, the parasitic capacitance has different effects depending on the current size, so a quantitative analysis is required.

[0043] The simplified internal schematic diagram of the insulated gate bipolar transistor IGBT is as follows Figure 2 As shown, the feedback capacitance expression is as follows, and this capacitance is also called Miller capacitance:

[0044] C res =C CG

[0045] The input capacitance of the insulated gate bipolar transistor IGBT is:

[0046] C ies =C GE +C res

[0047] The output capacitance of the insulated gate bipolar transistor IGBT is:

[0048] C oss =C CE +C res

[0049] Feedback capacitance and input capacitance have a greater impact on gate drive performance. Output capacitance generally affects the voltage change rate during switching, but the loss is small and can be ignored. Miller capacitance will cause the driving voltage to produce a Miller platform. Figure 3 shown.

[0050] Miller capacitance will generate an instantaneous current to charge the IGBT gate, which may cause misleading conduction. Therefore, it should be taken into account when analyzing nonlinear factors. p Instead, the inverter equivalent model is as follows Figure 4 shown.

[0051] When the parasitic capacitance Start charging, lower parasitic capacitance The discharge forms the flow of phase current, at this time the voltage u AN =u cp ,u cp The terminal voltage with lower parasitic capacitance is the discharge duration. Since the discharge duration varies with the phase current, it usually increases with the decrease of phase current. Therefore, when the current of phase a is greater than zero, the fall time will increase with i. a When the current of phase A is less than zero, due to i a The diode will continue to flow, and in this case the rise time is similar to i a Without considering the voltage drop, the voltage distortion caused by the inverter parasitic capacitance is as follows: Figure 5 shown.

[0052] in i a When the parasitic capacitance is greater than 0, it will present a voltage gain. a When <0, voltage loss occurs, which is the opposite of the error effect caused by the dead time. Therefore, if compensation is performed using the voltage error value without considering the parasitic capacitance, the problem of compensating for the larger or smaller value will occur. Especially when the current is small, the influence of the parasitic capacitance accounts for a large proportion, resulting in the opposite compensation effect.

[0053] According to the capacitor charging expression:

[0054]

[0055] If the current Dead time when the phase voltage reaches V dc Otherwise, the phase voltage will reach V before the dead time ends. dc When the capacitor charging and discharging time is equal to the dead time, let the current threshold be I thres . According to the area equivalence principle:

[0056] When-I thres <i a <0 hours:

[0057]

[0058] Combined to get:

[0059]

[0060] when i a =-I thres hour:

[0061]

[0062] when ia <-I thres hour:

[0063]

[0064] Combining the above formulas, we can get:

[0065]

[0066] Error voltage analysis considering the influence of parasitic capacitance, such as Figure 6 , Figure 7 As shown in the figure, the current is greater than 0 and less than 0 respectively. After taking the dead time, tube voltage drop, turn-on and turn-off time and parasitic capacitance into consideration, the current threshold is:

[0067]

[0068] Depend on Figure 6 Comprehensive analysis shows that: ① When T2 is turned off and T1 is turned on, the phase voltage is at T d The function is always pulled low, during this period, Maintain the DC bus voltage, is 0; point ② is T d Afterwards, I a Flowing through the upper power tube, at this time connected to the DC bus, since C p - There is a large charging current, which increases its voltage. Discharge through T1, in this case, the voltage edge appears a spike; point ③ is when T2 is turned on and T1 is turned off, i a Start to Charging reduces the phase voltage, and the slope of the decline is proportional to the phase current; at point ④, due to the small current value, at T d The internal phase voltage has not dropped to 0. When T1 is turned on, the voltage is forced to drop to 0. At points ⑤ and ⑥, the voltage drops faster due to the large current. d It dropped to 0 before it ended.

[0069] Depend on Figure 7 Comprehensive analysis shows that: Similar to the analysis when the current is positive, at point ①, T2 is turned off, T1 is turned on, and the current begins to Charging, the phase voltage begins to rise; Point ② has a small current amplitude at T d The internal phase voltage has not risen to the DC bus voltage value. When the upper tube is turned on, the voltage rises immediately. At point ③, T2 is turned on and T1 is turned off. d Inside Maintain the DC bus voltage value, The voltage value is 0; point ④ is T d After that, the current flow path is from D1 to T2. When charging through T2, the voltage value rises to the DC bus voltage. At the same time, due to the existence of large charging current, the phase voltage edge also has a spike. Points ⑤ and ⑥ are when the absolute value of the current is large, the voltage rises faster. d It can rise to the DC bus voltage value within a few seconds.

[0070] Analyze this:

[0071] 0<i a <I thres :

[0072] i a >I thres :

[0073] -I thres <i a <0:

[0074] i a <-I thres :

[0075] According to the area equivalence principle, it can be concluded that within a control cycle, the voltage error V err (i a )=V dc S a -u ao Right now:

[0076]

[0077] The above formula can be simplified as:

[0078]

[0079] in:

[0080]

[0081] The voltage error in the three-phase stationary coordinate system is converted into the voltage in the two-phase stationary coordinate system through Clarke transformation, and expanded into:

[0082]

[0083] Among them, if the motor is regarded as a time-resistance inductive load, the current error is:

[0084]

[0085] From the above formula, it can be obtained that the current harmonics in the stationary coordinate system are mainly the 5th and 7th harmonics, and the stationary coordinate system is transformed by Park to obtain a two-phase synchronous rotating coordinate system. Among them, the 5th and 7th harmonics in the stationary coordinate system are expressed as the 6th harmonic in the rotating coordinate system after the coordinate change.

[0086] The compensation strategy is mainly divided into the harmonic extraction module and the error voltage online compensation module. The harmonic extraction module includes the following steps:

[0087] According to the abc / dq coordinate transformation principle, when the synthetic vector rotates at the same speed as the dq coordinate system, its component projected on the dq coordinate system is a DC quantity. Based on this, if the 5th harmonic is projected on the coordinate system at a rotation speed of 5ω, the 5th harmonic is a DC component, and the fundamental wave and the 7th harmonic are AC components; similarly, if the 7th harmonic is projected on the coordinate system at a rotation speed of 7ω, the 7th harmonic is a DC component, and the fundamental wave and the 5th harmonic are AC components.

[0088] According to the above principle, the 5th and 7th harmonic components in the stationary coordinate system are transformed at their respective synchronous rotation speeds to obtain the harmonic DC components on the dq axis. Among them, the rotation direction of the 5th harmonic is opposite to that of the fundamental wave, and the rotation direction of the 7th harmonic is the same as that of the fundamental wave. After filtering out the non-DC amount through a low-pass filter, the 5th and 7th harmonic DC components can be obtained. After the inverse coordinate transformation, the 5th and 7th harmonic components in the abc stationary coordinate system can be obtained. Figure 8 It is the harmonic extraction module.

[0089] The steps of the error voltage online compensation strategy based on the adaptive linear neural network algorithm are as follows:

[0090] According to the accurate model of the nonlinear error voltage of the inverter mentioned above, the error voltage can be obtained as:

[0091]

[0092] It can be seen that the error voltage is mainly related to k1, k2, k3 and k4, and these four coefficients are relatively complex and difficult to measure directly. The linear neural network algorithm will be used to estimate the coefficients. Taking phase A as an example, the relationship between the error voltage and current can be calculated using a linear neural network. Fig. 9 express.

[0093] k i(i＝1,2,3,4) It can be regarded as the weight of the neural network at the current sampling moment, which is updated and adjusted by the least squares method:

[0094]

[0095] Among them, k i (n) is the weight value at the current moment; ki (n-1) is the weight value at the previous moment; μ is the learning rate, which is used to adjust the convergence speed of the neural network. The larger μ is, the faster the convergence speed is, but it is also more unstable, so a suitable learning rate should be selected. The selection of learning rate has the following rules: 0<2μx n 2 <1;x i (n) is the input value; is the expected value of current harmonics, set to 0; i h (n) is the current harmonic extraction value.

[0096] With 0<i a <I thres Take the adaptive linear neural network weight update principle diagram as an example. Fig.10 The same is true for other situations.

[0097] The calculated voltage error is used as the inverter nonlinear error compensation value, and the abc three-phase voltage error value is transformed into the αβ coordinate system and compensated to V α ,V β , to achieve the purpose of suppressing the 5th and 7th harmonics, the nonlinear error compensation block diagram is as follows Fig.11 shown.

[0098] In the embodiment of the present invention, an inverter nonlinear error compensation scheme based on an adaptive linear neural network algorithm is used, and the compensation voltage is as follows: Fig.12 As shown in Figure 2, the inverter output current before and after compensation is as follows: Fig.14 As shown in the figure, the uncompensated inverter has a high output current distortion rate and current clamping phenomenon; the compensated inverter has a lower output current harmonic content and a high degree of sinusoidalization. Compared with the traditional control scheme, the proposed method effectively reduces the current harmonics and improves the control performance.

[0099] In an embodiment of the present application, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any of the above methods when executing the program.

[0100] In an embodiment of the present application, the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0101] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0102] Those skilled in the art will readily appreciate other embodiments of the invention after considering the specification and practicing the invention invented herein. This application is intended to cover any variations, uses or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art that are not invented by the present invention. The specification and examples are intended to be exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0103] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above are only specific implementation methods of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

Claims

1. A method for compensating nonlinear errors of a permanent magnet synchronous motor inverter, characterized in that: include: Inputting the input capacitance of the insulated gate bipolar transistor IGBT and the output capacitance of the insulated gate bipolar transistor IGBT into the voltage error mathematical model, and using a linear neural network algorithm to estimate the first coefficient k1, the second coefficient k2, the third coefficient k3 and the fourth coefficient k4 in the voltage error mathematical model; The first coefficient k1, the second coefficient k2, the third coefficient k3 and the fourth coefficient k4 in the estimated voltage error mathematical model are input into the voltage error mathematical model, and the nonlinear voltage error of the permanent magnet synchronous motor inverter is obtained by using the output of the voltage error mathematical model.

2. The method for compensating a nonlinear error of a permanent magnet synchronous motor inverter according to claim 1, characterized in that: The expression of the voltage error mathematical model is: Where V err (i a ) is the nonlinear voltage error of the permanent magnet synchronous motor inverter, k1 is the first coefficient, k2 is the second coefficient, k3 is the third coefficient, k4 is the fourth coefficient, i a is the A-phase current, and the current flowing from the inverter to the motor is defined as the positive direction; I thres is the threshold current; T sp is the inverter switching cycle; C p is the parasitic capacitance value; V dc is the DC bus voltage; V ce is the conduction voltage drop of the power tube, V d is the diode conduction voltage drop, T d is the inverter dead time; S a is the A phase voltage duty cycle.

3. The method for compensating a nonlinear error of a permanent magnet synchronous motor inverter according to claim 2, characterized in that: The expressions for the first coefficient, the second coefficient, the third coefficient, and the fourth coefficient are: In the formula, k i (n) is the weight value at the current moment; k i (n-1) is the weight value at the previous moment; μ is the learning rate, x i (n) is the input value; is the expected value of current harmonics, i h (n) is the current harmonic extraction.

4. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 3 are implemented.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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