High-precision delay synchronization system with phase jitter compensation function

Abstract

The invention discloses a high-precision delay synchronization system with a phase jitter compensation function. The high-precision delay synchronization system comprises an upper computer, an external trigger module, a time reference module, a master control ZYNQ module, a frequency synthesis and trigger mode selection module, a jitter compensation module, a precise delay circuit and an output signal conditioning circuit. According to the invention, the pulse output with adjustable delay time, amplitude and polarity can be realized, the high-precision delay synchronization of signals is realized, and the stability is higher.

Description

Technical Field

[0001] The present invention belongs to the technical field of precision synchronization systems, and in particular relates to a high-precision delay synchronization system with a phase jitter compensation function. Background Art

[0002] The precision synchronization system, as a timing control component, can accurately delay the external trigger signal to generate the required synchronization signal, and can also send out multiple timing pulses by itself. As a timing control component, the precision synchronization system is widely used in inertial confinement fusion, radar, high-speed imaging, mass spectrometer, spectral instrument, attosecond laser physics and ultrafast optics.

[0003] The core content of the precision synchronization system is to propose a precision synchronization system architecture consisting of FPGA, digital circuit and analog circuit jitter compensation module. Through counter delay technology, a large range of coarse delay is obtained. A constant current source with a specific charging speed is designed to charge a capacitor with a specific capacitance value, thereby achieving a precise delay effect. The time variable is converted into an adjustable voltage variable. Since the jitter of the output signal will be affected by the clock cycle of the digital circuit, this random jitter time is processed in the form of voltage, and then a trigger jitter compensation circuit is constructed together with the analog delay circuit and the comparison output circuit, so that this trigger jitter time is converted into a fixed delay.

[0004] The existing pulse delay generator system has the following main problems: there is a large time jitter between the external input trigger signal and the pulse delay generator output pulse signal, the time jitter between the pulse signals output by the pulse delay generator is large, and the delay time resolution of the pulse output by the pulse delay generator is low. Therefore, it is very meaningful to propose a pulse delay generator that can generate high delay time resolution, low time jitter and small pulse rise time. Summary of the invention

[0005] In order to make up for the deficiencies of the prior art, the present invention provides a high-precision delay synchronization system with a phase jitter compensation function to achieve high-precision delay of a trigger pulse and have higher stability.

[0006] The high-precision delay synchronization system with phase jitter compensation function comprises a host computer, an external trigger module, a time reference module, a main control ZYNQ module, a frequency synthesis and trigger mode selection module, a jitter compensation module, a precision delay circuit and an output signal conditioning circuit.

[0007] The external trigger module is used to generate a high-frequency external reference signal;

[0008] The time reference module is used to generate the system master 100 MHZ clock, and can selectively lock the master clock to an internal oscillator or an external clock source;

[0009] The master control ZYNQ module is used to implement some medium-speed logic interfaces in the system, including SPI, counters for system coarse delay, and state machines;

[0010] The frequency synthesis and trigger mode selection module is used to generate a trigger signal of arbitrary waveform, frequency and amplitude, and to guide the source trigger signal to the time-to-voltage converter and select the trigger mode;

[0011] The jitter compensation module is used to collect the jitter error between the rising edge of the trigger signal and the rising edge of the system clock, and convert the uncertain time amount into a certain voltage amount;

[0012] The precision fine delay circuit is used to eliminate trigger jitter together with the jitter compensation module and realize precision fine delay with a resolution of hundreds of picoseconds;

[0013] The output signal conditioning circuit is used to condition the output pulses of each channel of the system, including amplitude, bias, and polarity;

[0014] The 100MHZ generated by the time reference module is used as the clock reference of each module in the whole system, and the jitter compensation module is triggered to measure the phase difference between the rising edge of the trigger signal and the rising edge of the 100MHZ time base by charging the capacitor, and the coarse delay is started. After the coarse delay ends, the fine delay is turned on. The time of the coarse delay and the fine delay is set by the host computer; the fine delay circuit is realized by charging and discharging the capacitor, and the delay signal passes through the voltage comparison module. When it is discharged to the same level as the phase difference, the synchronization system generates an output delay pulse; the output pulse is finally converted into a pulse output with adjustable delay time, amplitude and polarity through the output conditioning circuit.

[0015] Furthermore, the external trigger module includes a mode-locked laser and a high-speed optical detector.

[0016] The mode-locked laser is used to generate periodic optical pulses, and includes a pump source, an acousto-optic modulator, a pointing mirror and an oscillator connected in sequence, wherein the pump source is used to inject energy to excite oscillation and realize optical amplification; the acousto-optic modulator is used to control the frequency and characteristics of light; the pointing mirror is used to reflect the laser beam back to the oscillation cavity to form an optical cavity; the oscillation cavity generates laser pulses; and the laser pulses are regulated and stably outputted through the control of the pump source and the acousto-optic modulator;

[0017] The femtosecond laser electric pulse sequence received by the high-speed photodetector can be used as a stable external frequency trigger signal.

[0018] Furthermore, the time reference module includes an external input reference selection circuit, a circuit for selecting an internal or external referenceable 10MHz reference signal, a multiplexer, a phase-locked loop circuit, a clock distribution circuit, and a frequency division circuit. The phase-locked loop circuit includes a frequency detector, a phase detector, a loop filter, and a voltage-controlled oscillator. The frequency and phase of the internal oscillation signal of the loop are controlled by using an external input reference signal or an internal optional constant temperature crystal oscillator to realize automatic tracking of the output signal frequency to the input signal frequency. The frequency division circuit includes a single-channel high-speed receiver, a frequency divider, and a D flip-flop.

[0019] Furthermore, the master control ZYNQ module includes a power supply, a mode and a BANK, wherein the power supply includes all power supply lines; the mode includes all pins related to the ZYNQ configuration, and the logic module corresponds to the architecture block within the ZYNQ; the initial value and the coarse delay range of the counter are set, and the bit width of the counter is calculated according to the delay requirement. After each system clock, the value of the counter is accumulated, and when the count reaches a preset value, the counting process ends, thereby realizing the coarse delay of the system.

[0020] Furthermore, the frequency synthesis and trigger mode selection module includes a high-speed DDS, a Chebyshev filter, a D trigger, a high-speed receiver and a multiplexer. The working process is as follows: the buffered SPI interface of the master control ZYNQ is used to read and write register data to the high-speed DDS, and the high-speed DDS outputs to the internal digital-to-analog converter in a differential current mode, and is filtered by a Chebyshev low-pass filter to reduce the harmonic content, so that the high-speed DDS generates a drive signal with controllable frequency, phase and amplitude; finally, the trigger mode of the synchronization system is selected through the multiplexer.

[0021] Furthermore, the jitter compensation module includes a DAC, a trigger enable, a trigger establishment circuit, a cascaded D flip-flop, a constant current source circuit, an emitter-coupled high-speed switch circuit and a charging capacitor; the master control ZYNQ module allows the synchronization system to receive a trigger signal through a logic gate. When the trigger signal is captured, the output level of the cascaded D flip-flop jumps, causing the emitter-coupled high-speed switch to be turned off, thereby controlling the charging time of the constant current source for the charging capacitor, realizing the acquisition of the phase difference between the trigger source and the system 100MHz clock, completing the trigger jitter measurement, and the measured phase difference voltage is output after passing through the voltage comparison circuit to realize jitter compensation.

[0022] Furthermore, the precision fine delay module includes two high-speed differential receivers, a D flip-flop, a constant current source circuit, a DAC, a charging capacitor, and a voltage comparison circuit. The DAC is used to set the precision delay time required by the synchronization system. The precision delay enable signal and the 100MHz ultra-stable time base are transmitted in the form of differential signals. The high-speed differential receiver is used to convert the differential signal into a single-ended signal for processing. The two signals are then re-clocked through the D flip-flop to cause the constant current source circuit to discharge the charging capacitor, which is then compared with the voltage comparison circuit and the trigger jitter voltage. When the discharge is equal to the two, the delay signal is output in the form of a differential signal.

[0023] Furthermore, the output signal conditioning circuit includes a high-speed differential receiver, a logic gate circuit, a differential driver and an amplitude bias adjustment circuit. After the high-speed differential receiver receives the delay signal output by the precision delay module, it converts the differential signal into a single-ended signal. The switch signal controlled by the main control ZYNQ module acts on the logic gate circuit to condition the delay signal; and the signal is amplitude modulated and biased through the amplitude bias adjustment circuit.

[0024] Furthermore, if external triggering is selected, the mode-locked laser in the external triggering module generates a high-stability mode-locked laser pulse, which is converted into a femtosecond laser electrical pulse sequence by the high-speed photodetector in the external triggering module as a stable external frequency trigger signal; if internal triggering is selected, the digital frequency synthesizer generates a drive signal with controllable frequency, phase and amplitude as a system trigger signal, and the frequency, phase and amplitude are controlled by the host computer.

[0025] Compared with the prior art, the present invention has the following advantages: the present invention can realize pulse output with adjustable delay time, amplitude and polarity, realize high-precision delay synchronization of signals, and has higher stability. By accurately delaying the external trigger signal to generate the required synchronization signal, the delay system is divided into a coarse delay for counting the system clock by the internal counter of the system, and a fine delay for charging the capacitor; that is, the external 10MHz frequency reference signal is used as the frequency input of the phase-locked loop module to generate a 100MHz ultra-stable system time reference, and the selectable external trigger signal trigger circuit generates an internal trigger signal with adjustable frequency, amplitude and phase. At the same time, the trigger and the 100MHZ time base are synchronized, and the main control ZYNQ series expandable processing platform is enabled to start coarse delay counting; the ramp signal of the precision fine delay circuit converts the precision delay time preset by the host computer into a voltage value through the charging of the capacitor by the high-precision constant current source, and works with the jitter compensation module to compensate for the jitter between the trigger signal and the rising edge of the clock; and the output waveform generated from the ramp is processed by the signal conditioning circuit, and the polarity and amplitude of its output are regulated. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a module diagram of the synchronization system of the present invention;

[0027] Figure 2 It is a module diagram of the external trigger module of the present invention;

[0028] Figure 3 A module diagram of a time reference module of the present invention;

[0029] Figure 4 A module diagram of a frequency synthesis and trigger mode selection module of the present invention;

[0030] Figure 5 is a module diagram of a jitter compensation module of the present invention;

[0031] Figure 6 It is a module diagram of the precision fine delay circuit of the present invention;

[0032] Figure 7 It is a module diagram of the output signal conditioning circuit of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to more clearly understand the technical solution of the present invention, a high-precision delay synchronization system with a phase jitter compensation function of the present invention is further described below in conjunction with the accompanying drawings.

[0034] like Figure 1 As shown, a high-precision delay synchronization system with phase jitter compensation function includes a host computer, an external trigger module, a time reference module, a master ZYNQ module, a frequency synthesis and trigger mode selection module, a jitter compensation module, a precision fine delay circuit and an output signal conditioning circuit, wherein the external trigger module is used to generate a high-frequency external reference signal; the time reference module is used to generate a system main 100MHZ clock, and the main clock can be selectively locked to an internal oscillator or an external clock source; the master ZYNQ module is used to implement some medium-speed logic interfaces in the system, including SPI, for system coarse delay The module is used to generate a trigger signal of any waveform, frequency and amplitude, and leads the source trigger signal to the time-to-voltage converter, and selects the trigger mode; the jitter compensation module is used to collect the jitter error between the rising edge of the trigger signal and the rising edge of the system clock, and convert the uncertain time into a certain voltage; the precision delay circuit is used to eliminate the trigger jitter together with the jitter compensation module, and realize the precision delay with a resolution of hundreds of picoseconds; the output signal conditioning circuit is used to condition the output pulses of each channel of the system, including amplitude, bias and polarity.

[0035] The synchronization system of the present application can choose one of the two triggering modes, the external triggering module and the frequency synthesis module, to adapt to different application scenarios. If the external trigger is selected, the mode-locked laser pulse with high stability is generated by the mode-locked laser in the external triggering module, which is converted into a femtosecond laser electric pulse sequence by the high-speed photodetector in the external triggering module as a stable external frequency trigger signal; if the internal trigger is selected, the digital frequency synthesizer generates a drive signal with controllable frequency, phase and amplitude as the system trigger signal, and the frequency, phase and amplitude are controlled by the host computer.

[0036] It can be understood that the 100MHZ generated by the time reference module is used as the clock reference for each module of the entire system. The trigger jitter compensation module measures the phase difference between the rising edge of the trigger signal and the rising edge of the 100MHZ time base by charging the capacitor, and starts the coarse delay. After the coarse delay ends, the fine delay is turned on. The time of the coarse delay and the fine delay is set by the host computer; the fine delay circuit is realized by charging and discharging the capacitor, and the delay signal passes through the voltage comparison module. When it is discharged to the same level as the phase difference, the synchronization system generates an output delay pulse; the output pulse is finally converted into a pulse output with adjustable delay time, amplitude, and polarity through the output conditioning circuit.

[0037] like Figure 2 As shown, the external trigger module in the present application includes a mode-locked laser and a high-speed photodetector. The mode-locked laser is used to generate periodic light pulses, including a pump source, an acousto-optic modulator, a pointing mirror and an oscillator connected in sequence. The pump source is used to inject energy to excite oscillation and realize light amplification; the acousto-optic modulator is used to control the frequency and characteristics of light; the pointing mirror is used to reflect the laser beam back to the oscillation cavity to form an optical cavity; the oscillation cavity generates laser pulses; the laser pulses are regulated and stably output by controlling the pump source and the acousto-optic modulator; the femtosecond laser electrical pulse sequence received by the high-speed photodetector can be used as a stable external frequency trigger signal.

[0038] like Figure 3 As shown, the time reference module of the present application includes an external input reference selection circuit, a 10MHz reference signal that can be selected internally or externally, a multiplexer, a phase-locked loop circuit, a clock distribution circuit, and a frequency division circuit. The phase-locked loop circuit includes a frequency detector, a phase detector, a loop filter, and a voltage-controlled oscillator. The frequency and phase of the internal oscillation signal of the loop are controlled by using an external input reference signal or an internal optional constant temperature crystal oscillator to realize automatic tracking of the output signal frequency to the input signal frequency; the frequency division circuit includes a single-channel high-speed receiver, a frequency divider, and a D flip-flop. Among them, the external input reference selection circuit can select an internal 10MHz constant temperature crystal oscillator (selection 1) or an external wiring signal generator 10MHz (selection 2), and one of the two can be selected as the reference frequency of the time reference module.

[0039] In the present application, the phase-locked loop circuit includes a frequency detector, a loop filter and a voltage-controlled oscillator, and uses an external input reference signal or an internal optional constant temperature crystal oscillator to control the frequency and phase of the oscillation signal inside the loop, so as to realize the automatic tracking of the output signal frequency to the input signal frequency. The phase detector is used to compare the frequency and phase of the input 10MHz reference frequency and the feedback frequency, and convert the phase difference into a voltage signal and transmit it to the charge pump to generate a voltage signal. After filtering by the loop filter, it is input into the voltage-controlled oscillator to generate a 100MHz time reference signal of the system. The phase-locked loop configuration circuit and the phase detector are transmitted with the master control through SPI communication, including chip selection, clock and data transmission and reception. The driving signal outputs the clock of the phase-locked loop and the slave input signal through two or gates, which is used to configure the load enable port of the PLL phase-locked loop. When the chip select signal is high, the clock signal is pulled high to ensure the stability of data transmission. In the absence of a reference, the phase-locked loop chip select is driven to a low level, the phase-locked loop is disabled, and the output linearity of the voltage-controlled oscillator is met by setting the DAC calibration voltage to ensure that the output is a 100MHz clock reference.

[0040] In the clock distribution output circuit, the voltage-controlled oscillator signal passes through a 1:5 differential driver, and then impedance matching is performed before it is led to the jitter compensation module and the precision delay as a reference time base. In the jitter compensation module, the clock signal of the differential input is converted to a single-ended output through a single-channel high-speed receiver, and the trigger source signal and the time base signal are passed through two cascaded D flip-flops to generate an output delay of one clock cycle. Since the two D flip-flops are clocked by the same source, the output delay of the previous D flip-flop signal is 10ns before the clock is processed by the subsequent D flip-flop, thereby eliminating any metastable state. The output signal of the subsequent D flip-flop is synchronized with the 100MHz time base and used to start the ZYNQ coarse counting cycle. In the precision delay module, the single-channel high-speed receiver processes the delay end signal and time base from the ZYNQ, and enters the D flip-flop for resynchronization, minimizing any timing interference from adjacent channels.

[0041] The frequency division circuit includes a single-channel high-speed receiver, a frequency divider and a D flip-flop. The 100MHz clock signal is pre-divided and divided by 2 through the frequency divider and the D flip-flop, and a 10MHz signal is output for external reference.

[0042] In this application, the main control ZYNQ module includes power supply, mode and BANK, the power supply includes all power supply lines; the mode includes all pins related to the ZYNQ configuration, and the logic module corresponds to the architecture block in ZYNQ; the initial value and coarse delay range of the counter are set, and the bit width of the counter is calculated according to the delay requirement. After each system clock, the value of the counter is accumulated. When the count reaches the preset value, the counting process ends and the system coarse delay is realized. Among them, the core feature of the ZYNQ series is the integration of ARM processor and FPGA (field programmable gate array) on a single chip. Specifically, the main control ZYNQ module contains a dual-core ARM Cortex-A9 processing system (PS) and a programmable logic part (PL), which enables it to have both the high-performance computing capability of the processor and the flexibility and parallel processing capability of the FPGA. The coarse delay of the synchronous system is realized by the main control ZYNQ module.

[0043] like Figure 4 As shown, the frequency synthesis and trigger mode selection module includes a high-speed DDS, a Chebyshev filter, a D flip-flop for resynchronizing and scaling the high-speed DDS output, a high-speed receiver for receiving an external trigger signal, and a multiplexer for trigger mode selection. When the clock is 100 MHz, the DDS provides a 12-bit current source output.

[0044] The specific workflow is as follows: the buffered SPI interface of the master control ZYNQ is used to read and write register data to the high-speed DDS, which outputs to the internal digital-to-analog converter in differential current mode, and is filtered through a Chebyshev low-pass filter to reduce the harmonic content, and then the high-speed DDS generates a drive signal with controllable frequency, phase, and amplitude; finally, the trigger mode of the synchronization system is selected through a multiplexer. Among them, the trigger mode selection module realizes the selection of internal and external trigger modes by selecting the high and low levels of the single-channel logic switch.

[0045] like Figure 5 As shown, the jitter compensation module includes DAC, trigger enable, trigger establishment circuit, cascade D flip-flop, constant current source circuit, emitter coupled high-speed switch circuit and charging capacitor; the main control ZYNQ module allows the synchronous system to receive the trigger signal, i.e., trigger enable, through the logic gate. The data must be stable within a certain period of time before the arrival of the effective edge of the clock, otherwise the trigger cannot latch the data, so a fixed time is required for establishment. The charging rate of the current source circuit is calibrated by setting the value of the DAC; when the trigger signal is captured, the output level of the cascade D flip-flop jumps, causing the emitter coupled high-speed switch to turn off, thereby controlling the charging time of the constant current source to the charging capacitor, realizing the acquisition of the phase difference between the trigger source and the system 100MHz clock, completing the trigger jitter measurement, and the measured phase difference voltage is output after passing through the voltage comparison circuit to realize jitter compensation.

[0046] The trigger jitter measurement circuit uses a stable current source to charge the charging capacitor. According to the law that the voltage across the charging capacitor is proportional to the charging time, a high-precision constant current source is used to charge, and the time quantity is converted into a voltage signal, thereby measuring the jitter caused by the partial trigger. The jitter time is uncertain relative to the system synchronization clock. In order to eliminate this uncertainty, the jitter time is measured and recorded each time, and the time quantity is converted into a voltage quantity. Constant current source circuit is used to provide a circuit for providing a stable output current. It includes a DC voltage source, an operational amplifier, a comparison amplifier and a transistor. The DC voltage source is used to provide a stable DC voltage. The feedback loop formed by the operational amplifier takes the voltage output by the DC voltage source as input, and amplifies and feeds back through the operational amplifier to stabilize the output. The comparison amplifier compares the output of the feedback loop with the voltage after the DC voltage source is divided to generate an error signal. According to the error signal output by the comparison amplifier, the working state of the transistor is adjusted, thereby adjusting the output current of the constant current source. By continuously adjusting the input voltage, the error signal generated by the comparison amplifier is used to control the transistor so that the output current remains at a constant value.

[0047] The emitter-coupled high-speed switch circuit is essentially a current switch composed of two pairs of symmetrical transistors. In the entire circuit, the switching speed of the current switch is the most important factor determining the measurement accuracy of the shaking time. This requires that the transistors that make up the current switch have very good AC performance to adapt to the ultra-high-speed requirements of the circuit. The transistors in the circuit only work in the amplification state and the cut-off state to prevent the transistors from entering the saturation region. From the circuit structure, the time wasted by the collector junction capacitor releasing the stored charge when the transistor enters the cut-off state from the saturation state in the anti-saturation logic circuit is removed, and there is no additional parasitic capacitance caused by the clamping of the anti-saturation logic circuit. The constant current source provides a constant charging current to the charging capacitor through the high-speed current switch, and the system sets the output current of the constant current source to 10mA. The emitter-coupled high-speed switch is composed of two identical PNP transistors and two identical NPN transistors. When the control signal is low, the PNP transistor is turned on, the switch is turned on, and charging starts. When the control signal is high, the PNP is turned off, the switch is turned off, and charging stops.

[0048] The voltage comparison circuit includes two NPN transistors to form a voltage comparator. At the end of the set delay time, the delay signal passes through the voltage comparison module. When the voltage across the charging capacitor does not reach the set value, the output transistor is turned off, the input transistor is turned on, and the output is low potential. When the voltage across the capacitor is greater than the set value, the two transistors are reversed and output high potential, thereby realizing the voltage comparison function. The output signal of the voltage comparison module is flipped to control the driving circuit as the final output signal. In this way, we convert the random jitter time into a fixed time.

[0049] like Figure 6 As shown, the precision fine delay module includes two high-speed differential receivers, a D flip-flop, a constant current source circuit, a DAC, a charging capacitor, and a voltage comparison circuit. The DAC is used to set the precision delay time required by the synchronization system. The precision delay enable signal and the 100MHz ultra-stable time base are transmitted in the form of differential signals. The high-speed differential receiver is used to convert the differential signal into a single-ended signal for processing. The two signals are then re-clocked through the D flip-flop to cause the constant current source circuit to discharge the charging capacitor, which is then compared with the voltage comparison circuit and the trigger jitter voltage. When the discharge is equal to the two, the delay signal is output in the form of a differential signal.

[0050] The linear relationship between the voltage across the charging capacitor and time converts the amount of time that cannot be directly measured into a voltage that can be accurately measured. When the ramp control signal is at a low level, the high-speed switch is closed, and the high-speed operational amplifier clamps the voltage on the capacitor at a fixed level. When the rising edge of the ramp signal arrives, it passes through the high-speed operational amplifier and turns off the switch. At this time, the capacitor is discharged through the constant current source, and the voltage on the capacitor is cached by the operational amplifier.

[0051] like Figure 7 As shown, the output signal conditioning circuit includes a high-speed differential receiver, a logic gate circuit, a differential driver and an amplitude bias adjustment circuit. After the high-speed differential receiver receives the delay signal output by the precision delay module, it converts the differential signal into a single-ended signal. The switch signal controlled by the main control ZYNQ module acts on the logic gate circuit to condition the delay signal; and the signal is amplitude modulated and biased through the amplitude bias adjustment circuit.

[0052] The SPI data in the amplitude offset adjustment circuit is clocked into an 8-bit shift register to control the pulse output polarity and multiplexer; the serial data in the amplitude offset adjustment circuit is clocked into two octal 12-bit DACs to control the pulse output amplitude and offset. The DAC has been offset and scaled to a certain range, the op amp circuit has a certain gain between the non-inverting input and the emitter of the transistor, and the resistor network is set to offset and scale the output voltage. The ADC remotely measures the output voltage through the analog multiplexer. This can not only ensure the signal output, but also provide initial calibration of the output offset and amplitude, and realize the amplitude modulation of the delayed signal.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-precision delay synchronization system with phase jitter compensation function, characterized in that: It includes host computer, external trigger module, time reference module, main control ZYNQ module, frequency synthesis and trigger mode selection module, jitter compensation module, precision delay circuit and output signal conditioning circuit. The external trigger module is used to generate a high-frequency external reference signal; The time reference module is used to generate the system master 100 MHZ clock, and can selectively lock the master clock to an internal oscillator or an external clock source; The master control ZYNQ module is used to implement some medium-speed logic interfaces in the system, including SPI, counters for system coarse delay, and state machines; The frequency synthesis and trigger mode selection module is used to generate a trigger signal of arbitrary waveform, frequency and amplitude, and to guide the source trigger signal to the time-to-voltage converter and select the trigger mode; The jitter compensation module is used to collect the jitter error between the rising edge of the trigger signal and the rising edge of the system clock, and convert the uncertain time amount into a certain voltage amount; The precision fine delay circuit is used to eliminate trigger jitter together with the jitter compensation module and realize precision fine delay with a resolution of hundreds of picoseconds; The output signal conditioning circuit is used to condition the output pulses of each channel of the system, including amplitude, bias, and polarity; The 100MHZ generated by the time reference module is used as the clock reference of each module in the whole system, and the jitter compensation module is triggered to measure the phase difference between the rising edge of the trigger signal and the rising edge of the 100MHZ time base by charging the capacitor, and the coarse delay is started. After the coarse delay ends, the fine delay is turned on. The time of the coarse delay and the fine delay is set by the host computer; the fine delay circuit is realized by charging and discharging the capacitor, and the delay signal passes through the voltage comparison module. When it is discharged to the same level as the phase difference, the synchronization system generates an output delay pulse; the output pulse is finally converted into a pulse output with adjustable delay time, amplitude and polarity through the output conditioning circuit.

2. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The external trigger module includes a mode-locked laser and a high-speed photodetector. The mode-locked laser is used to generate periodic light pulses, and includes a pump source, an acousto-optic modulator, a pointing mirror and an oscillator connected in sequence, wherein the pump source is used to inject energy to excite oscillation and realize light amplification; the acousto-optic modulator is used to control the frequency and characteristics of light; and the pointing mirror is used to reflect the laser beam back to the oscillation cavity to form an optical cavity; The oscillator cavity generates laser pulses; through the control of the pump source and the acousto-optic modulator, the laser pulses are regulated and stably output; The femtosecond laser electric pulse sequence received by the high-speed photodetector can be used as a stable external frequency trigger signal.

3. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The time reference module includes an external input reference selection circuit, a 10MHz reference signal that can be selected internally or externally, a multiplexer, a phase-locked loop circuit, a clock distribution circuit, and a frequency division circuit. The phase-locked loop circuit includes a frequency detector, a phase detector, a loop filter, and a voltage-controlled oscillator. The frequency and phase of the internal oscillation signal of the loop are controlled by using an external input reference signal or an internal optional constant temperature crystal oscillator to realize automatic tracking of the output signal frequency to the input signal frequency. The frequency division circuit includes a single-channel high-speed receiver, a frequency divider, and a D flip-flop.

4. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The master control ZYNQ module includes power supply, mode and BANK, the power supply includes all power supply lines; the mode includes all pins related to the ZYNQ configuration, and the logic module corresponds to the architecture block in ZYNQ; the initial value and coarse delay range of the counter are set, and the bit width of the counter is calculated according to the delay requirement. After each system clock, the value of the counter is accumulated. When the count reaches a preset value, the counting process ends, and the system coarse delay is realized.

5. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The frequency synthesis and trigger mode selection module includes a high-speed DDS, a Chebyshev filter, a D trigger, a high-speed receiver and a multiplexer. The working process is as follows: the buffered SPI interface of the master control ZYNQ is used to read and write register data to the high-speed DDS, and the high-speed DDS outputs to the internal digital-to-analog converter in a differential current mode, and is filtered by a Chebyshev low-pass filter to reduce the harmonic content, so that the high-speed DDS generates a drive signal with controllable frequency, phase and amplitude; finally, the trigger mode of the synchronization system is selected through the multiplexer.

6. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The jitter compensation module includes a DAC, a trigger enable, a trigger establishment circuit, a cascaded D flip-flop, a constant current source circuit, an emitter-coupled high-speed switch circuit and a charging capacitor; the master control ZYNQ module allows the synchronization system to receive a trigger signal through a logic gate. When the trigger signal is captured, the output level of the cascaded D flip-flop jumps, causing the emitter-coupled high-speed switch to be turned off, thereby controlling the charging time of the constant current source for the charging capacitor, realizing the acquisition of the phase difference between the trigger source and the system 100MHz clock, completing the trigger jitter measurement, and the measured phase difference voltage is output after passing through the voltage comparison circuit to realize jitter compensation.

7. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The precision fine delay module includes two high-speed differential receivers, a D flip-flop, a constant current source circuit, a DAC, a charging capacitor, and a voltage comparison circuit. The DAC is used to set the precision delay time required by the synchronization system. The precision delay enable signal and the 100MHz ultra-stable time base are transmitted in the form of differential signals. The high-speed differential receiver is used to convert the differential signal into a single-ended signal for processing. The two signals are then re-clocked through the D flip-flop to cause the constant current source circuit to discharge the charging capacitor, which is then compared with the voltage comparison circuit and the trigger jitter voltage. When the discharge is equal to the two, the delay signal is output in the form of a differential signal.

8. The high-precision delay synchronization system with phase jitter compensation function according to claim 1, characterized in that: The output signal conditioning circuit includes a high-speed differential receiver, a logic gate circuit, a differential driver and an amplitude bias adjustment circuit. After receiving the delay signal output by the precision delay module, the high-speed differential receiver converts the differential signal into a single-ended signal. The switch signal controlled by the main control ZYNQ module acts on the logic gate circuit to condition the delay signal; and the amplitude bias adjustment circuit is used to modulate the signal.

9. A high-precision delay synchronization system with phase jitter compensation function according to any one of claims 1 to 8, characterized in that: If external triggering is selected, the mode-locked laser in the external triggering module generates a high-stability mode-locked laser pulse, which is converted into a femtosecond laser electrical pulse sequence by the high-speed photodetector in the external triggering module as a stable external frequency triggering signal; if internal triggering is selected, the digital frequency synthesizer generates a drive signal with controllable frequency, phase and amplitude as the system triggering signal, and the frequency, phase and amplitude are controlled by the host computer.

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