Input interface circuit suitable for high-voltage chip
By designing an input interface circuit including NMOS tube, PMOS tube, hysteresis switching module and voltage shaping module, the problem that traditional circuits cannot achieve level conversion and noise cancellation in high-voltage chips is solved, and high-efficiency level conversion is achieved and low power design.
Patent Information
- Application Number
- CN202411455514.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-07
AI Technical Summary
Traditional input interface circuits cannot achieve level conversion in high-voltage chip applications, resulting in high and low input levels failure and cannot effectively eliminate the noise of the input signal, affecting the normal operation of the circuit.
An input interface circuit including a first NMOS tube, a first PMOS tube, a hysteresis switching module, a voltage shaping module, a resistor and a PMOS tube is designed, and the input signal is transferred through the third resistor and the fourth resistor and voltage shaping module. The logic high and low levels are converted to high and low levels inside the high voltage chip and eliminates noise through the hysteresis switching module.
The level conversion from low voltage to high voltage is realized, ensuring the effectiveness of the high-level input signal, and a low-power design is realized by reducing current, while eliminating the noise of the input signal, ensuring the normal operation of the circuit.
Smart Images
Figure CN119402000A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of input interface circuits, and in particular to an input interface circuit suitable for a high-voltage chip. Background Art
[0002] In integrated circuit systems, input and output interface circuits are bridges between information processing systems or chips, and are used for data and information exchange and control. Therefore, the design of input and output buffer circuits for pins is particularly important and is an indispensable part of chip integrity design. Usually, the input digital signal level is not consistent with the internal level of the chip, especially for high-voltage working chips. If the level conversion is not performed, the input high level or low voltage will fail. At this time, a boost or buck circuit is required for processing. At the same time, the input interface circuit should also have the ability to filter out noise. The noise in the circuit system usually parasitizes on the signal level and may cause misjudgment of the input interface circuit, thereby affecting the normal operation of the circuit.
[0003] The traditional input interface circuit is Figure 1 The Schmitt trigger structure shown in the figure uses the hysteresis effect to eliminate the influence of input noise. As long as the input noise amplitude does not exceed the hysteresis window width, the output will not flip incorrectly. However, when the input digital signal level is inconsistent with the internal working level of the chip, the structure does not have the level conversion function, which will cause the input high and low levels to fail. Especially in high-voltage chip applications, the chip's power supply voltage usually exceeds the withstand voltage of ordinary low-voltage transistors. Figure 1 When the power supply voltage of the input interface circuit shown is high, the transistors NM1, NM2, PM1, and PM2 will be broken down and damaged, resulting in more serious safety problems. Summary of the invention
[0004] In view of the problems existing in the prior art, the present invention provides an input interface circuit suitable for a high-voltage chip, which has the characteristics of simple structure and low power consumption, can not only ensure the effectiveness of high-level input signals, but also realize level conversion and eliminate noise of input signals.
[0005] To achieve the above technical objectives, the present invention adopts the following technical solutions: an input interface circuit suitable for a high-voltage chip, comprising: a first NMOS tube NM1, a first PMOS tube PM1, a hysteresis switching module, a voltage shaping module, a third resistor R3, a third PMOS tube PM3 and a fourth resistor R4; the gate of the first NMOS tube NM1 is used as a signal input terminal IN to access the input signal, the source of the first NMOS tube NM1 is connected to the ground potential GND of the high-voltage chip, the drain of the first NMOS tube NM1 is connected to the drain of the first PMOS tube PM1, and the source of the first PMOS tube PM1 is respectively connected to the hysteresis switching terminal IN. The output of the voltage shaping module is fed back to the input end of the hysteresis switching module, and the output end of the voltage shaping module is used as the output end OUT of the input interface circuit; the source of the third PMOS tube PM3, the hysteresis switching module and the other end of the third resistor R3 are all connected to the power supply potential VBB of the high-voltage chip, the drain of the third PMOS tube PM3 is respectively connected to the input end of the voltage shaping module and one end of the fourth resistor R4, and the other end of the fourth resistor R4 and the gate of the first PMOS tube PM1 are both connected to the relative ground potential HVSS inside the high-voltage chip.
[0006] Furthermore, the hysteresis switching module is used to control the lower flip threshold VIL of the input interface circuit, and forms a hysteresis window with the upper flip threshold VIH.
[0007] Furthermore, the hysteresis switching module includes: a second PMOS tube PM2 and a second resistor R2, the drain of the second PMOS tube PM2, the source of the first PMOS tube PM1, the gate of the third PMOS tube PM3 and the other end of the third resistor R3 are connected to form a high-voltage node VG; the source of the second PMOS tube PM2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the power supply potential VBB of the high-voltage chip, and the gate of the second PMOS tube PM2 is connected to the output end of the voltage shaping module.
[0008] Furthermore, the second resistor R2 and the third resistor R3 are cross-matched.
[0009] Further, the voltage shaping module includes: a Schmitt trigger SMIT and an inverter INV, the input end of the Schmitt trigger SMIT is respectively connected to the drain of the third PMOS tube PM3 and one end of the fourth resistor R4, the output end of the Schmitt trigger SMIT is connected to the input end of the inverter INV, and the output end of the inverter INV serves as a signal output end OUT and is connected to the gate of the second PMOS tube PM2.
[0010] Furthermore, the working power supply voltages of the Schmitt trigger SMIT and the inverter INV are both the power supply potential VBB of the high-voltage chip, the working ground voltages of the Schmitt trigger SMIT and the inverter INV are both the relative ground potential HVSS inside the high-voltage chip, and the voltage difference between the power supply potential VBB of the high-voltage chip and the relative ground potential HVSS inside the high-voltage chip is 2V-6V.
[0011] Furthermore, it also includes a current limiting protection module, which is used to limit the current of the input signal of the signal input terminal IN and reduce the gate voltage of the first NMOS tube NM1.
[0012] Furthermore, the current limiting protection module is composed of a first resistor R1 and a clamping diode D1, one end of the first resistor R1 and the cathode of the clamping diode D1 are both connected to the gate of the first NMOS tube NM1, and the other end of the first resistor R1 and the anode of the clamping diode D1 are both connected to the ground potential GND of the high-voltage chip.
[0013] Furthermore, both the first NMOS transistor NM1 and the first PMOS transistor PM1 are high-voltage transistors.
[0014] Compared with the prior art, the present invention has the following beneficial effects: the present invention is applicable to the input interface circuit of the high-voltage chip, through the third resistor R3, the fourth resistor R4 and the voltage shaping module, the logic high and low levels of the input signal are converted into the high level VBB and the low level HVSS inside the high-voltage chip, thereby realizing the level conversion from low voltage to high voltage; at the same time, the static power consumption of the present invention only exists in the path from the power supply potential VBB of the high-voltage chip through the third resistor R3, the first PMOS tube PM1, the first NMOS tube NM1 and the path from the third PMOS tube PM3 and the fourth resistor R4 to the relative ground potential HVSS inside the high-voltage chip, therefore, only by increasing the resistance value of the third resistor R3 and the fourth resistor R4, the current can be reduced to realize the low power consumption design. In summary, the present invention has the characteristics of simple structure and low power consumption, which can not only ensure the effectiveness of the high-level input signal, but also realize the level conversion, and can also eliminate the noise of the input signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 This is a schematic diagram of a traditional input interface circuit;
[0016] Figure 2 The present invention is a schematic diagram of an input interface circuit suitable for a high-voltage chip. DETAILED DESCRIPTION
[0017] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.
[0018] like Figure 2The present invention is a schematic diagram of an input interface circuit suitable for a high-voltage chip, wherein the input interface circuit comprises: a first NMOS tube NM1, a first PMOS tube PM1, a hysteresis switching module, a voltage shaping module, a third resistor R3, a third PMOS tube PM3 and a fourth resistor R4; the gate of the first NMOS tube NM1 is used as a signal input terminal IN to access the input signal, the source of the first NMOS tube NM1 is connected to the ground potential GND of the high-voltage chip, the drain of the first NMOS tube NM1 is connected to the drain of the first PMOS tube PM1, the source of the first PMOS tube PM1 is respectively connected to the hysteresis switching module, one end of the third resistor R3 and the gate of the third PMOS tube PM3, and the output of the voltage shaping module is connected to the ground potential GND of the high-voltage chip. Feedback to the input end of the hysteresis switching module, and the output end of the voltage shaping module is used as the output end OUT of the input interface circuit; the source of the third PMOS tube PM3, the hysteresis switching module and the other end of the third resistor R3 are all connected to the power supply potential VBB of the high-voltage chip, the drain of the third PMOS tube PM3 is respectively connected to the input end of the voltage shaping module and one end of the fourth resistor R4, the other end of the fourth resistor R4 and the gate of the first PMOS tube PM1 are both connected to the relative ground potential HVSS inside the high-voltage chip, the relative ground potential HVSS inside the high-voltage chip is a fixed voltage lower than the power supply potential VBB of the high-voltage chip, and the internal circuit of the high-voltage chip works as a whole in the voltage domain range from HVSS to VBB. Since the power supply point VBB of the high-voltage chip is usually high voltage, which is greater than the withstand voltage of ordinary low-voltage tubes, therefore, the first NMOS tube NM1 and the first PMOS tube PM1 both need to use high-voltage tubes with high voltage resistance for pressure resistance. The present invention converts the logic high and low levels of the input signal into the high level VBB and the low level HVSS inside the high-voltage chip through the third resistor R3, the fourth resistor R4 and the voltage shaping module, which can overcome the disadvantage that the traditional input interface circuit cannot realize level conversion, convert the voltage signal into a high-voltage signal, and is suitable for the high-voltage chip; at the same time, the static power consumption of the present invention only exists in the path from the power supply potential VBB of the high-voltage chip through the third resistor R3, the first PMOS transistor PM1, the first NMOS transistor NM1 and the path through the third PMOS transistor PM3 and the fourth resistor R4 to the relative ground potential HVSS inside the high-voltage chip, therefore, the current can be reduced by increasing the resistance values of the third resistor R3 and the fourth resistor R4, thereby realizing a low-power design.
[0019] The hysteresis switching module in the present invention is used to control the lower flip threshold VIL of the input interface circuit, and forms a hysteresis window with the upper flip threshold VIH, so as to eliminate the influence of input noise by using the hysteresis effect. The hysteresis switching module includes: a second PMOS tube PM2 and a second resistor R2, the drain of the second PMOS tube PM2, the source of the first PMOS tube PM1, the gate of the third PMOS tube PM3 and the other end of the third resistor R3 are connected to form a high-voltage node VG; the source of the second PMOS tube PM2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the power supply potential VBB of the high-voltage chip, and the gate of the second PMOS tube PM2 is connected to the output end of the voltage shaping module.
[0020] In one technical solution of the present invention, the resistance value and relative size of the second resistor R2 and the third resistor R3 play a decisive role in the upper flip threshold VIH and the lower flip threshold VIL of the input interface circuit. Therefore, the second resistor R2 and the third resistor R3 should be designed to match and cross-match on the layout to avoid resistance mismatch.
[0021] The voltage shaping module in the present invention includes: a Schmitt trigger SMIT and an inverter INV, the input end of the Schmitt trigger SMIT, the drain of the third PMOS tube PM3, and one end of the fourth resistor R4 are connected to form a VD node; the output end of the Schmitt trigger SMIT is connected to the input end of the inverter INV, and the output end of the inverter INV is used as a signal output end OUT and is connected to the gate of the second PMOS tube PM2. The working power supply voltage of the Schmitt trigger SMIT and the inverter INV are both the power supply potential VBB of the high-voltage chip, and the working ground voltage of the Schmitt trigger SMIT and the inverter INV are both the relative ground potential HVSS inside the high-voltage chip. The voltage difference between the power supply potential VBB of the high-voltage chip and the relative ground potential HVSS inside the high-voltage chip is 2V-6V. If the voltage difference between the power supply potential VBB of the high-voltage chip and the relative ground potential HVSS inside the high-voltage chip is too large, the Schmitt trigger SMIT and the inverter INV will have a withstand voltage problem and a breakdown risk; if it is too small, the Schmitt trigger SMIT and the inverter INV will not work properly.
[0022] In a technical solution of the present invention, it also includes: a current limiting protection module, which is used to limit the current of the input signal of the signal input terminal IN and reduce the gate voltage of the first NMOS tube NM1. The current limiting protection module is composed of a first resistor R1 and a clamping diode D1, one end of the first resistor R1 and the cathode of the clamping diode D1 are both connected to the gate of the first NMOS tube NM1, and the other end of the first resistor R1 and the anode of the clamping diode D1 are both connected to the ground potential of the high-voltage chip.
[0023] The working process of the input interface circuit of the present invention applicable to the high voltage chip is as follows:
[0024] When the input signal of the signal input terminal IN increases from 0 and before reaching the conduction threshold of the first NMOS tube NM1, the first NMOS tube NM1 is not turned on, and the voltage of the high-voltage node VG is pulled up to the power supply potential VBB of the high-voltage chip by the third resistor R3. At this time, the third PMOS tube PM3 is turned off, and the voltage of the VD node is pulled down to the relative ground potential HVSS inside the high-voltage chip by the fourth resistor R4. The Schmitt trigger SMIT outputs a high level, and the signal output terminal OUT outputs a low level after the inverter INV. Therefore, the input interface circuit determines that the input signal is a low level, the second PMOS tube PM2 is turned on, and the second resistor R2 and the third resistor R3 are equivalent to being connected in parallel;
[0025] When the input signal of the signal input terminal IN increases to the conduction threshold of the first NMOS transistor NM1 and gradually increases, according to the NMOS transistor linear region IV formula: Wherein, k is the process parameter of the first NMOS tube NM1, W and L are the width and length of the first NMOS tube NM1 respectively, Vgs is the gate-source voltage of the first NMOS tube NM1, Vth is the threshold voltage of the first NMOS tube NM1, and Vds is the drain-source voltage of the first NMOS tube NM1. It can be seen that the current of the NMOS tube increases with the increase of Vgs. When the current I1 generated by the first NMOS tube NM1 and the product of the second resistor R2 in parallel with the third resistor R3 generate a voltage V1=I1×(R2||R3) that meets the turn-on condition of the third PMOS tube PM3, and the product of the current generated by the turn-on of the third PMOS tube PM3 and the fourth resistor R4 meets the turn-on condition of the Schmitt trigger SMIT, the Schmitt trigger SMIT outputs a low level, and outputs a high level through the inverter INV. Therefore, the input interface circuit determines that the input signal is a high level and turns off the second PMOS tube PM2. At this time, the input signal voltage of the signal input terminal IN is defined as the up-turn threshold VIH of the input interface circuit;
[0026] When the input signal of the signal input terminal IN gradually decreases from a high voltage, due to the turning off of the second PMOS tube PM2, when the first NMOS tube NM1 generates a current I2, and the product of the current and the third resistor R3 generates a voltage V2=I2*R3 that is lower than the conduction threshold of the third PMOS tube PM3, the third PMOS tube PM3 is turned off, the VD node voltage is pulled down to the low level HVSS by the fourth resistor R4, the Schmitt trigger SMIT outputs a high level, and the inverter INV outputs a low level, so the input interface circuit determines that the input signal is a low level, and the second PMOS tube PM2 is turned on. At this time, the input signal voltage of the signal input terminal IN is defined as the lower flip threshold VIL of the input interface circuit.
[0027] Through the above process, it can be known that when the input signal of the signal input terminal IN changes from low to high, the voltage of the high-voltage node VG must be equal to V1 to satisfy the turn-on condition of the third PMOS tube PM3; when the input signal of the signal input terminal IN changes from high to low, the voltage of the high-voltage node VG must be equal to V2 to satisfy the turn-off condition of the third PMOS tube PM3. Because the turn-on and turn-off thresholds of the third PMOS tube PM3 are equal, V1=V2. Because the resistance of the second resistor R2 and the third resistor R3 in parallel is less than the resistance of the third resistor R3, I1>I2. Therefore, VIH>VIL. The difference between VIH and VIL is the hysteresis window width of the input interface circuit. At the same time, since the gate voltage of the first PMOS tube PM1 is the relative ground potential HVSS inside the high-voltage chip, when the voltage of the high-voltage node VG is too low, the first PMOS tube PM1 will be turned off because the potential of the high-voltage node VG is pulled up to the VBB potential by the third resistor R3, so that the potential of the high-voltage node VG will not be too low, thereby ensuring the Vds of the second PMOS tube PM2 and the Vgs of the third PMOS tube PM3 will not be broken down.
[0028] Therefore, the present invention can safely convert the high and low levels of the input signal into the high level VBB and low level HVSS required by the high voltage chip under a relatively simple circuit structure, and at the same time, the low power consumption requirement can be achieved by setting the resistance values of the second resistor R2, the third resistor R3 and the fourth resistor R4 to larger reasonable values.
[0029] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.
Claims
1. An input interface circuit suitable for a high voltage chip, characterized in that: include: a first NMOS transistor NM1, a first PMOS transistor PM1, a hysteresis switching module, a voltage shaping module, a third resistor R3, a third PMOS transistor PM3 and a fourth resistor R4; the gate of the first NMOS transistor NM1 is used as a signal input terminal IN to access the input signal, the source of the first NMOS transistor NM1 is connected to the ground potential GND of the high-voltage chip, the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1, the source of the first PMOS transistor PM1 is respectively connected to the hysteresis switching module, one end of the third resistor R3, the third PMOS transistor P The output of the voltage shaping module is fed back to the input end of the hysteresis switching module, and the output end of the voltage shaping module is used as the output end OUT of the input interface circuit; the source of the third PMOS tube PM3, the hysteresis switching module and the other end of the third resistor R3 are all connected to the power supply potential VBB of the high-voltage chip, the drain of the third PMOS tube PM3 is respectively connected to the input end of the voltage shaping module and one end of the fourth resistor R4, and the other end of the fourth resistor R4 and the gate of the first PMOS tube PM1 are both connected to the relative ground potential HVSS inside the high-voltage chip.
2. The input interface circuit suitable for a high voltage chip according to claim 1, characterized in that: The hysteresis switching module is used to control the lower flip threshold VIL of the input interface circuit, and forms a hysteresis window with the upper flip threshold VIH.
3. The input interface circuit suitable for a high voltage chip according to claim 2, characterized in that: The hysteresis switching module includes: a second PMOS tube PM2 and a second resistor R2, the drain of the second PMOS tube PM2, the source of the first PMOS tube PM1, the gate of the third PMOS tube PM3 and the other end of the third resistor R3 are connected to form a high-voltage node VG; the source of the second PMOS tube PM2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the power supply potential VBB of the high-voltage chip, and the gate of the second PMOS tube PM2 is connected to the output end of the voltage shaping module.
4. The input interface circuit suitable for a high voltage chip according to claim 3, characterized in that: The second resistor R2 and the third resistor R3 are cross-matched.
5. The input interface circuit suitable for a high voltage chip according to claim 3, characterized in that: The voltage shaping module includes: a Schmitt trigger SMIT and an inverter INV, wherein the input end of the Schmitt trigger SMIT is respectively connected to the drain of the third PMOS tube PM3 and one end of the fourth resistor R4, the output end of the Schmitt trigger SMIT is connected to the input end of the inverter INV, and the output end of the inverter INV is used as a signal output end OUT and is connected to the gate of the second PMOS tube PM2.
6. The input interface circuit suitable for a high voltage chip according to claim 5, characterized in that: The working power supply voltage of the Schmitt trigger SMIT and the inverter INV are both the power supply potential VBB of the high-voltage chip, the working ground voltage of the Schmitt trigger SMIT and the inverter INV are both the relative ground potential HVSS inside the high-voltage chip, and the voltage difference between the power supply potential VBB of the high-voltage chip and the relative ground potential HVSS inside the high-voltage chip is 2V-6V.
7. The input interface circuit suitable for a high voltage chip according to claim 1, characterized in that: It also includes a current limiting protection module, which is used to limit the current of the input signal of the signal input terminal IN and reduce the gate voltage of the first NMOS tube NM1.
8. The input interface circuit suitable for a high voltage chip according to claim 7, characterized in that: The current limiting protection module is composed of a first resistor R1 and a clamping diode D1, one end of the first resistor R1 and the cathode of the clamping diode D1 are both connected to the gate of the first NMOS tube NM1, and the other end of the first resistor R1 and the anode of the clamping diode D1 are both connected to the ground potential GND of the high-voltage chip.
9. The input interface circuit suitable for a high voltage chip according to claim 1, characterized in that: The first NMOS transistor NM1 and the first PMOS transistor PM1 are both high-voltage transistors.