Packaging structure of stacked capacitor and preparation method

Abstract

The invention discloses a packaging structure and a preparation method of a stacked capacitor, and the packaging structure comprises a semiconductor substrate, and a metal film layer is deposited on the first surface of the semiconductor substrate to form a bottom metal layer; the columnar array comprises a bottom metal layer and a plurality of stand columns which are vertically borne on the bottom metal layer and communicated with the bottom metal layer, and a plurality of dielectric layers and metal layers which are arranged at intervals are deposited on the surface of the columnar array; the step part comprises a plurality of steps parallel to the upper surface of the bottom metal layer, and the upper surface and the lower surface of each step are in one-to-one correspondence with the metal layer and the dielectric layer respectively; the connecting part comprises a plurality of through electrodes which are vertically borne on the upper surface of the step and communicated with the step; the multiple through holes are communicated to serve as the positive electrode and the negative electrode of the stacked capacitor; and the filling dielectric layer comprises a first capacitor dielectric layer filled between the stand columns and a second capacitor dielectric layer filled between the through electrodes. The problems of difficulty in groove filling, complexity in etching control and high cost in a traditional deep groove capacitor are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a packaging structure and a preparation method of a stacked capacitor. Background Art

[0002] As the bandwidth of logic chips in AI accelerators, high-performance computing (HPC) and servers increases rapidly, the power consumption of ASIC chips has also increased significantly. The power transmission design in the system package (including power noise margin) has become increasingly critical. In order to ensure that the power transmission network (PDN) of the system package can work effectively, it is crucial to minimize high-frequency switching noise and design a low-impedance power transmission network.

[0003] The most common way to improve the power integrity PI performance is to optimize the layout design of decoupling capacitors. In particular, silicon capacitor structures with miniaturization, low equivalent series inductance ESL and high capacitance value have been widely studied in recent years. In order to reduce power noise in the frequency band of hundreds of MHz, on-chip capacitor solutions such as MOS capacitors, metal-insulator-metal MIM capacitors, deep trench capacitors DTC, stacked capacitors ISC, embedded capacitors and package bottom capacitors LSC have been widely used in a single package and are considered to be effective solutions. Generally, multi-layer MIM capacitors use high dielectric constant materials, and their capacitance density is relatively low despite the large capacitance value. In the past few decades, with the continuous advancement of deep silicon etching technology, the research and development of deep trench capacitors has also made important breakthroughs. This type of capacitor can provide higher capacitance density in a limited chip area. However, with the continuous improvement of capacitance density, higher aspect ratios are required in design and process to expand the surface area, which has brought about a continuous increase in cost and a sharp decline in reliability.

[0004] Therefore, it is necessary to provide a more efficient and reliable silicon capacitor to overcome the shortcomings of the above technology. Summary of the invention

[0005] In order to overcome the shortcomings of the above technologies, the present invention provides a packaging structure and preparation method of a stacked capacitor. A multi-layer stacked capacitor is formed by etching to form a columnar array, and a capacitor parallel structure is utilized to solve the problems of difficult trench filling, complex etching control and extremely high cost in traditional deep trench capacitors. The present invention has broad application prospects in advanced packaging and high-performance computing scenarios.

[0006] The technical solution adopted by the present invention to overcome its technical problems is as follows: the first aspect of the present invention is to propose a packaging structure of a stacked capacitor, which at least includes a semiconductor substrate, a metal film layer is deposited on the first surface of the semiconductor substrate to form a bottom metal layer; a columnar array, which at least includes a bottom metal layer and a plurality of columns vertically supported on and connected to the bottom metal layer, and a plurality of dielectric layers and metal layers are deposited on the surface of the columnar array; a step portion, which includes a plurality of steps arranged in parallel on the upper surface of the bottom metal layer, the upper surface of each step corresponds to the metal layer deposited on the surface of the column, and the lower surface corresponds to the dielectric layer deposited on the surface of the column; a connecting portion, which includes a plurality of through electrodes, which are vertically supported on the upper surface of the step and are respectively connected to the upper surface of the corresponding step; the plurality of through electrodes are respectively connected as the positive and negative electrodes of the stacked capacitor to realize capacitor parallel connection; a filling dielectric layer, which includes at least a first capacitor dielectric layer filled between the columns and a second capacitor dielectric layer filled between the through electrodes.

[0007] By controlling the etching parameters, the side wall angle of the columnar array can be adjusted, which is beneficial to the subsequent stacking of capacitor films.

[0008] Furthermore, the top surface of the column is circular or elliptical.

[0009] Furthermore, the width of the step is determined based on the size of the through electrode.

[0010] Furthermore, the first capacitor dielectric layer, the second capacitor dielectric layer and the dielectric layer are all made of at least one or a combination of silicon oxide, silicon nitride, hafnium oxide, yttrium aluminate, barium titanate and tantalum oxide.

[0011] Furthermore, the bottom metal layer and the metal layer are a combination of one or more materials selected from the group consisting of polysilicon, tungsten, copper, titanium, and ruthenium.

[0012] The second aspect of the present invention also proposes a method for preparing a stacked capacitor with a packaging structure for preparing the above-mentioned stacked capacitor, comprising depositing a metal film on the first surface of a semiconductor substrate to form a bottom metal layer, performing photolithography and etching to form a plurality of columns, wherein the columns are vertically supported on the bottom metal layer and connected to the bottom metal layer, and the columns and the bottom metal layer constitute a columnar array; depositing a dielectric layer and a metal layer in sequence on the surface of the columnar array; filling a first capacitor dielectric layer to obtain a first capacitor structure; performing photolithography and etching on the first capacitor structure to obtain a plurality of steps corresponding to the bottom metal layer and the deposited metal layer, respectively; filling a second capacitor dielectric layer; performing photolithography and etching based on the second capacitor dielectric layer to obtain a plurality of through electrodes corresponding to and connected to the bottom metal layer or the metal layer, respectively; and metal interconnecting the through electrodes to obtain a stacked capacitor with a parallel structure.

[0013] The columnar array is formed by etching, and the exposure area of ​​the process is larger, which improves the exposure efficiency. Compared with the traditional deep trench capacitor, the process window of photolithography and etching is increased, so that in actual mass production, the process is more stable and the yield is improved. The columnar array is formed by etching and combined with multi-layer stacked capacitors to form capacitors in parallel, which is simpler in overall structure and more flexible in application scenarios.

[0014] Furthermore, the depositing of the dielectric layer, the depositing of the metal layer, the filling of the first capacitor dielectric layer, and the filling of the second capacitor dielectric layer adopt a filling method with a high step coverage.

[0015] Furthermore, the filled second capacitor dielectric layer and the second dielectric layer are surface planarized by at least one or more of chemical mechanical polishing, dry etching, and wet etching.

[0016] Furthermore, the photolithography and etching of the second capacitor dielectric layer to obtain a plurality of through electrodes connected to the bottom metal layer or metal layer specifically includes etching on the step based on the selection ratio of the second capacitor dielectric layer and the metal layer to obtain the through electrodes.

[0017] Furthermore, the photoresist trimming is performed by at least in-situ trimming using dry plasma etching.

[0018] The beneficial effects of the present invention are:

[0019] 1. Etching is used to form a columnar array, the exposure area of ​​the process is larger, the exposure efficiency is improved, and the process window of lithography and etching is increased compared to traditional deep trench capacitors, so that in actual mass production, the process is more stable and the yield is improved.

[0020] 2. The sidewall angle of the columnar array is flexible and controllable, which is conducive to the subsequent stacking of capacitor films, such as MIMIM stacking, and the formation of capacitor structures with better quality;

[0021] 3. Etching to form a columnar array and combining it with multi-layer stacked capacitors to form capacitors in parallel has a simpler overall structure and more flexible application scenarios. It has broad application prospects in various decoupling circuits and advanced packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The figure is a schematic flow chart of a method for preparing a stacked capacitor according to an embodiment of the present invention.

[0023] Figure 2 Schematic diagram of a columnar array structure according to an embodiment of the present invention

[0024] Figure 3 This is a schematic diagram of the structure after the metal and dielectric layers are deposited according to an embodiment of the present invention;

[0025] Figure 4 A schematic diagram for implementing the first step etching;

[0026] Figure 5 A schematic diagram of implementing the second step etching;

[0027] Figure 6 A schematic diagram for implementing the third step etching;

[0028] Figure 7 This is a schematic diagram of the dielectric layer being filled after the step etching is completed;

[0029] Figure 8 A schematic diagram of the structure after the through electrode is formed;

[0030] Fig. 9 A top view of a stacked capacitor packaging structure;

[0031] In the figure, 100 is a semiconductor substrate; 101 is a columnar array; 102 is a first dielectric layer; 103 is a first metal layer; 104 is a second dielectric layer; 105 is a second metal layer; 106 is a first capacitor dielectric layer; 107 is a second capacitor dielectric layer; and 108 is a through electrode. DETAILED DESCRIPTION

[0032] In order to facilitate those skilled in the art to better understand the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The following is only exemplary and does not limit the protection scope of the present invention.

[0033] like Figure 1 As shown, a schematic flow chart of a method for preparing a stacked capacitor according to the present embodiment includes the following steps, and the method for preparing the stacked capacitor according to the present embodiment is described in detail as follows in conjunction with the accompanying drawings.

[0034] S1, depositing a metal film on a first surface of a semiconductor substrate to form a bottom metal layer.

[0035] like Figure 2 As shown, a semiconductor substrate 100 is provided, and a metal film is deposited on a first surface of the semiconductor substrate, ie, an upper surface in the figure, to form a bottom metal layer.

[0036] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0037] S2, performing photolithography and etching to form a plurality of pillars, wherein the pillars are vertically supported on the bottom metal layer and connected to the bottom metal layer, and the pillars and the bottom metal layer form a columnar array.

[0038] like Figure 2 As shown, the pillars are formed by photolithography and etching. The pillar array 101 is used to make a stacked capacitor structure. The pillar array 101 is composed of a plurality of pillars and a bottom metal layer. The bottom metal layer and the pillars can be made of the same or different metals.

[0039] In particular, the material of the pillar can be a combination of one or more metals such as tungsten (W), tantalum (Ta), gold (Au), etc.

[0040] In some embodiments of the present application, the height of the pillar is deeper than the design depth of the stacked capacitor, thereby expanding the surface area and improving the capacitance density.

[0041] In particular, the top surface of the pillar may be cylindrical, elliptical or other possible shapes.

[0042] It should be noted that the top surface shape affects the density of the column arrangement, which in turn affects the density of the capacitor.

[0043] In particular, the spacing and arrangement positions of the columns can be adjusted according to actual process capabilities and requirements.

[0044] It should be noted that etching needs to ensure that a thin layer of metal is left at the bottom for subsequent routing. And by controlling the etching parameters, the side wall angle of the column can be adjusted, for example, the column is wide at the bottom and narrow at the top, and its side wall is at a certain angle to the metal film layer.

[0045] S3, depositing a dielectric layer and a metal layer in sequence and at intervals on the surface of the columnar array.

[0046] Multiple layers of dielectric and metal are deposited on the surface of the columnar array to form a capacitor structure, such as Figure 3 As shown in the example, on the surface of the columnar array 101, a first dielectric layer 102, a first metal layer 103, a second dielectric layer 104 and a second metal layer 105 are sequentially deposited.

[0047] In some embodiments of the present application, commonly used materials for the first dielectric layer 102 and the second dielectric layer 104 include silicon dioxide (SiO2), silicon nitride (SiNx), hafnium oxide (HfO2), yttrium aluminate (Y2O3), barium titanate (BaTiO3), tantalum oxide (Ta2O5), etc., or a combination of one or more materials.

[0048] Common materials for the first metal layer 103 and the second metal layer 105 include polysilicon (Poly-Si), tungsten (W), copper (Cu), titanium (Ti), ruthenium (Ru), etc., or a combination of one or more materials.

[0049] The method of depositing the first dielectric layer 102 , the first metal layer 103 , the second dielectric layer 104 and the second metal layer 105 includes a filling method with high step coverage, such as an atomic layer deposition process.

[0050] It should be noted that the number of deposited metal layers and dielectric layers can be appropriately adjusted according to actual process capabilities and requirements. This embodiment is merely an example of depositing two metal layers and two dielectric layers respectively.

[0051] S4, filling the first capacitor dielectric layer to the gaps in the columnar array to obtain a first capacitor structure.

[0052] like Figure 3 As shown, a first capacitor dielectric layer 106 is deposited to fill the gaps in the columnar array, and chemical mechanical polishing is performed to make the surface flat but not to expose the top of the capacitor structure.

[0053] In some embodiments of the present application, commonly used materials for the first capacitor dielectric layer 106 include silicon oxide (SiO 2 ), silicon nitride (SiNx), etc., or a combination of one or more materials.

[0054] In some embodiments of the present application, the method for forming the first capacitor dielectric layer 106 includes a filling method with high step coverage, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like.

[0055] In particular, chemical mechanical polishing is used to planarize the surface, and other methods may also be used to achieve the same effect, such as dry etching, wet etching, etc.

[0056] In particular, the planarization process should not expose the top of the capacitor structure, and the thickness of the remaining first capacitor dielectric layer 106 can be determined according to design and process requirements.

[0057] S5, performing photolithography and etching on the first capacitor structure to obtain a plurality of steps corresponding to the bottom metal layer and the deposited metal layer respectively.

[0058] S51, photolithography is performed on the first capacitor structure and etching is performed based on the metal film layer to obtain a first step.

[0059] like Figure 4 As shown, in Figure 3 Photolithography is performed on the basis of the formed first capacitor structure to form a first step, and etching is performed and stopped at the surface of the bottom metal layer to form a first step.

[0060] In one embodiment of the present invention, the width of the first step depends on the requirements of subsequent processes, particularly the size of the through electrode.

[0061] It should be noted that the etching needs to rely on a better selectivity to stop at the bottom surface of the metal 101, with at least no residue of the first metal layer 103 and the second metal layer 105, so that the bottom metal layer and the subsequent process form a better electrical connection without short-circuiting with the first metal layer 103 and the second metal layer 105.

[0062] S52, trimming the photoresist to form a second step, then etching and stopping on the surface of the first metal layer, and trimming the photoresist to form a third step, then etching and stopping on the surface of the second metal layer.

[0063] like Figure 5 As shown, in the process of forming the second step, etching needs to rely on a better selectivity to stop at the surface of the 103 metal, at least without leaving the second metal layer 105, so that the 103 metal layer and the subsequent process form a good electrical connection without short-circuiting the second metal layer 105. Figure 6 As shown, during the etching of the third step, the etching needs to stop at the surface of the 105 metal layer with a good selectivity, and avoid the 101 metal layer and the 103 metal layer from being damaged by etching, at least ensuring that the 101 metal layer and the 103 metal layer have complete thin films.

[0064] The widths of the second step and the third step depend on the requirements of subsequent processes. In one embodiment of the present invention, they are related to the size of the through electrode.

[0065] In one embodiment of the present invention, the photoresist is trimmed, usually using dry plasma etching to perform in-situ trimming.

[0066] It should be noted that the trimming and etching of the photoresist can be performed together in the same process without destroying the vacuum environment. The first step, the second step and the third step can be completed in different photolithography steps, or three steps can be formed by multiple trimmings in one photolithography. The position of the step can be set close to the edge of the semiconductor substrate or in the middle according to the needs.

[0067] S53, removing the photoresist.

[0068] After forming three steps corresponding to the three deposited metal layers, the photoresist is removed.

[0069] S6, filling the second capacitor dielectric layer.

[0070] like Figure 7 As shown, a second capacitor dielectric layer 107 is deposited for filling and chemical mechanical polishing is performed.

[0071] In some embodiments of the present application, commonly used materials for the second capacitor dielectric layer 107 include silicon oxide (SiO2), silicon nitride (SiNx), etc., or a combination of one or more materials.

[0072] Among them, chemical mechanical polishing is used to planarize the surface, and other methods can also be used to achieve the same effect, such as dry etching, wet etching, etc.

[0073] It should be noted that the top of the capacitor structure should not be exposed during the planarization process, and the remaining surface of the second capacitor dielectric layer 107 can be parallel or non-parallel to the surface of the first capacitor dielectric layer 106 .

[0074] S7, performing photolithography and etching based on the second capacitor dielectric layer to obtain a plurality of through electrodes corresponding to the connected metal films or metal layers.

[0075] The etching stops at the bottom metal layer, the first metal layer 103 and the second metal layer 105 to form contact, and then metal filling and chemical mechanical polishing are performed to form the through electrode 108 .

[0076] The photolithography is used to form a cylindrical hole, and the through electrode 108 is formed by etching the second capacitor dielectric layer 107. The through electrode 108 can be in the form of a connecting through hole. Figure 8 As shown, the connecting through holes are represented by symbols T1, T2, and T3. Each deposited metal layer is connected to at least one connecting through hole, and the number of connecting through holes is related to the number of stacked metal film layers.

[0077] Based on the high selectivity of etching the second capacitor dielectric layer 107 to the metal layers 101 , 103 and 105 , an electrical connection is formed.

[0078] S8, metal interconnecting the through electrodes to obtain a stacked capacitor with a parallel structure.

[0079] like Fig. 9 , which is a top view of the capacitor structure after the second capacitor dielectric layer is filled, and the metal through holes are connected by metal interconnection, so that the odd-numbered layers or even-numbered layers of the metal layer are connected together to form the positive electrode or negative electrode of the capacitor, thereby forming a parallel structure of the capacitor. The capacitance value is increased through the parallel structure.

[0080] The stacked capacitor is formed by the above-mentioned method for preparing the stacked capacitor. Figure 8 The stacked capacitor structure shown,

[0081] In yet another embodiment of the present invention, a packaging structure of a stacked capacitor is prepared by the above-mentioned method for preparing a stacked capacitor.

[0082] It should be noted that the stacked capacitor in the present application can be in the form of an on-chip capacitor or in the form of a capacitor structure in a system-level packaged chip.

[0083] The packaging structure of the stacked capacitor includes a semiconductor substrate, a columnar array, a step portion, a connecting portion, and a filling dielectric layer. Among them, a metal film layer is deposited on the first surface of the semiconductor substrate to form a bottom metal layer; the columnar array includes at least a number of columns vertically supported on and connected to the bottom metal layer, and a number of dielectric layers and metal layers are deposited on the surface of the columnar array at intervals; the step portion is arranged on one side of the semiconductor substrate, including a number of staggered steps parallel to the bottom metal layer, and the upper surface of each step corresponds to the metal layer deposited on the surface of the column, and the lower surface corresponds to the dielectric layer deposited on the surface of the column; the connecting portion includes a number of through electrodes, which are perpendicular to the steps and penetrate the upper surface of the steps; the through electrodes are respectively connected as the positive and negative electrodes of the stacked capacitor to realize the parallel connection of the capacitor; the filling dielectric layer includes at least a first capacitor dielectric layer filled between the columns and a second capacitor dielectric layer filled between the through electrodes.

[0084] In one embodiment of the present invention, the top surface shape of the pillar may be circular, elliptical or other shapes, and the side wall angle may be different according to the device design and actual process capability.

[0085] The bottom metal layer can be the same or different metal as the columnar structure. Stacked capacitors need to rely on multiple steps to achieve external electrical connection of different metal layers. Each dielectric layer and metal layer are stacked alternately, and the thickness of each layer is related to device design and process capabilities. Different through electrodes can have different heights, which can be achieved through one or more lithography. The height of each step can also be the same or different. The through electrodes can use through holes or other connection forms.

[0086] The present invention discloses a packaging structure and a preparation method of a stacked capacitor. By etching to form a columnar array combined with multi-layer stacked capacitors and utilizing a capacitor parallel structure, the problems of difficult trench filling, complex etching control and extremely high cost in traditional deep trench capacitors are solved. The invention has broad application prospects in advanced packaging and high-performance computing scenarios.

[0087] It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may be combined into a single step for description in other embodiments.

[0088] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiment described above are only illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

Claims

1. A packaging structure of a stacked capacitor, characterized in that: At least: A semiconductor substrate, wherein a metal film layer is deposited on a first surface of the semiconductor substrate to form a bottom metal layer; A columnar array at least comprises a bottom metal layer and a plurality of columns vertically supported on and connected to the bottom metal layer, wherein a plurality of dielectric layers and metal layers disposed at intervals are deposited on the surface of the columnar array; The step portion includes a plurality of steps arranged in parallel on the upper surface of the bottom metal layer, wherein the upper surface of each step corresponds to the metal layer deposited on the surface of the column, and the lower surface corresponds to the dielectric layer deposited on the surface of the column; A connecting portion, the connecting portion comprising a plurality of through electrodes, the through electrodes being vertically supported on the upper surface of the step and respectively connected with the upper surface of the corresponding step; the plurality of through electrodes are respectively connected as the positive electrode and the negative electrode of the stacked capacitor to realize capacitor parallel connection; The filling dielectric layer at least includes a first capacitor dielectric layer filled between the pillars and a second capacitor dielectric layer filled between the through electrodes.

2. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The top surface of the column is circular or elliptical.

3. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The width of the step is determined based on the size of the through electrode.

4. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The first capacitor dielectric layer, the second capacitor dielectric layer and the dielectric layer are all made of at least one or a combination of silicon oxide, silicon nitride, hafnium oxide, yttrium aluminate, barium titanate and tantalum oxide.

5. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The bottom metal layer and the metal layer are made of a combination of one or more materials selected from the group consisting of polysilicon, tungsten, copper, titanium and ruthenium.

6. A method for preparing a stacked capacitor having a packaging structure as claimed in any one of claims 1 to 5, characterized in that: include: Depositing a metal film on the first surface of the semiconductor substrate to form a bottom metal layer, Performing photolithography and etching to form a plurality of pillars, wherein the pillars are vertically supported on the bottom metal layer and connected to the bottom metal layer, and the pillars and the bottom metal layer form a columnar array; Depositing a dielectric layer and a metal layer in sequence and at intervals on the surface of the columnar array; Filling the first capacitor dielectric layer to obtain a first capacitor structure; Photolithography and etching are performed on the first capacitor structure to obtain a plurality of steps corresponding to the bottom metal layer and the deposited metal layer respectively; Filling the second capacitor dielectric layer; Photolithography and etching are performed based on the second capacitor dielectric layer to obtain a plurality of through electrodes corresponding to and connected to the bottom metal layer or metal layers; The through electrodes are metal interconnected to obtain a stacked capacitor with a parallel structure.

7. The method for preparing a stacked capacitor according to claim 6, characterized in that: The depositing of the dielectric layer, the depositing of the metal layer, the filling of the first capacitor dielectric layer, and the filling of the second capacitor dielectric layer adopt a filling method with a high step coverage rate.

8. The method for preparing a stacked capacitor according to claim 6, characterized in that: The filled second capacitor dielectric layer and the second dielectric layer are planarized by at least one or more of chemical mechanical grinding, dry etching and wet etching.

9. The method for preparing a stacked capacitor according to claim 6, characterized in that: The photolithography and etching of the second capacitor dielectric layer to obtain a plurality of through electrodes connected to the bottom metal layer or metal layer specifically includes etching on the step based on the selection ratio of the second capacitor dielectric layer and the metal layer to obtain the through electrodes.

10. A method for preparing a stacked capacitor according to claim 6, characterized in that: The photoresist trimming is performed in-situ by at least dry plasma etching.

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