IGBT device and manufacturing method thereof
By annealing the polysilicon layer in the trench gate structure of the IGBT device and optimizing the subsequent process, the problems of discrete saturation voltage drop and poor threshold voltage uniformity are solved, and more efficient production and performance improvement are achieved.
Patent Information
- Application Number
- CN202411479786.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-02-07
AI Technical Summary
During the manufacturing process, the distance between the body contact hole and the trench gate is reduced, resulting in discrete saturation voltage drop and poor threshold voltage uniformity, which increases production difficulty and cost.
By annealing the polysilicon layer in the trench gate structure, a dense annealed polysilicon layer is formed, and in the subsequent process, back-etching is made to form a groove, covering the gate isolation layer and the dielectric layer, and finally forming a contact through the emitter region hole.
Improves threshold voltage uniformity between different memory cells and between different devices in IGBT devices, simplifies production processes, improves yield and yield, and improves device performance.
Smart Images
Figure CN119403146A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an IGBT device and a manufacturing method thereof. Background Art
[0002] IGBT (Insulated Gate Bipolar Transistor) devices have evolved from planar to trench type, and the pitch between repeated structural units is getting smaller and smaller, so that the distance between the body contact hole and the trench gate is also getting smaller and smaller, and the problem of wafer warpage is becoming more and more serious, which leads to higher and higher requirements for the alignment accuracy of the body contact hole mask and the alignment accuracy of the trench gate mask, and ultimately leads to more and more difficult processes for manufacturing IGBT devices. If the body contact hole mask and the trench gate mask are poorly aligned, the distance between the body contact hole and the trench gate will be too narrow, which will cause the saturation voltage drop (Vcesat) in the IGBT device to be discrete. At the same time, when etching to form the body contact hole, in order to allow the formed body contact hole to expose the maximum body area, it is necessary to etch back the gate conductive layer in the trench gate. However, the depth and morphology of the gate conductive layer after back etching in different storage cells are less consistent, resulting in deterioration of the top morphology of the final IGBT device, and poor uniformity of the threshold voltage (Vth) between different storage cells in the IGBT device and between different IGBT devices, which is not conducive to mass production of IGBT devices.
[0003] Therefore, how to improve the uniformity of the threshold voltage between different storage cells within the IGBT device and between different IGBT devices while avoiding the discreteness of the saturation voltage drop of the IGBT device, thereby simplifying the production process of the IGBT device, improving the yield and yield of the IGBT device, and improving the performance of mass-produced IGBT devices, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides an IGBT device and a manufacturing method thereof, which are used to improve the uniformity of threshold voltages between different storage cells in the IGBT device and between different IGBT devices while avoiding the discreteness of the saturation voltage drop of the IGBT device, thereby simplifying the production process of the IGBT device, improving the production rate and yield of the IGBT device, and improving the performance of the mass-produced IGBT devices.
[0005] According to some embodiments, the present invention provides a method for manufacturing an IGBT device, comprising the following steps:
[0006] Forming a substrate, the substrate comprising a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a plurality of trench gate structures, the trench gate structure comprising a gate trench continuously penetrating the emitter region, the body region, and the carrier storage region, a gate dielectric layer covering an inner wall of the gate trench, and a polysilicon layer at least filling the gate trench and covering the gate dielectric layer;
[0007] Annealing the polysilicon layer to form an annealed polysilicon layer;
[0008] Etching back the annealed polysilicon layer in the plurality of gate trenches to form a groove in the substrate located above the remaining annealed polysilicon layer;
[0009] forming a gate isolation layer covering the inner wall of the groove and a dielectric layer filling the groove and covering the gate isolation layer;
[0010] A contact hole is formed that at least penetrates the emitter region and exposes the body region.
[0011] In some embodiments, the specific steps of forming the substrate include:
[0012] Providing a substrate, the substrate comprising a first main surface and a second main surface oppositely distributed along a first direction;
[0013] sequentially forming the carrier storage region located above the first main surface of the substrate along the first direction, the body region located above the carrier storage region along the first direction, and the emitter region located above the body region along the first direction;
[0014] forming a gate trench penetrating the emitter region, the body region and the carrier storage region along the first direction and extending to the interior of the substrate, wherein a plurality of the gate trenches are arranged at intervals at least along a second direction, and the second direction is parallel to the first main surface;
[0015] forming the gate dielectric layer covering the inner wall of the gate trench;
[0016] The polysilicon layer is formed to fill the gate trench and cover the gate dielectric layer and the emitter region.
[0017] In some embodiments, the polysilicon layer is annealed to form an annealed polysilicon layer, and the specific steps include:
[0018] The polysilicon layer is subjected to furnace tube thermal annealing treatment at a temperature of 950° C. to 1100° C. to form the annealed polysilicon layer.
[0019] In some embodiments, before etching back the annealed polysilicon layer in the plurality of gate trenches, the method further includes the following steps:
[0020] A first oxide layer on the surface of the annealed polysilicon layer is removed, wherein the first oxide layer is formed during the annealing process.
[0021] In some embodiments, the specific steps of etching back the annealed polysilicon layer in the plurality of gate trenches to form a groove in the substrate located above the remaining annealed polysilicon layer include:
[0022] The annealed polysilicon layer is etched back to remove the annealed polysilicon layer on the surface of the emitter region, and a groove is formed in the substrate above the remaining annealed polysilicon layer, and the top surface of the remaining annealed polysilicon layer is higher than the bottom surface of the emitter region.
[0023] In some embodiments, the depth of the groove is 0.3 μm to 0.6 μm.
[0024] In some embodiments, the specific steps of forming a gate isolation layer covering the inner wall of the groove and a dielectric layer filling the groove and covering the gate isolation layer include:
[0025] forming a second oxide layer covering the inner wall of the groove and the surface of the emitter region by a thermal oxidation process, and using the second oxide layer as the gate isolation layer;
[0026] A dielectric material is deposited on the substrate to form a dielectric layer that fills the groove and covers the gate isolation layer.
[0027] In some embodiments, the specific steps of forming a contact hole that at least penetrates the emitter region and exposes the body region include:
[0028] removing a portion of the gate isolation layer and the dielectric layer to expose the emitter region;
[0029] The emitter region and the body region are etched by a dry etching process to form the contact hole that penetrates the emitter region and extends into the body region.
[0030] In some embodiments, after forming a contact hole that at least penetrates the emitter region and exposes the body region, the method further includes the following steps:
[0031] forming a conductive contact layer at the bottom of the contact hole;
[0032] A front metal layer is formed which at least covers the conductive contact layer and the emitter region and completely fills the contact hole.
[0033] In some embodiments, the material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; the specific steps of forming a conductive contact layer at the bottom of the contact hole include:
[0034] The first doping ions are implanted into the body region at the bottom of the contact hole to form the conductive contact layer, wherein the concentration of the first doping ions in the conductive contact layer is higher than the concentration of the first doping ions in the body region.
[0035] According to some other embodiments, the present invention further provides an IGBT device, which is formed by the manufacturing method of the IGBT device as described above; the IGBT device comprises:
[0036] substrate;
[0037] A carrier storage region, located above the substrate;
[0038] A body region, located on a surface of the carrier storage region facing away from the substrate;
[0039] An emitter region, located on a surface of the body region facing away from the carrier storage region;
[0040] A plurality of trench gate structures, wherein the trench gate structures include gate trenches continuously penetrating the emitter region, the body region and the carrier storage region, a gate dielectric layer covering inner walls of the gate trenches, and an annealed polysilicon layer at least filling the gate trenches and covering the gate dielectric layer;
[0041] a groove located above the annealed polysilicon layer;
[0042] A gate isolation layer covering an inner wall of the groove;
[0043] a dielectric layer, covering the gate isolation layer and filling the groove;
[0044] The lead-out structure comprises a contact hole which at least penetrates the emitter region and exposes the body region, a conductive contact layer located at the bottom of the contact hole, and a front metal layer which at least covers the conductive contact layer and fills the contact hole.
[0045] In some embodiments, the depth of the groove is 0.3 μm to 0.6 μm.
[0046] In some embodiments, the body region is made of silicon material including first doping ions, the emitter region is made of silicon material including second doping ions, the gate isolation layer is made of silicon dioxide, and the dielectric layer is made of borophosphosilicate glass.
[0047] In some embodiments, the material of the body region is a silicon material including a first doping ion, the material of the emitter region is a silicon material including a second doping ion, the material of the conductive contact layer is a silicon material including the first doping ion, and the concentration of the first doping ion in the conductive contact layer is higher than the concentration of the first doping ion in the body region, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.
[0048] The IGBT device and the manufacturing method thereof provided by the present invention form an annealed polysilicon layer by annealing the polysilicon layer in the trench gate structure, so that the amorphous silicon in the polysilicon layer is converted into polysilicon, thereby improving the density of the formed annealed polysilicon layer. On the one hand, the filling effect of the polysilicon material in the gate trench is improved, and defects such as gaps in the annealed polysilicon layer are reduced, thereby improving the electrical performance of the trench gate structure; on the other hand, the consistency of the depth and morphology of the groove formed after the subsequent back etching of the annealed polysilicon layer is improved, and while avoiding the discrete saturation voltage drop of the IGBT device, the uniformity of the threshold voltage between different storage cells in the IGBT device and between different IGBT devices is improved, thereby simplifying the production process of the IGBT device, improving the yield and yield of the IGBT device, and improving the performance of the mass-produced IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] Figure 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention;
[0050] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;
[0051] Figure 3 is a schematic diagram of the structure after the polysilicon layer is annealed in a specific embodiment of the present invention;
[0052] Figure 4 is a schematic diagram of the structure after the groove is formed in a specific embodiment of the present invention;
[0053] Figure 5 is a schematic diagram of a structure after a gate isolation layer is formed in a specific embodiment of the present invention;
[0054] Figure 6 is a schematic diagram of the structure after the dielectric layer is formed in a specific embodiment of the present invention;
[0055] Figure 7 is a schematic diagram of the structure after a portion of the gate isolation layer and the dielectric layer are removed in a specific embodiment of the present invention;
[0056] Figure 8is a schematic diagram of the structure after the contact hole is formed in a specific embodiment of the present invention;
[0057] Fig. 9 is a schematic diagram of the structure after a conductive contact layer is formed in a specific embodiment of the present invention;
[0058] Fig.10 is a schematic diagram of the structure after the front metal layer is formed in a specific embodiment of the present invention;
[0059] Fig.11 It is a schematic diagram of the structure after the back metal layer is formed according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0060] The specific implementation manner of the IGBT device and the manufacturing method thereof provided by the present invention is described in detail below with reference to the accompanying drawings.
[0061] This specific embodiment provides a method for manufacturing an IGBT device. Figure 1 FIG. 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the IGBT device comprises the following steps:
[0062] Step S11, forming a substrate, wherein the substrate includes a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a plurality of trench gate structures, wherein the trench gate structure includes a gate trench continuously penetrating the emitter region, the body region, and the carrier storage region, a gate dielectric layer covering an inner wall of the gate trench, and a polysilicon layer at least filling the gate trench and covering the gate dielectric layer;
[0063] Step S12, annealing the polysilicon layer to form an annealed polysilicon layer;
[0064] Step S13, etching back the annealed polysilicon layer in the plurality of gate trenches to form a groove in the substrate located above the remaining annealed polysilicon layer;
[0065] Step S14, forming a gate isolation layer covering the inner wall of the groove and a dielectric layer filling the groove and covering the gate isolation layer;
[0066] Step S15 , forming a contact hole that at least penetrates the emitter region and exposes the body region.
[0067] Figure 2 Schematic diagram of the structure of the substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the substrate include:
[0068] Providing a substrate 20, wherein the substrate 20 includes a first main surface 201 and a second main surface 202 that are oppositely distributed along a first direction D1;
[0069] sequentially forming the carrier storage region 21 located above the first main surface 201 of the substrate 20 along the first direction D1, the body region 22 located above the carrier storage region 21 along the first direction D1, and the emitter region 23 located above the body region 22 along the first direction D1;
[0070] A gate trench 24 is formed along the first direction D1, penetrating the emitter region 23, the body region 22 and the carrier storage region 21 and extending to the inside of the substrate 20, wherein a plurality of the gate trenches 24 are arranged at intervals at least along a second direction D2, and the second direction D2 is parallel to the first main surface 201;
[0071] forming the gate dielectric layer 25 covering the inner wall of the gate trench 24;
[0072] The polysilicon layer 26 is formed to fill the gate trench 24 and cover the gate dielectric layer 25 and the emitter region 23. Figure 2 shown.
[0073] Specifically, the substrate 20 may be a single crystal silicon substrate. In some embodiments, the substrate 20 may also be made of other materials, such as but not limited to silicon germanium, germanium, silicon carbide, gallium arsenide or indium phosphide. The substrate 20 includes the first main surface 201 and the second main surface 202 which are relatively distributed along the first direction D1, and the carrier storage area 21, the body area 22 and the emitter area 23 are sequentially stacked on the first main surface 201 of the substrate 20 along the first direction D1. In one example, the substrate 20 is an N-type ion-doped substrate, the carrier storage area 21 is N-type ion-doped, the body area 22 is P-type ion-doped, and the emitter area 23 is N-type ion-doped. Among them, the ion doping concentration in the substrate 20, the ion doping concentration in the carrier storage area 21, the ion doping concentration in the body area 22 and the ion doping concentration in the emitter area 23 can be set according to the parameters such as the on-resistance and reverse withstand voltage performance of the IGBT device to be prepared.
[0074] The emitter region 23, the body region 22, the carrier storage region 21 and the substrate 20 may be etched along the first direction by a dry etching process to form a gate trench 24 that continuously penetrates the emitter region 23, the body region 22 and the carrier storage region 21 along the first direction D1 and extends to the interior of the substrate 20. Afterwards, silicon dioxide or a high-K dielectric material is deposited in the gate trench 24 to form the gate dielectric layer 25 that covers the inner wall of the gate trench 24 (including the sidewall of the gate trench 24 and the bottom surface of the gate trench 24). Next, a material such as polysilicon is deposited on the substrate to form the polysilicon layer 26 that fills the gate trench 24 and covers the gate dielectric layer 25 and the emitter region 23, as shown in FIG. Figure 2 As shown, the IGBT device has a trench gate structure. In one example, a plurality of the gate trenches 24 are arranged at intervals along the second direction D2, so that a plurality of the trench gate structures are arranged along the second direction D2. The polysilicon layer 26 formed by the deposition process is a mixture of polysilicon and amorphous silicon, and the filling uniformity is poor. Moreover, when the polysilicon material is deposited by the deposition process to fill the gate trench 24, it is easy to generate gaps in the polysilicon layer 26 in the gate trench 24, and the depth and position of the gaps are random, that is, the position and depth of the gaps in the polysilicon layer 26 in the plurality of gate trenches 24 are less consistent. The plurality described in this specific embodiment refers to more than two.
[0075] Figure 3 2 is a schematic diagram of the structure after the polysilicon layer is annealed in a specific embodiment of the present invention. In some embodiments, the specific steps of annealing the polysilicon layer 26 to form the annealed polysilicon layer 30 include:
[0076] The polysilicon layer 26 is subjected to furnace tube thermal annealing treatment at a temperature of 950° C. to 1100° C. to form the annealed polysilicon layer 30. Figure 3 shown.
[0077] For example, the polysilicon layer 26 is thermally annealed by a furnace tube process, so that the amorphous silicon in the polysilicon layer is converted into polysilicon, and the filling gaps in the gate trench 24 are reduced, thereby improving the density of the formed annealed polysilicon layer 30. On the one hand, the filling effect of the polysilicon material in the gate trench 24 is improved, and defects such as gaps in the annealed polysilicon layer 30 are reduced, thereby improving the electrical performance of the trench gate structure; on the other hand, the consistency of the structure and morphology of the polysilicon materials filled in different gate trenches 24 is improved, thereby improving the consistency of the depth and morphology of the groove formed after the subsequent back etching of the annealed polysilicon layer 30, while avoiding the discrete saturation voltage drop of the IGBT device, the uniformity of the threshold voltage between different storage cells in the IGBT device and between different IGBT devices is improved, thereby simplifying the production process of the IGBT device, improving the yield and yield of the IGBT device, and improving the performance of the mass-produced IGBT devices. In one example, the annealing temperature is 950° C. to 1100° C., and the annealing time is 30 min to 120 min, so that the amorphous silicon in the plurality of gate trenches 24 is fully converted into polysilicon and damage to other device structures in the substrate is avoided.
[0078] In some embodiments, before etching back the annealed polysilicon layer 30 in the plurality of gate trenches 24, the following steps are further included:
[0079] The first oxide layer 31 on the surface of the annealed polysilicon layer 30 is removed, wherein the first oxide layer 31 is formed during the annealing process.
[0080] Specifically, during the process of furnace tube thermal annealing of the polysilicon layer 26, the surface of the polysilicon layer 26 is easily oxidized to form the first oxide layer 31 made of silicon dioxide. The first oxide layer 31 on the surface of the annealed polysilicon layer 30 can be removed by a wet etching process to expose the annealed polysilicon layer 30, thereby facilitating subsequent back etching of the annealed polysilicon layer 30. In an example, the thickness of the first oxide layer 31 (for example, the thickness along the first direction D1) is
[0081] Figure 4 2 is a schematic diagram of a structure after a groove is formed in a specific embodiment of the present invention. In some embodiments, the specific steps of etching back the annealed polysilicon layer 30 in the plurality of gate trenches 24 to form a groove 40 located above the remaining annealed polysilicon layer 30 in the substrate include:
[0082] The annealed polysilicon layer 30 is etched back to remove the annealed polysilicon layer 30 on the surface of the emitter region 23, and a groove 40 is formed in the substrate above the remaining annealed polysilicon layer 30, and the top surface of the remaining annealed polysilicon layer 30 is higher than the bottom surface of the emitter region 23, such as Figure 4 shown.
[0083] For example, part of the annealed polysilicon layer 30 is etched back to remove all of the annealed polysilicon layer 30 on the top surface of the emitter region 23 (i.e., the surface of the emitter region 23 facing away from the substrate 20) and part of the annealed polysilicon layer 30 in the gate trench 24, thereby lowering the height of the annealed polysilicon layer 30 in the gate trench 24, so that the top surface of the remaining annealed polysilicon layer 30 is lower than the top surface of the emitter region 23, so as to form the groove 40 located above the annealed polysilicon layer 30 in the substrate. Since the annealed polysilicon layer 30 is a polysilicon layer that has been annealed, the depth and morphology of the back etching of the plurality of annealed polysilicon layers 30 arranged along the second direction D2 can be improved, so that the depths of the plurality of grooves 40 arranged along the second direction D2 (for example, the depths along the first direction D1) are all the same, and the morphologies of the plurality of grooves 40 arranged along the second direction D2 are all the same (for example, the cross-sections of the plurality of grooves 40 arranged along the second direction D2 are all rectangular), thereby ensuring not only the performance consistency of the plurality of trench gate structures in the IGBT device, but also the consistency of different IGBT devices in the same batch, and improving the uniformity of the threshold voltage between different storage cells in the IGBT device and between different IGBT devices. By forming the groove 40, it is convenient to form the contact hole through a self-alignment process in the subsequent process to avoid the discrete saturation voltage drop of the IGBT device.
[0084] In some embodiments, the depth of the groove 40 (eg, the depth along the first direction D1 ) is 0.3 μm to 0.6 μm, thereby providing sufficient space for subsequent formation of a gate isolation layer and a filling dielectric layer while avoiding affecting the electrical performance of the trench gate structure.
[0085] Figure 5 is a schematic diagram of a structure after a gate isolation layer is formed in a specific embodiment of the present invention, Figure 6 is a schematic diagram of the structure after the dielectric layer is formed in a specific embodiment of the present invention, Figure 7 Schematic diagram of the structure after removing part of the gate isolation layer and the dielectric layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the gate isolation layer 50 covering the inner wall of the groove 40 and the dielectric layer 60 filling the groove 40 and covering the gate isolation layer 50 include:
[0086] A second oxide layer covering the inner wall of the groove 40 and the surface of the emitter region 23 is formed by a thermal oxidation process, and the second oxide layer is used as the gate isolation layer 50. Figure 5 As shown;
[0087] A dielectric material is deposited on the substrate to form a dielectric layer 60 that fills the groove 40 and covers the gate isolation layer 50. Figure 6 shown.
[0088] Figure 8 2 is a schematic diagram of a structure after forming a contact hole in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the contact hole 80 that at least penetrates the emitter region 23 and exposes the body region 22 include:
[0089] Part of the gate isolation layer 50 and the dielectric layer 60 are removed to expose the emitter region 23. Figure 7 As shown;
[0090] The emitter region 23 and the body region 22 are etched by dry etching process to form the contact hole 80 penetrating the emitter region 23 and extending into the body region 22. Figure 8 shown.
[0091] For example, the second oxide layer that continuously covers the inner walls of the plurality of grooves 40 and the top surface of the emitter region 23 can be formed by a furnace thermal oxidation process, and the second oxide layer is used as the gate isolation layer 50. Figure 5 As shown. Wherein, the material of the second oxide layer can be silicon dioxide. In one example, the thickness of the gate isolation layer 50 can be Next, an insulating material such as borophosphosilicate glass material is deposited on the surface of the gate isolation layer 50 to form the dielectric layer 60. Figure 6 In one example, the thickness of the dielectric layer 60 is Afterwards, the borophosphosilicate glass material is reflowed, wherein the reflow temperature is 900°C to 1000°C and the reflow time is 30min to 240min. Next, a chemical mechanical polishing or etching process is used to remove part of the gate isolation layer 50 and the dielectric layer 60 to expose the emitter region 23. Figure 7 shown.
[0092] Since the materials of the gate isolation layer 50 and the dielectric layer 60 are both oxide materials, and the emitter region 23 and the body region 22 are both silicon materials, the difference in etching rate between the oxide material and silicon can be utilized to etch the emitter region 23 and the body region 22 through a self-aligned process, thereby forming the contact hole 80 penetrating the emitter region 23 and extending into the body region 22. Figure 8 By adopting the above method, even when the distance between the preset position of the contact hole 60 and the trench gate structure is reduced, damage to the trench gate structure can be reduced or even avoided, and the consistency of the distance between the plurality of contact holes 80 and the adjacent trench gate structures is improved, thus avoiding the problem of discrete saturation voltage drop of the IGBT device.
[0093] Fig. 9 is a schematic diagram of the structure after the conductive contact layer is formed in a specific embodiment of the present invention, Fig.10 is a schematic diagram of the structure after the front metal layer is formed in a specific embodiment of the present invention, Fig.11 2 is a schematic diagram of a structure after forming a back metal layer in a specific embodiment of the present invention. In some embodiments, after forming a contact hole 80 that at least penetrates the emitter region 23 and exposes the body region 22, the following steps are also included:
[0094] A conductive contact layer 90 is formed at the bottom of the contact hole 80. Fig. 9 As shown;
[0095] A front metal layer is formed which at least covers the conductive contact layer 90 and the emitter region 23 and completely fills the contact hole 80 .
[0096] In some embodiments, the material of the body region 22 is a silicon material including a first doping ion, and the material of the emitter region 23 is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; the specific steps of forming the conductive contact layer 90 at the bottom of the contact hole 80 include:
[0097] The first doping ions are implanted into the body region 22 at the bottom of the contact hole 80 to form the conductive contact layer 90 , and the concentration of the first doping ions in the conductive contact layer 90 is higher than the concentration of the first doping ions in the body region 22 .
[0098] In one example, the first doping ion is a P-type ion. By forming the conductive contact layer 90 with a high doping concentration, it can be ensured that the front metal layer formed in the contact hole 80 has good ohmic contact with the body region 22. For example, the first doping ion is a boron ion, and the first doping ion injected into the body region 22 at the bottom of the contact hole 80 may be injected into the body region 22 at the bottom of the contact hole 80, and the injection energy may be 40keV to 100keV, and the injection dose may be 5×10 12 Pieces / cm 2 ~1×10 15 Pieces / cm 2 For another example, the first doping ion is a boron ion, and the first doping ion implanted into the body region 22 at the bottom of the contact hole 80 may be implanted with boron difluoride into the body region 22 at the bottom of the contact hole 80, and the implantation energy may be 20keV to 50keV, and the implantation dose may be 1×10 15 Pieces / cm 2 ~5×10 15 Pieces / cm 2 .
[0099] After forming the conductive contact layer 90, an atomic layer deposition process may be used to deposit a material such as metal tungsten in the contact hole 80 to form a first metal layer 100 that fills the contact hole 80 and covers the conductive contact layer 90 and the emitter region 23. Then, an atomic layer deposition process is used to deposit AlCu or the like on the substrate to form a second metal layer 101 that continuously covers the first metal layers 100, the gate isolation layer 50 and the dielectric layer 60. Fig.10 As shown, the first metal layer 100 and the second metal layer 101 together serve as the front metal layer.
[0100] After forming the front metal layer, the substrate is turned over and the second main surface 202 of the substrate 20 is thinned. The thickness of the substrate 20 thinned depends on the voltage resistance requirements of the IGBT device. Afterwards, the first doping ions (e.g., boron ions) are implanted into the substrate 20 from the second main surface 202 of the substrate 20, and the implanted first doping ions are activated by an annealing process to form a collector region 111 on the second main surface of the substrate 20. In one example, the ion implantation energy when forming the collector region 111 is 20keV to 60keV, and the implantation dose is 1×10 12 Pieces / cm 2 ~1×10 14 Pieces / cm 2Next, the second doping ions are implanted from the second main surface 202 of the substrate 20, and annealing is performed to form a buffer layer 112 on the side of the collector region 111 facing the first main surface 201. Then, an Al / Ti / Ni / Ag metal stack is deposited on the surface of the collector region 111 to form a back metal layer 110, such as Fig.11 In one example, the buffer layer 112 is formed by injecting hydrogen ions. The number of hydrogen ion injections is between 2 and 4 times. By adjusting the injection dose and injection energy of the hydrogen ions each time, a hydrogen ion doping layer having multiple different doping peaks can be formed in the buffer layer 102 after annealing, for example Fig.11 Four different hydrogen ion doping peaks are shown, namely a first hydrogen ion doping peak 1121 , a second hydrogen ion doping peak 1122 , a third hydrogen ion doping peak 1123 and a fourth hydrogen ion doping peak 1124 .
[0101] This specific embodiment also provides an IGBT device. The IGBT device is formed by the manufacturing method of the IGBT device as described above, see Figure 1-Figure 11 .like Figure 1-Figure 11 As shown, the IGBT device comprises:
[0102] Substrate 20;
[0103] A carrier storage region 21, located above the substrate 20;
[0104] a body region 22, located on a surface of the carrier storage region 21 facing away from the substrate 20;
[0105] an emitter region 23, located on a surface of the body region 22 away from the carrier storage region 21;
[0106] A plurality of trench gate structures, wherein the trench gate structures include a gate trench 24 continuously penetrating the emitter region 23, the body region 22 and the carrier storage region 21, a gate dielectric layer 25 covering the inner wall of the gate trench 24, and an annealed polysilicon layer 30 at least filling the gate trench 24 and covering the gate dielectric layer 25;
[0107] A groove 40, located above the annealed polysilicon layer 30;
[0108] A gate isolation layer 50 covering the inner wall of the groove 40;
[0109] A dielectric layer 60 covering the gate isolation layer 50 and filling the groove 40;
[0110] The lead-out structure includes a contact hole 80 at least penetrating the emitter region 23 and exposing the body region 22 , a conductive contact layer 90 located at the bottom of the contact hole 80 , and a front metal layer at least covering the conductive contact layer 90 and filling the contact hole 80 .
[0111] In some embodiments, the depth of the groove 40 is 0.3 μm to 0.6 μm.
[0112] In some embodiments, the body region 22 is made of silicon material including first doping ions, the emitter region 23 is made of silicon material including second doping ions, the gate isolation layer 50 is made of silicon dioxide, and the dielectric layer 60 is made of borophosphosilicate glass.
[0113] In some embodiments, the material of the body region 22 is a silicon material including a first doping ion, the material of the emitter region 23 is a silicon material including a second doping ion, the material of the conductive contact layer 90 is a silicon material including the first doping ion, and the concentration of the first doping ion in the conductive contact layer 90 is higher than the concentration of the first doping ion in the body region 22, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.
[0114] The IGBT device and the manufacturing method thereof provided in the present specific embodiment form an annealed polysilicon layer by annealing the polysilicon layer in the trench gate structure, so that the amorphous silicon in the polysilicon layer is converted into polysilicon, thereby improving the density of the formed annealed polysilicon layer. On the one hand, the filling effect of the polysilicon material in the gate trench is improved, and defects such as gaps in the annealed polysilicon layer are reduced, thereby improving the electrical performance of the trench gate structure; on the other hand, the consistency of the depth and morphology of the groove formed after the subsequent back etching of the annealed polysilicon layer is improved, while avoiding the discrete saturation voltage drop of the IGBT device, the uniformity of the threshold voltage between different storage cells in the IGBT device and between different IGBT devices is improved, thereby simplifying the production process of the IGBT device, improving the yield and yield of the IGBT device, and improving the performance of the mass-produced IGBT devices.
[0115] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing an IGBT device, characterized in that: The steps include: Forming a substrate, the substrate comprising a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a plurality of trench gate structures, the trench gate structure comprising a gate trench continuously penetrating the emitter region, the body region, and the carrier storage region, a gate dielectric layer covering an inner wall of the gate trench, and a polysilicon layer at least filling the gate trench and covering the gate dielectric layer; Annealing the polysilicon layer to form an annealed polysilicon layer; Etching back the annealed polysilicon layer in the plurality of gate trenches to form a groove in the substrate located above the remaining annealed polysilicon layer; forming a gate isolation layer covering the inner wall of the groove and a dielectric layer filling the groove and covering the gate isolation layer; A contact hole is formed that at least penetrates the emitter region and exposes the body region.
2. The method for manufacturing an IGBT device according to claim 1, characterized in that: The specific steps of forming the substrate include: Providing a substrate, the substrate comprising a first main surface and a second main surface oppositely distributed along a first direction; sequentially forming the carrier storage region located above the first main surface of the substrate along the first direction, the body region located above the carrier storage region along the first direction, and the emitter region located above the body region along the first direction; forming a gate trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends to the interior of the substrate, wherein a plurality of the gate trenches are arranged at intervals at least along a second direction, and the second direction is parallel to the first main surface; forming the gate dielectric layer covering the inner wall of the gate trench; The polysilicon layer is formed to fill the gate trench and cover the gate dielectric layer and the emitter region.
3. The method for manufacturing an IGBT device according to claim 2, characterized in that: The specific steps of annealing the polysilicon layer to form an annealed polysilicon layer include: The polysilicon layer is subjected to furnace tube thermal annealing treatment at a temperature of 950° C. to 1100° C. to form the annealed polysilicon layer.
4. The method for manufacturing an IGBT device according to claim 2, characterized in that: Before etching back the annealed polysilicon layer in the plurality of gate trenches, the method further includes the following steps: A first oxide layer on the surface of the annealed polysilicon layer is removed, wherein the first oxide layer is formed during the annealing process.
5. The method for manufacturing an IGBT device according to claim 2, characterized in that: The specific steps of etching back the annealed polysilicon layer in the plurality of gate trenches to form a groove in the substrate located above the remaining annealed polysilicon layer include: The annealed polysilicon layer is etched back to remove the annealed polysilicon layer on the surface of the emitter region, and a groove is formed in the substrate above the remaining annealed polysilicon layer, and the top surface of the remaining annealed polysilicon layer is higher than the bottom surface of the emitter region.
6. The method for manufacturing an IGBT device according to claim 1, characterized in that: The depth of the groove is 0.3 μm to 0.6 μm.
7. The method for manufacturing an IGBT device according to claim 1, characterized in that: The specific steps of forming a gate isolation layer covering the inner wall of the groove and a dielectric layer filling the groove and covering the gate isolation layer include: forming a second oxide layer covering the inner wall of the groove and the surface of the emitter region by a thermal oxidation process, and using the second oxide layer as the gate isolation layer; A dielectric material is deposited on the substrate to form a dielectric layer that fills the groove and covers the gate isolation layer.
8. The method for manufacturing an IGBT device according to claim 7, characterized in that: The specific steps of forming a contact hole that at least penetrates the emitter region and exposes the body region include: removing a portion of the gate isolation layer and the dielectric layer to expose the emitter region; The emitter region and the body region are etched by a dry etching process to form the contact hole that penetrates the emitter region and extends into the body region.
9. The method for manufacturing an IGBT device according to claim 1, characterized in that: After forming a contact hole that at least penetrates the emitter region and exposes the body region, the following steps are also included: forming a conductive contact layer at the bottom of the contact hole; A front metal layer is formed which at least covers the conductive contact layer and the emitter region and completely fills the contact hole.
10. The method for manufacturing an IGBT device according to claim 9, characterized in that: The material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, wherein the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; and the specific steps of forming a conductive contact layer at the bottom of the contact hole include: The first doping ions are implanted into the body region at the bottom of the contact hole to form the conductive contact layer, wherein the concentration of the first doping ions in the conductive contact layer is higher than the concentration of the first doping ions in the body region.
11. An IGBT device, characterized in that: The IGBT device is formed by the manufacturing method of the IGBT device according to claim 1; the IGBT device comprises: substrate; A carrier storage region, located above the substrate; A body region, located on a surface of the carrier storage region facing away from the substrate; An emitter region, located on a surface of the body region facing away from the carrier storage region; A plurality of trench gate structures, wherein the trench gate structures include gate trenches continuously penetrating the emitter region, the body region and the carrier storage region, a gate dielectric layer covering inner walls of the gate trenches, and an annealed polysilicon layer at least filling the gate trenches and covering the gate dielectric layer; a groove located above the annealed polysilicon layer; A gate isolation layer covering an inner wall of the groove; a dielectric layer, covering the gate isolation layer and filling the groove; The lead-out structure comprises a contact hole which at least penetrates the emitter region and exposes the body region, a conductive contact layer located at the bottom of the contact hole, and a front metal layer which at least covers the conductive contact layer and fills the contact hole.
12. The IGBT device according to claim 11, characterized in that: The depth of the groove is 0.3 μm to 0.6 μm.
13. The IGBT device according to claim 11, characterized in that: The material of the body region is a silicon material including a first doping ion, the material of the emitter region is a silicon material including a second doping ion, the material of the gate isolation layer is silicon dioxide, and the material of the dielectric layer is borophosphosilicate glass.
14. The IGBT device according to claim 11, characterized in that: The material of the body region is a silicon material including a first doping ion, the material of the emitter region is a silicon material including a second doping ion, the material of the conductive contact layer is a silicon material including the first doping ion, and the concentration of the first doping ion in the conductive contact layer is higher than the concentration of the first doping ion in the body region, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.