Manufacturing method of Trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with multiple film formation of grid polycrystalline silicon

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of a Trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) for multiple film formation of grid polycrystalline silicon. The manufacturing method of the Trench MOSFET mainly comprises the following steps: etching a groove on a silicon wafer with epitaxy, forming a gate oxide layer through a thermal oxidation process, then filling gate polycrystalline silicon for the first time, filling the gate polycrystalline silicon for the second time after etching, and forming a gate oxide layer on the gate oxide layer. And after surface grinding, a second oxide layer is formed through thermal oxidation, body injection and annealing treatment are carried out, and finally ion injection and annealing treatment are carried out on the source electrode. The Trench MOSFET manufactured by the manufacturing method disclosed by the invention is relatively good in insulativity and stability, and more uniform electric field distribution and relatively low on resistance can be realized, so that the performance and the reliability of the Trench MOSFET are improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a Trench MOSFET with multiple gate polysilicon film formation. Background Art

[0002] Trench MOSFET (trench metal oxide semiconductor field effect transistor) is a mature technology in modern semiconductor processes and is widely used in various low-power, high-efficiency power management systems. Its main advantages are lower on-resistance (Rds(on)) and lower gate-drain charge density, which leads to lower conduction losses and higher switching speeds. These characteristics make Trench MOSFET suitable for various applications with operating frequencies below 100kHz, such as power conversion, lighting drive, and motor control.

[0003] In view of the technical improvement of Trench MOSFET, existing patent documents have given methods for improving the structural stability and product reliability of Trench MOSFET. For example, patent document CN116564821A discloses a method for manufacturing a high-density Trench-type MOSFET, the core principle of which is to first implement well region injection before the trench, adopt a multi-layer hard mask structure of epitaxial silicon-silicon oxide-silicon nitride, and form side walls on both sides of the polycrystalline by SPACER etching technology, thereby improving the structural stability of the device. Its advantage is that by optimizing the process steps and process sequence, the reliability of the device is effectively improved, while avoiding the addition of additional photolithography layers. However, there are still problems of process complexity and high manufacturing cost, which limit its wider application. Although the existing Trench MOSFET technology has the advantages of low on-resistance and high switching speed, it still faces problems such as uneven polysilicon filling, uneven electric field distribution, complex process, poor thermal stability and insufficient long-term reliability. These problems not only affect the performance and reliability of the device, but also increase the manufacturing cost, limiting the further promotion of Trench MOSFET in more complex and demanding applications.

[0004] Therefore, the present invention designs and proposes a method for manufacturing a Trench MOSFET with multiple gate polysilicon film formation. By optimizing the multiple film formation and etching process of the gate polysilicon, the generation of gaps in the manufacturing process is effectively reduced, and the leakage problem caused by etching penetration is avoided. This patent not only simplifies the filling process of polysilicon, but also greatly improves the electrical performance and long-term reliability of the device, while maintaining the cost-effectiveness and process controllability in the manufacturing process, so that it is suitable for large-scale production and a wider range of application scenarios. Summary of the invention

[0005] The purpose of the present invention is to provide a novel method for manufacturing a trench metal oxide semiconductor field effect transistor (Trench MOSFET) to solve the problems existing in the prior art. By controlling the thickness of each polysilicon deposition, the current transmission path in the trench is optimized, the conduction loss is effectively reduced and the breakdown voltage of the device is increased, and a more uniform electric field distribution and a lower on-resistance can be achieved, thereby improving the performance and reliability of the Trench MOSFET.

[0006] In order to achieve the above-mentioned purpose, the present invention proposes the following technical scheme, a method for manufacturing a Trench MOSFET with multiple gate polysilicon film formation, characterized in that the Trench MOSFET device includes a silicon substrate, a trench structure located on the silicon substrate, a gate oxide layer, and a gate polysilicon layer that is deposited and etched multiple times.

[0007] In view of claim 1, the present invention adopts a silicon substrate with epitaxy, a groove design of a specific depth, and a special process for gate oxide layer and polysilicon layer, firstly forms a groove structure on a silicon wafer with epitaxy, and deposits a gate oxide layer and a first layer of polysilicon in the groove in sequence; then performs ion implantation and annealing treatment on the gate region, and further performs multiple deposition and etching of polysilicon in different regions of the groove; after each deposition and etching of polysilicon, ion implantation and high-temperature annealing are performed in sequence to ensure the formation of the body region and the source electrode. In the multiple deposition and etching processes, by optimizing the process steps, the problem of polysilicon voids in the traditional process is avoided, and the integrity of the groove structure and the stability of the electrical performance are ensured.

[0008] Preferably, with respect to claim 2, the monocrystalline silicon epitaxial layer grown on the silicon substrate has a thickness of 1 to 3 microns, has high uniformity and conductivity, and serves as the active region of the device. Through epitaxial growth technology, the layer has better conductivity and low on-resistance, making the Trench MOSFET suitable for high current density and high voltage applications, ensuring the electrical performance stability of the device under high voltage.

[0009] Further, with respect to claim 3, the groove structure is formed in the monocrystalline silicon epitaxial layer, and the groove depth ranges from 0.5 to 1 micron. The groove is precisely etched by a plasma etching process to ensure a smooth inner surface of the groove and reduce the electric field concentration effect. This groove design not only reduces leakage current, but also improves the switching speed and overall performance of the device, and is suitable for high-speed switching applications.

[0010] According to claim 4, the gate oxide layer is thermally grown silicon dioxide (SiO2) with a thickness ranging from 30 to 100 nanometers, covering the inner wall of the trench and forming a complete electric field isolation layer with the polysilicon layer. The gate oxide layer is generated by a high temperature (800°C to 1200°C) thermal oxidation process, and has excellent dielectric properties and electrical insulation, effectively reducing channel capacitance and improving the switching speed and stability of the MOSFET.

[0011] In accordance with claim 5, the etching process of the gate polysilicon adopts semiconductor dry etching to ensure accurate etching of the polysilicon layer in the groove. After the second polysilicon deposition, a chemical mechanical polishing (CMP) process is used to make the polysilicon filling flush with the substrate, ensuring that there are no gaps in the polysilicon deposition in the groove, thereby avoiding subsequent etching penetration problems.

[0012] Preferably, the first and second deposition thicknesses and film-forming temperatures of the gate polysilicon are different, wherein the thickness of the first polysilicon film is 2 to 3 times the thickness of the second polysilicon film, specifically, the first polysilicon film thickness is between 200 nanometers and 600 nanometers, and the second polysilicon film thickness is between 100 nanometers and 300 nanometers. The first polysilicon film-forming temperature is set to 580°C to ensure a high deposition rate and good crystal quality; and the second polysilicon film-forming temperature is 530°C, which helps control the subsequent film-forming process and reduce the thermal impact on the underlying structure.

[0013] Furthermore, the selection of the temperature and thickness of the gate polysilicon film can not only effectively improve the density and uniformity of the polysilicon layer, but also reduce the stress concentration caused by the difference in deposition rate to a certain extent, thereby improving the stability and reliability of the overall device. In addition, the setting of the thickness difference enables the electrical characteristics between the polysilicon layers to be better matched in the subsequent process, thereby optimizing the performance of the device.

[0014] In accordance with claim 6, the growth of the single crystal silicon epitaxial layer adopts low pressure chemical vapor deposition (LPCVD) technology to ensure high uniformity and low defect density of the epitaxial layer. By precisely controlling the deposition rate and the concentration of the reaction gas, the integrity of the crystal structure of the epitaxial layer is ensured, and it has excellent thermal stability and can maintain the stability of its electrical properties in high temperature processes.

[0015] In accordance with claim 7, the groove forming step includes depositing a hard mask layer of silicon nitride or silicon oxide on the single crystal silicon epitaxial layer, and after photolithography, anisotropic dry etching is performed to form a groove structure with a depth of 0.5 to 1 micron. After etching, a cleaning process is performed to ensure that the inner wall of the groove is smooth, avoid the electric field concentration effect, and improve the breakdown voltage of the device.

[0016] Preferably, with respect to claim 8, the gate polysilicon is formed by multiple deposition and etching processes, and the surface of the polysilicon layer after each deposition is passivated by plasma enhanced chemical vapor deposition (PECVD) technology. This treatment effectively reduces surface defects and interface state density, improves the conductivity and electrical stability of the device, and ensures the overall reliability of the gate polysilicon.

[0017] The manufacturing steps of the Trench MOSFET device are 9 steps in total, wherein step 1 selects a P-type or N-type doped silicon wafer with an epitaxial layer as the substrate material, and accurately defines the pattern of the groove on the surface of the epitaxial layer through mask technology and photolithography. Subsequently, a plasma etching technology is used to etch a groove with a depth of 0.5-1 micron in the epitaxial layer. This etching process must be strictly controlled to ensure the smoothness and depth-to-width ratio of the inner wall of the groove, thereby reducing the electric field concentration effect when the device is working and avoiding leakage. Step 2, after the trench etching is completed, a layer of gate oxide layer (SiO2) is grown on the inner wall of the trench using a high-temperature thermal oxidation process. This thermal oxidation process is usually carried out at a high temperature of 800°C to 1200°C to ensure that the thickness of the gate oxide layer is between 30-100 nanometers. The thickness and uniformity of the oxide layer are crucial to the electrical performance of the device, and can effectively isolate the gate polysilicon from the epitaxial silicon to ensure the electric field control capability of the gate. Step three, fill the gate polysilicon for the first time on the gate oxide layer in the trench, using chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD) process to ensure the uniform distribution of polysilicon in the trench. The thickness of the first polysilicon is usually 2-3 times that of the second polysilicon, and the thickness ranges from 200-600 nanometers. This step requires strict control of the deposition temperature and rate to ensure that the polysilicon fills the trench without gaps. Step four, after the first polysilicon filling is completed, dry etching (such as reactive ion etching, RIE) is performed to etch the polysilicon to the desired thickness and shape. This step can remove excess polysilicon, ensure the integrity of the gate structure, and provide a uniform surface for the subsequent second filling. At the same time, care should be taken to avoid damaging the gate oxide layer in the trench during etching.

[0018] Furthermore, in step five, a second gate polysilicon filling is performed, and a polysilicon layer with a thickness of 100-300 nanometers is filled in the trench using a chemical vapor deposition process. Compared with the first filling, the second deposition temperature is lower (530°C) to reduce crystal stress and optimize the structural morphology after deposition. Multiple fillings of polysilicon can ensure that there are no gaps in the polysilicon layer in the trench and improve the conductivity of the device. Step six, after completing the second polysilicon filling, a chemical mechanical polishing (CMP) process is used to grind the surface of the polysilicon layer to make it flush with the silicon substrate. This step ensures that the polysilicon structure in the trench is flat to avoid uneven electric fields and fluctuations in device performance in subsequent processes. Through precise grinding, the electrical performance and switching speed of the device can be further improved.

[0019] Furthermore, in step seven, after the polysilicon is polished, a thermal oxidation treatment is performed again to grow an oxide layer on the surface of the polysilicon. This oxide layer not only plays a protective role, but also serves as a barrier layer in the subsequent ion implantation process to prevent ions from diffusing into unnecessary areas. The thickness of this oxide layer is usually controlled between 10-50 nanometers to avoid affecting the current transmission path. Step eight, the dopant of the body region (such as boron ions or phosphorus ions) is implanted into the silicon substrate on both sides of the trench through an ion implantation process to form a body region. Subsequently, a high-temperature annealing treatment (usually at 900°C to 1050°C) is performed to activate the implanted dopant and repair the lattice damage caused during the implantation process to ensure that the body region has good conductivity. Step nine, the source region is doped (such as phosphorus ions) through an ion implantation process, and annealing is performed again to ensure that the dopant is evenly distributed and forms a good ohmic contact with the body region. After this step is completed, a complete Trench MOSFET device structure is formed, and the device is ensured to have excellent electrical performance and reliability.

[0020] The above technical solution can achieve the following beneficial effects:

[0021] Compared with the prior art, the present invention has the following advantages and positive effects:

[0022] (1) The present invention reduces the risk of voids in the polysilicon filling process in the traditional process through multiple gate polysilicon deposition and etching processes, avoids the penetration problem in the subsequent etching process, and thus improves the reliability and stability of the device.

[0023] (2) The present invention adopts a multi-film-forming polysilicon gate structure, which optimizes the electric field distribution in the trench, reduces the electric field concentration effect, reduces the on-resistance and leakage current, and thus improves the electrical performance of the Trench MOSFET, especially the stability in high voltage applications.

[0024] (3) The present invention simplifies the manufacturing process, reduces the manufacturing difficulty and cost, and is suitable for large-scale production by optimizing the process flow, such as accurately controlling the thickness and temperature of polysilicon film formation, without adding additional photolithography steps.

[0025] (4) The present invention effectively reduces doping diffusion and crystal defects by controlling the deposition process of the epitaxial layer and the polysilicon layer under different temperature conditions, ensuring that the electrical performance of the device remains stable in the high-temperature process and extending the service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0027] Figure 1 It is a schematic diagram of the Trench MOSFET structure model provided by the present invention.

[0028] Figure 2 It is a manufacturing flow chart of the Trench MOSFET provided by the present invention.

[0029] Figure 3 It is a process flow chart of steps one to three in the Trench MOSFET manufacturing method adopted by the present invention.

[0030] Figure 4 It is a process flow chart of steps four and five in the Trench MOSFET manufacturing method adopted by the present invention.

[0031] Figure 5 It is a process flow chart of steps six and seven in the Trench MOSFET manufacturing method adopted by the present invention.

[0032] Figure 6 It is a process flow chart of steps eight and nine in the Trench MOSFET manufacturing method adopted by the present invention.

[0033] In the figure: (1) silicon substrate, (2) trench, (3) SiO2 protective layer, (4) first layer of polysilicon, (5) oxide layer, (6) second layer of polysilicon, (7) body region (8) source. DETAILED DESCRIPTION

[0034] The present invention is further explained below with reference to the accompanying drawings and specific embodiments.

[0035] The embodiment of the present invention relates to a method for manufacturing a Trench MOSFET with multiple gate polysilicon film formation, such as Figure 1As shown, the Trench MOSFET consists of the following parts: silicon substrate, trench structure, gate oxide layer, gate polysilicon layer, source and body region. The silicon substrate provides basic support, the trench structure contains gate oxide layer and polysilicon gate, forming a complete gate control structure, and the source and body region are formed on both sides of the trench by ion implantation.

[0036] like Figure 2 As shown, the manufacturing process of the Trench MOSFET includes the following steps: First, a trench structure is etched on the silicon substrate 1 as a basis for defining the gate area. Next, a SiO2 layer is grown on the surface of the trench by a thermal oxidation process to ensure the insulation between the gate and the silicon substrate 1. Then, the first filling of the gate polysilicon 3 is performed, and then the excess part is removed by etching to adjust the shape and thickness of the gate. Then, the second polysilicon 5 is filled to optimize the electric field distribution and device performance. After the filling is completed, the gate is flattened by a chemical mechanical polishing (CMP) process to ensure a uniform surface. Next, a protective oxide layer 4 is grown on the surface of the polysilicon by a thermal oxidation process to avoid damage in subsequent processes. Finally, ion implantation of the source 6 and the body region 7 is performed, and lattice defects and activated ions are repaired by an annealing process. This manufacturing process ensures the uniformity of the electric field in the channel through precise polysilicon deposition and etching processes, and improves the electrical performance and stability of the device.

[0037] like Figure 3 As shown, the step 1 first deposits a layer of hard mask material, usually silicon nitride or silicon oxide, on the surface of the silicon substrate 1 to protect the non-etched area. Then, the shape and position of the groove are accurately defined on the hard mask layer through a photolithography process. Then, anisotropic plasma etching technology is used to etch the silicon wafer along the preset groove area to form a groove structure with a depth of 0.5 to 1 micron. During the etching process, the depth of the groove and the smoothness of the sidewall are precisely controlled to ensure the uniformity of the electric field distribution inside the groove and reduce the electric field concentration effect. Finally, the photoresist and impurities remaining after etching are cleaned to ensure that the inner surface of the groove is clean and smooth, so as to prepare for the subsequent growth of the gate oxide layer.

[0038] Step 2: Through a thermal oxidation process, a silicon dioxide (SiO2) protective layer 2 is uniformly formed on the inner wall of the trench to form a gate oxide layer. This process is usually carried out at a high temperature (800°C to 1200°C), using oxygen or water vapor to react with the surface of the silicon wafer to form an oxide layer. The thickness of the gate oxide layer is generally controlled between 30 nanometers and 100 nanometers, and its thickness directly affects the electrical performance of the device, including key parameters such as leakage current and gate capacitance. The purpose of growing the gate oxide layer is to form a high-quality dielectric insulation layer between the silicon wafer and the subsequently deposited gate polysilicon to ensure electrical isolation between the gate and the silicon wafer. This high-quality silicon dioxide layer can effectively increase the switching speed of the MOSFET, reduce the power consumption of the device during operation, and improve its long-term reliability and stability. After the thermal oxidation process is completed, it is necessary to ensure that the surface of the oxide layer is uniform and free of defects to avoid gate leakage or poor insulation problems that may occur in subsequent processes.

[0039] Step three, deposit polysilicon material uniformly in the trench by physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. The filling of polysilicon must not only cover the entire trench, but also ensure that the surface is smooth and free of gaps to form the first layer 3 of the gate. During the deposition process, the thickness and deposition temperature of polysilicon need to be precisely controlled. The deposition temperature of the first layer of polysilicon 3 is usually 580°C, and the filling thickness is usually 2-3 times that of the subsequent second deposition. This thicker initial polysilicon layer helps to improve the conductivity of the gate, thereby improving the conduction performance of the device. After the filling is completed, the polysilicon layer in the trench will be in close contact with the previously grown gate oxide layer 4, forming a complete gate structure foundation, laying the foundation for subsequent etching and refilling steps.

[0040] like Figure 4 As shown, in step four, the polysilicon layer 3 filled for the first time is etched by dry etching technology (such as plasma etching) to remove excess polysilicon and ensure that the shape and thickness of the polysilicon layer in the trench meet the design requirements.

[0041] The etching process requires special attention to the uniformity and precise control of the polysilicon in the trench to avoid over-etching or under-etching. This operation not only accurately defines the height of the gate area, but also optimizes the electric field distribution in the trench and reduces the channel capacitance. After etching, the remaining polysilicon will be flush with the trench surface to form a regular gate structure, providing ideal surface conditions for the subsequent second filling of polysilicon. The core goal of this step is to process the first layer of polysilicon 3 of the gate to an ideal geometry through etching, thereby ensuring that the device can maintain good electrical properties and structural integrity in subsequent processes.

[0042] Step 5 involves the second filling of gate polysilicon. After the polysilicon layer is etched for the first time, the trench has an ideal shape and size. At this time, a second filling of polysilicon 5 is required to further improve the gate structure.

[0043] The second deposition of polysilicon 5 adopts a chemical vapor deposition (CVD) process to fill the remaining part of the trench and ensure the integrity of the gate. This process is carried out at a lower temperature of 530°C, and the thickness of the filled polysilicon is thinner than the first time, about 1 / 2 to 1 / 3 of the first time, so as to optimize the electric field distribution inside the trench and reduce the channel capacitance. The second polysilicon layer 5 and the first deposited polysilicon layer 3 together form a complete gate, thereby ensuring that the gate has good conductivity and control characteristics. By combining the two polysilicon filling and etching processes, this step can effectively improve the performance of the device, especially in high voltage and high temperature environments, ensuring that the Trench MOSFET has better stability and reliability.

[0044] like Figure 5 As shown, in step six, chemical mechanical polishing (CMP) is used to process the gate polysilicon to keep the second filled polysilicon 5 and the silicon wafer surface flat for subsequent process steps.

[0045] Furthermore, during this process, the CMP process will remove excess polysilicon material from the top surface of the groove by a combination of mechanical and chemical methods to ensure that the polysilicon inside the groove is maintained at the required thickness. This grinding process is very precise and can not only ensure the uniformity of the thickness of the gate material, but also reduce the roughness of the groove surface, thereby improving the electric field distribution. The CMP process achieves a fine grinding effect by controlling the grinding time, the chemical properties of the grinding liquid, and the pressure. Its purpose is to form a smooth and flat surface, ensuring that the gate polysilicon in the groove is at the same height as the silicon wafer surface, and providing ideal surface conditions for the subsequent growth and implantation of the oxide layer 4.

[0046] Step seven: Through the thermal oxidation process, the silicon wafer is placed in a high-temperature oxygen or water vapor environment. At a high temperature of 800°C to 1200°C, oxygen atoms react with the surface of the silicon wafer to generate silicon dioxide. The role of this protective layer is to provide additional electrical insulation, especially in the subsequent injection process, to prevent ions from diffusing to areas that should not be affected. At the same time, the thermal oxide film can also improve the physical properties of the surface, further reduce the defect density on the groove surface, and reduce the electric field concentration effect.

[0047] The thickness of the thermal oxide layer 4 is usually tens to hundreds of nanometers, and the specific thickness is adjusted according to the design requirements to ensure that electrical insulation and good thermal stability are maintained during subsequent implantation and annealing. This step prepares for the subsequent ion implantation of the body and source to ensure the excellent performance of the device in electrical performance.

[0048] like Figure 6 As shown, in step eight, dopants (such as phosphorus or boron) are implanted into the silicon epitaxial layer on both sides of the trench by ion implantation technology to form a body region 7. This region controls the switching operation of the device, and the implantation depth and concentration are adjusted by the energy and dose of the ions. Subsequently, a high-temperature annealing treatment (900°C to 1100°C) is performed to repair the damage to the silicon crystal during the implantation process and to activate the doped ions to make them evenly distributed and enhance electrical activity. After this step is completed, the body region has good conductivity, which provides a basis for the subsequent implantation of the source 6.

[0049] Step nine, dopants (such as phosphorus ions) are implanted into the source 6 by ion implantation technology. This area is located at the top of the trench, adjacent to the body region 7, and the implanted doping concentration and depth are precisely controlled to ensure that the source and body regions 7 form a good ohmic contact. After the implantation is completed, a high-temperature annealing process is performed, usually in the temperature range of 900°C to 1050°C, to repair the silicon crystal defects generated during ion implantation and activate the dopants to ensure their good electrical conductivity. After annealing, the source 6 region is formed, and the Trench MOSFET device structure is completed, with ideal electrical performance and switching characteristics.

[0050] The above-mentioned configuration can also be set in other embodiments, and the scope of protection of the present invention includes but is not limited to the situations listed in this embodiment. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention shall be subject to the scope defined by the claims.

[0051] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. The present invention provides a method for manufacturing a trench MOSFET device with multiple gate polysilicon film formation, wherein the device comprises a silicon substrate, a trench structure located on the silicon substrate, a gate oxide layer, and a gate polysilicon layer that is deposited and etched multiple times. A single-crystal silicon epitaxial layer is grown on the silicon substrate to form the active area of ​​the device, and then the silicon substrate is etched to form a groove; the groove has a gate oxide layer located inside the groove, covering the groove surface and in contact with the polysilicon layer to form a complete gate structure; the polysilicon layer is distributed in the groove, and different deposited layers are separated by ion implantation and etching processes to optimize the electric field distribution; the body region and the source electrode are formed on both sides of the groove by ion implantation to form a complete MOSFET structure.

2. The method for manufacturing a Trench MOSFET according to claim 1, characterized in that A single crystal silicon epitaxial layer with a thickness of 1 to 3 microns is grown on the silicon substrate. The single crystal silicon epitaxial layer is used to form the active area of ​​the device and provides better conductivity and low on-resistance; the silicon substrate is a P-type or N-type doped silicon-based material, and its doping concentration is controlled at 1×10 16 atoms / cm 3 Up to 1×10 17 atoms / cm 3 , to ensure the stability of the device under high voltage.

3. The method for manufacturing a Trench MOSFET according to claim 1, characterized in that The groove is formed in the silicon epitaxial layer, and a groove with a depth of 0.5-1 μm is formed by a plasma etching process, and the inner surface of the groove is smooth, so as to reduce the electric field concentration effect in the channel and reduce the leakage current.

4. The method for manufacturing a Trench MOSFET according to claim 1, characterized in that The gate oxide layer is a layer of thermally grown silicon dioxide (SiO2) with a thickness of 30 nanometers to 100 nanometers. It is connected to the first layer of polysilicon through a physical vapor deposition (PVD) process to form an electric field isolation layer to reduce channel capacitance. The gate oxide layer covers the inner wall of the trench and is used to isolate the polysilicon gate from the single crystal silicon epitaxial layer to ensure the electrical insulation between the gate and the substrate and the accuracy of gate control. By thermally oxidizing the gate oxide layer at a high temperature of 800°C to 1200°C, its dielectric properties can be improved, the channel capacitance can be reduced, and the switching speed and stability of the device can be improved.

5. The method for manufacturing a Trench MOSFET according to claim 1, characterized in that The first etching of the gate polysilicon adopts semiconductor dry etching, and the second etching of the polysilicon adopts chemical mechanical grinding to make the filled polysilicon flush with the substrate.

6. The silicon epitaxial layer according to claim 2, characterized in that: The epitaxial layer growth process uses low-pressure chemical vapor deposition (LPCVD) technology to ensure high uniformity and low defect density of the epitaxial layer, thereby improving the reliability of the device. The silicon epitaxial layer has precise thickness control, and the deposition rate and concentration of the reaction gas are adjusted during the epitaxial growth process to ensure the integrity of the epitaxial layer crystal structure and reduce lattice defects. The epitaxial layer also has excellent thermal stability and can maintain its crystal integrity in subsequent high-temperature processes (such as annealing and ion implantation), ensuring excellent electrical properties under various temperature conditions.

7. The groove according to claim 3, characterized in that The steps of forming the groove include: first, depositing a hard mask layer on the surface of the single crystal silicon epitaxial layer, wherein the hard mask layer is silicon nitride or silicon oxide. Then, the hard mask layer is subjected to photolithography to accurately define the groove area. Subsequently, the hard mask layer and the epitaxial layer are etched by an anisotropic dry etching process to form a groove structure with a depth of 0.5 microns to 1 micron. After the etching is completed, a cleaning process is used to remove the residual photoresist and etching products to ensure the smoothness of the groove sidewalls to reduce the electric field concentration effect when the device is working.

8. The gate polysilicon according to claim 5, characterized in that The gate polysilicon is formed by multiple deposition and etching processes, and the polysilicon layer after each deposition is surface passivated by plasma enhanced chemical vapor deposition (PECVD) technology to reduce surface defects and interface state density.

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