ESD protection structure of medium-voltage device
By forming an isolation structure in the drain region of the medium voltage device, it is divided into small areas, and using the high-voltage N-well region structure in the medium voltage P-well region to limit the flow of holes to the substrate, the ESD uniformity of the medium voltage device is solved The poor problem achieves higher coupling and rapid protection capabilities.
Patent Information
- Application Number
- CN202411525145.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
The ESD uniformity of existing medium-voltage devices is poor, resulting in preferential opening of the center finger in ESD test, and multiple folding phenomena exist, making it difficult to open other fingers, and the device works in the collapsed area of the drain junction every time. Facilitate rapid protection.
By forming an isolation structure in the drain region, the drain region is divided into small areas, and the medium-voltage P-well region is used to form it in the high-voltage N-well region to limit the flow of holes to the substrate, achieving higher coupling between different small regions and promoting uniformity and small current trigger.
It improves the rapid protection capability of the ESD protection structure, realizes the uniformity of the device and small current triggering, enhances the uniformity of the ESD and avoids the increase in process costs.
Smart Images
Figure CN119403232A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an ESD protection structure for a medium voltage device. Background Art
[0002] OLED is a current-driven type, and its current density depends on the driving voltage at both ends. The higher the voltage, the greater the current density. During long-term use, the OLED device itself will age, and the relationship between voltage, current density, and luminous brightness will not always remain constant. The most direct manifestation of OLED device aging is the increase in OLED turn-on voltage and the decrease in luminous efficiency. In order to maintain the same luminous brightness, the OLED current flowing through must be increased, so high-voltage devices are required in OLED to achieve high current functions. In 28HV MG technology, it is necessary to integrate low-voltage SRAM and high-voltage driver devices, and the gate of the high-voltage driver device requires thick gate oxide, and the thick gate oxide layer will affect the subsequent process of the metal gate. In order to be compatible with the metal gate technology, the high-voltage area (HV) will be etched back (Recess) of the active area, and then thick gate oxide will be grown to make it as consistent as possible with the height of the active area to facilitate subsequent process development.
[0003] The medium voltage device (MV 8.0V) of 28nm process uses a field area double diffusion process structure. The source and drain in the structure are both conventional active areas. When used as an ESD device, the 28HV MV device has a large size and the base resistance of the parasitic BJT of the center finger is the largest. Therefore, in the ESD test, the center finger is always turned on first. Once the center finger is turned on, the ESD voltage will turn to the return voltage (snapback voltage), resulting in a large number of multiple foldbacks. If the second trigger voltage (Vtriggr2) is less than the first trigger voltage (Vtrigger1), the other fingers will not be able to turn on. At the same time, due to the small substrate current, a high current is required to achieve conduction, so that the ESD device works in the collapse area of the drain junction every time, which is not conducive to the rapid protection of the ESD device. In response to this problem, the current solution proposed is to use the segmented active area to disperse the current to improve the uniform conduction of the device, and to divide the active area (such as Figure 1 As shown in the figure, the coupling between the active area and the adjacent active area is used to achieve better uniform conduction. However, when the distance between the active areas is far (that is, when Dx and Sx are large in the figure), effective substrate coupling cannot be formed to open more active areas, and the hole current in the open active area is drawn away by the substrate at a faster speed. In this structure, the substrate coupling effect caused by the increased distance between the active areas is low, or even no improvement, resulting in poor practical usability. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an ESD protection structure for a medium voltage device, so as to solve the problem of poor ESD uniformity of the existing medium voltage device.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides an ESD protection structure for a medium voltage device, the structure comprising:
[0006] A substrate having a high-voltage N-well region formed therein;
[0007] A medium voltage P-well region, wherein the medium voltage P-well region is formed in the high voltage N-well region;
[0008] at least two gate structures, wherein the gate structures are formed on the surface of the substrate;
[0009] A drain region, wherein the drain region is formed in the medium voltage P-well region and is located between two adjacent gate structures;
[0010] A source region, the source region is formed in the medium voltage P-well region and is located on a side of each gate structure away from the drain region;
[0011] The drain region is divided into small regions by at least one isolation structure extending along the length direction of the drain region, and the isolation structure is located between two adjacent gate structures.
[0012] Optionally, the length of the isolation structure ranges from 0.5um to 1.2um, and the width ranges from 0.07 to 0.11um, wherein the length direction of the isolation structure is the length direction of the drain region, and the width direction is the width direction of the drain region.
[0013] Optionally, the isolation structure is formed by forming a trench in the substrate and filling the trench with silicon oxide.
[0014] Optionally, the depth of the trench is greater than the ion implantation depth of the drain region.
[0015] Optionally, the depth of the groove ranges from 180 nm to 220 nm.
[0016] Optionally, there are multiple isolation structures, and the multiple isolation structures are arranged at intervals along the width direction of the drain region.
[0017] Optionally, the drain region and the source region are N-type doped.
[0018] Optionally, the structure further includes a P-type guard ring, and the P-type guard ring is formed in the medium-voltage P-well and surrounds the source region, the drain region and the periphery of the region where the gate structure is located.
[0019] Optionally, the structure further includes a shallow trench isolation structure, wherein the shallow trench isolation structure is formed between the P-type guard ring and the source region, and is formed on a side of the P-type guard ring away from the source region.
[0020] Optionally, the gate structure includes a gate dielectric layer, a metal gate and a sidewall, and the gate dielectric layer is formed between the metal gate and the substrate, and the sidewall is formed on the sidewall of the metal gate.
[0021] Optionally, the structure further includes a refractory silicide barrier layer, wherein the refractory silicide barrier layer is formed on the surface of the substrate between the gate structure and the drain region and the isolation structure.
[0022] Optionally, the substrate is a P substrate.
[0023] Optionally, the drain region serves as an electrostatic discharge region and is connected to an electrostatic discharge voltage, and the P-type guard ring, the source region, and the gate structure are all connected to a common ground terminal.
[0024] As described above, the medium voltage device ESD protection structure of the present invention forms an isolation structure in the drain area to divide the drain area into small areas, which is beneficial to the movement of generated holes between different small areas; and because the medium voltage P-well area is formed in the high voltage N-well area, it can prevent the generated holes from being quickly extracted by the substrate, thereby achieving higher coupling between different small areas, which is beneficial to achieving uniform conduction and small current triggering of the device, thereby improving the rapid protection capability of the ESD protection structure; moreover, the ESD protection structure proposed by the present invention is compatible with existing processes, there is no need for new process development, no need for new mask templates, and can avoid an increase in process costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It shows a top view schematic diagram of a conventional device with divided active regions and a cross-sectional structural schematic diagram of the device cut along lines AA', BB', CC' and DD'.
[0026] Figure 2 Shown is a top view schematic diagram of the medium voltage device ESD protection structure of the present invention.
[0027] Figure 3 Display as Figure 2 The cross-sectional structure diagram of the medium voltage device ESD protection structure cut along the AA' direction is shown.
[0028] Figure 4 Display as Figure 2 The cross-sectional structure diagram of the medium voltage device ESD protection structure cut along the BB' direction is shown.
[0029] Figure 5 Display as Figure 2 The cross-sectional structure diagram of the medium voltage device ESD protection structure cut along the CC' direction is shown.
[0030] Description of Figure Numbers
[0031] 10: substrate; 20: high-voltage N-well region; 30: medium-voltage P-well region; 40: gate structure; 41: gate dielectric layer; 42: metal gate; 43: sidewall; 51: drain region; 52: source region; 60: isolation structure; 70: P-type guard ring; 80: shallow trench isolation structure; 90: refractory silicide barrier layer; 100: contact hole DETAILED DESCRIPTION
[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0033] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0034] like Figure 2 to Figure 5 As shown, this embodiment provides an ESD protection structure for a medium voltage device, the structure comprising:
[0035] A substrate 10, wherein a high-voltage N-well region 20 is formed in the substrate 10;
[0036] A medium voltage P-well region 30, wherein the medium voltage P-well region 30 is formed in the high voltage N-well region 20;
[0037] At least two gate structures 40, wherein the gate structures 40 are formed on the surface of the substrate 10;
[0038] A drain region 51, wherein the drain region 51 is formed in the medium voltage P-well region 30 and is located between two adjacent gate structures 40;
[0039] A source region 52 , wherein the source region 52 is formed in the medium voltage P-well region 30 and is located on a side of each gate structure 40 away from the drain region 51 ;
[0040] The drain region 51 is divided into small regions by at least one isolation structure 60 extending along the length direction thereof, and the isolation structure 60 is located between two adjacent gate structures 40 .
[0041] like Figure 2 As shown, in this embodiment, the length direction of the drain region 51 is the direction of the dotted line AA' (or CC'), and the width direction of the drain region 51 is the direction of the dotted line BB'. In this embodiment, the drain region 51 is divided into small areas by using an isolation structure 60, which can facilitate the movement of holes and increase the coupling between different small areas. In addition, the medium-voltage P-well region 30 is formed in the high-voltage N-well region 20, which can limit the generated avalanche holes from flowing to the substrate 10, thereby promoting the coupling between different small areas.
[0042] Specifically, the substrate 10 is a P substrate.
[0043] Specifically, the gate structure 40 includes a gate dielectric layer 41 , a metal gate 42 and a sidewall spacer 43 , wherein the gate dielectric layer 41 is formed between the metal gate 42 and the substrate 10 , and the sidewall spacer 43 is formed on the sidewall of the metal gate 42 .
[0044] like Figure 3 As shown, in this embodiment, the gate dielectric layer 41 includes silicon oxide or a high-K dielectric layer.
[0045] Specifically, the drain region 51 and the source region 52 are N-type doped.
[0046] Specifically, the length of the isolation structure 60 ranges from 0.5um to 1.2um, and the width ranges from 0.07 to 0.11um, wherein the length direction of the isolation structure 60 is the length direction of the drain region 51 , and the width direction is the width direction of the drain region 51 .
[0047] Specifically, the isolation structure 60 is formed by forming a trench in the substrate 10 and filling the trench with silicon oxide.
[0048] Specifically, the depth of the trench is greater than the ion implantation depth of the drain region 51 .
[0049] Specifically, the depth of the groove ranges from 180 nm to 220 nm.
[0050] Specifically, there are a plurality of isolation structures 60 , and the plurality of isolation structures 60 are arranged at intervals along the width direction of the drain region 51 .
[0051] Specifically, the structure further includes a P-type guard ring 70 , and the P-type guard ring 70 is formed in the medium-voltage P-well and surrounds the source region 52 , the drain region 51 and the periphery of the region where the gate structure 40 is located.
[0052] Specifically, the structure further includes a shallow trench isolation structure 60 , and the shallow trench isolation structure 60 is formed between the P-type guard ring 70 and the source region 52 , and is formed on a side of the P-type guard ring 70 away from the source region 52 .
[0053] Specifically, the structure further includes a refractory silicide barrier layer 90 , which is formed on the surface of the substrate 10 between the gate structure 40 and the drain region 51 and the isolation structure 60 .
[0054] Specifically, the drain region 51 is used as an electrostatic discharge region and is connected to an electrostatic discharge voltage, and the P-type guard ring 70 , the source region 52 , and the gate structure 40 are all connected to a common ground terminal.
[0055] In this embodiment, the P-type guard ring, the source region, and the gate structure are connected to a common ground terminal through a contact hole 100 , and a pad PAD is formed on the drain region 51 .
[0056] In summary, the medium voltage device ESD protection structure of the present invention forms an isolation structure in the drain area to divide the drain area into small areas, which is conducive to the movement of generated holes between different small areas; and because the medium voltage P well area is formed in the high voltage N well area, it can prevent the generated holes from being quickly drawn away by the substrate, and achieve higher coupling between different small areas, so as to facilitate the uniform conduction and small current triggering of the device, thereby improving the rapid protection capability of the ESD protection structure; moreover, the ESD protection structure proposed by the present invention is compatible with the existing process, there is no need for new process development, no need for new mask templates, and can avoid the increase of process costs. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0057] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A medium voltage device ESD protection structure, characterized in that: The structure comprises: A substrate having a high-voltage N-well region formed therein; A medium voltage P-well region, wherein the medium voltage P-well region is formed in the high voltage N-well region; at least two gate structures, wherein the gate structures are formed on the surface of the substrate; A drain region, wherein the drain region is formed in the medium voltage P-well region and is located between two adjacent gate structures; A source region, the source region is formed in the medium voltage P-well region and is located on a side of each gate structure away from the drain region; The drain region is divided into small regions by at least one isolation structure extending along the length direction of the drain region, and the isolation structure is located between two adjacent gate structures.
2. The medium voltage device ESD protection structure according to claim 1, characterized in that: The length of the isolation structure ranges from 0.5um to 1.2um, and the width ranges from 0.07um to 0.11um, wherein the length direction of the isolation structure is the length direction of the drain region, and the width direction is the width direction of the drain region.
3. The medium voltage device ESD protection structure according to claim 1, characterized in that: The isolation structure is formed by forming a trench in the substrate and filling the trench with silicon oxide.
4. The medium voltage device ESD protection structure according to claim 3, characterized in that: The depth of the trench is greater than the ion implantation depth of the drain region.
5. The medium voltage device ESD protection structure according to claim 4, characterized in that: The depth of the groove ranges from 180 nm to 220 nm.
6. The medium voltage device ESD protection structure according to claim 1, characterized in that: There are multiple isolation structures, and the multiple isolation structures are arranged at intervals along the width direction of the drain region.
7. The medium voltage device ESD protection structure according to claim 1, characterized in that: The drain region and the source region are N-type doped.
8. The medium voltage device ESD protection structure according to claim 1, characterized in that: The structure further includes a P-type protection ring, and the P-type protection ring is formed in the medium-voltage P-well and surrounds the periphery of the source region, the drain region and the region where the gate structure is located.
9. The medium voltage device ESD protection structure according to claim 8, characterized in that: The structure further includes a shallow trench isolation structure, which is formed between the P-type guard ring and the source region, and is formed on a side of the P-type guard ring away from the source region.
10. The medium voltage device ESD protection structure according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a metal gate and a sidewall, wherein the gate dielectric layer is formed between the metal gate and the substrate, and the sidewall is formed on the sidewall of the metal gate.
11. The medium voltage device ESD protection structure according to claim 1, characterized in that: The structure further includes a refractory silicide barrier layer formed on a surface of the substrate between the gate structure and the drain region and the isolation structure.
12. The medium voltage device ESD protection structure according to claim 1, characterized in that: The substrate is a P substrate.
13. The medium voltage device ESD protection structure according to claim 8, characterized in that: The drain region serves as an electrostatic discharge region and is connected to an electrostatic discharge voltage. The P-type guard ring, the source region, and the gate structure are all connected to a common ground terminal.