Display device

Abstract

A display device includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each sub-pixel, the thin film transistor including a gate electrode, a source electrode, and a drain electrode; first and second intermediate layers sequentially on the thin film transistor; a light emitting element on the second intermediate layer, connected to the thin film transistor and including a first driving electrode, an electroluminescent layer, and a second driving electrode; a lower connection line in the non-display area; a bank layer on the lower connecting line; a power line connected to the second driving electrode through a lower connection line; at least two weirs on the power line, each including a first intermediate layer, a second intermediate layer, a bank layer, and a spacer, and the first and second intermediate layers of the at least two weirs being separated from the first and second intermediate layers in the display area; a fracture detector surrounding the at least two weirs in the non-display area; and an encapsulation layer on the light emitting element, including first, second, and third encapsulation layers.

Description

[0001] This application is a divisional application of the invention patent application with application date of December 25, 2020, application number 202011563550.6, and invention name “Display Device”. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device in which electrode disconnection defects generated in a non-display area are reduced. Background Art

[0003] An image display device that realizes various information on the screen is a core technology in the information communication era. Such image display devices are developing to be thinner, lighter and more portable, and to have high performance. Therefore, a display device that can be manufactured in a thin and light form has attracted attention. Since the display device is a self-luminous device, the display device is not only advantageous in terms of power consumption due to low voltage driving, but also has a high-speed response speed, high luminous efficiency, wide viewing angle and excellent contrast, and is therefore being studied as a next-generation display. The display device realizes an image by arranging a plurality of sub-pixels in a matrix form. Each of the plurality of sub-pixels includes a light-emitting element and a plurality of transistors that independently drive the light-emitting element.

[0004] Specific examples of the display device include a liquid crystal display (LCD) device, a quantum dot (QD) display device, a field emission display (FED) device, and an organic light emitting diode (OLED) display device.

[0005] Among these display devices, OLED display devices, which do not require a separate light source and have attracted attention as compact devices and clear color displays, have advantages such as fast response speed, high contrast, high luminous efficiency, high brightness, and a wide viewing angle by using self-luminous OLEDs.

[0006] The OLED display device includes an organic light-emitting element that is driven individually for each sub-pixel, and each organic light-emitting element includes: a first driving electrode; a second driving electrode; and multiple organic layers between the first driving electrode and the second driving electrode, such as a hole injection layer, a hole transport layer, an organic light-emitting layer, and an electron transport layer.

[0007] Since the organic light-emitting element includes a common layer commonly provided for each sub-pixel, in order to prevent leakage current from flowing to the side through the common layer, a bank etch layer is additionally provided at the upper end of the positive electrode, thereby causing a portion of the common layer to be disconnected, thereby blocking the leakage current generated on the side between the sub-pixels.

[0008] However, there is a problem that the second driving electrode is easily disconnected due to the bank etching layer provided for the purpose of disconnecting some of the common layers. Unlike the display area where a plurality of other common layers exist, since there is no common layer in the non-display area of ​​the peripheral portion, the disconnection of the second driving electrode may cause a connection defect with the lower connection line through which the power supply voltage in the power supply line is supplied to the second driving electrode. Summary of the invention

[0009] Accordingly, the present invention is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0010] An object of the present invention is to provide a display device, wherein a second driving electrode is connected to a lower connecting line at least once in a non-display area, and in particular, dam holes are densely formed in the non-display area so that a lower etching rate is applied according to a microscopic loading effect compared to a display area, thereby reducing defects caused by disconnection of the second driving electrode.

[0011] Additional features and advantages of the present invention will be described in the following description, some of which will be apparent from the description or can be understood through the practice of the present invention. These and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification, claims and drawings.

[0012] To achieve these and other advantages and in accordance with the intent of the present invention, as embodied and broadly described herein, a display device includes: a substrate having a display area and a non-display area; a lower connecting line arranged in the non-display area; a dam layer, the dam layer being arranged on the lower connecting line and having an undercut structure at the edge of the lower end of the dam layer; a dam etching layer, the dam etching layer being arranged between the lower connecting line and the dam layer and having an edge inside the edge of the lower end of the dam layer; and a second driving electrode, the second driving electrode being arranged on the dam layer and electrically connected to the lower connecting line at least once, wherein a plurality of dam holes are formed in the dam layer.

[0013] In another aspect, a display device includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a first driving electrode arranged for each sub-pixel; a lower connecting line, the lower connecting line being made of the same material as the first driving electrode and arranged in the non-display area; a dam layer, the dam layer being arranged on the first driving electrode and the lower connecting line and having an undercut structure at an edge of the dam layer adjacent to the lower connecting line; a second driving electrode, the second driving electrode being arranged on the dam layer, separated from the first driving electrode and electrically connected to the lower connecting line at least once; and a dam etching layer, the dam etching layer being arranged so that an upper surface of the dam etching layer is covered by the dam layer, wherein the second driving electrode is in contact with a side of the dam layer.

[0014] In another aspect, a display device includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor including a gate electrode, a source electrode and a drain electrode; a first intermediate layer and a second intermediate layer sequentially located on the thin film transistor; a light-emitting element on the second intermediate layer, the light-emitting element being connected to the thin film transistor and including a first driving electrode, an electroluminescent layer and a second driving electrode; a lower connecting line in the non-display area; a dam layer on the lower connecting line; a power line connected to the second driving electrode through the lower connecting line, the power line having a phase relationship with one of the gate electrode, the source electrode and the drain electrode. the same material as the gate electrode, the source electrode and the drain electrode; at least two dams on the power line, each of the at least two dams including the first intermediate layer, the second intermediate layer, the bank layer and the spacer, and the first intermediate layer and the second intermediate layer of the at least two dams are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector surrounding the at least two dams in the non-display area, the rupture detector including the same material as one of the gate electrode, the source electrode and the drain electrode; and an encapsulation layer on the light emitting element, the encapsulation layer including a first encapsulation layer, a second encapsulation layer and a third encapsulation layer, an end of the first encapsulation layer being arranged to be farther away from the display area than an end of the second encapsulation layer, the first encapsulation layer overlapping the rupture detector.

[0015] In another aspect, a display device includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor including a gate electrode, a source electrode, and a drain electrode; a first intermediate layer and a second intermediate layer sequentially located on the thin film transistor; a light-emitting element on the second intermediate layer, the light-emitting element being connected to the thin film transistor and including a first driving electrode, an electroluminescent layer, and a second driving electrode; a lower connecting line in the non-display area; a bank layer on the lower connecting line, the bank layer having a plurality of bank holes in the non-display area; a power line connected to the second driving electrode through the lower connecting line, the power line having the same material as one of the gate electrode, the source electrode and the drain electrode; at least two dams on the power line, each of the at least two dams comprising the first intermediate layer, the second intermediate layer, the bank layer and the spacer, and the first intermediate layer and the second intermediate layer of the at least two dams are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector surrounding the at least two dams in the non-display area, the rupture detector comprising the same material as one of the gate electrode, the source electrode and the drain electrode; and an encapsulation layer on the light-emitting element, the encapsulation layer comprising a first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer overlapping the rupture detector.

[0016] In another aspect, a display device includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor including a gate electrode, a source electrode and a drain electrode; a first intermediate layer and a second intermediate layer sequentially located on the thin film transistor; a light-emitting element on the second intermediate layer, the light-emitting element being connected to the thin film transistor and including a first driving electrode, an electroluminescent layer and a second driving electrode; a lower connecting line in the non-display area; a dam layer on the lower connecting line, the dam layer having a plurality of dam holes in the non-display area; a power line connected to the second driving electrode through the lower connecting line, the A power line having the same material as one of the gate electrode, the source electrode and the drain electrode; at least two dams on the power line, each of the at least two dams including the first intermediate layer, the second intermediate layer, the bank layer and the spacer, and the first intermediate layer and the second intermediate layer of the at least two dams are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector located at the outermost part of the non-display area to surround the at least two dams and the power line, the rupture detector including the same material as one of the gate electrode, the source electrode and the drain electrode; and an encapsulation layer on the light-emitting element, the encapsulation layer including a first encapsulation layer, a second encapsulation layer and a third encapsulation layer.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this application, illustrate embodiments of the present invention and together with the description serve to explain the principle of the present invention. In the drawings:

[0019] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0020] Figure 2A and Figure 2B is a diagram for describing formation of a bank layer of a display device according to an embodiment of the present invention.

[0021] Figure 2C is a cross-sectional view of a pixel in a display area of ​​a display device according to an embodiment of the present invention.

[0022] Figure 2D is a plan view of a non-display area of ​​a display device according to an embodiment of the present invention.

[0023] Figure 3 is a cross-sectional view illustrating a display region in a display device according to an embodiment of the present invention.

[0024] Figure 4 is a cross-sectional view illustrating a non-display region of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing examples of the present invention are merely examples, and thus, the present invention is not limited to the details shown in the drawings. Similar reference numerals generally represent similar elements throughout the present invention. In the description of examples of the present invention, when it is determined that a detailed description of a related known function or structure would unnecessarily obscure the key points of the present invention, its detailed description will be omitted.

[0026] When the terms "including", "having" and "comprising" are used to describe the present invention, other components may be added unless these terms are used together with the term "only".

[0027] Even if not expressly stated, the components are construed as including ordinary error ranges.

[0028] In describing a positional relationship, for example, when the positional relationship between two parts is described as “on” and “over,” one or more other parts may be disposed between the two parts unless the term “directly” is used.

[0029] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuity may be included unless the term "directly" or "directly" is used.

[0030] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, within the technical concept of the present invention, the first component described below may be the second component.

[0031] The wording "at least one" should be understood to include any one of the relevant listed items and all combinations of one or more. For example, the meaning of "at least one of the first item, the second item, and the third item" means the combination of all items selected from the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0032] The features of each example of the present invention may be combined or combined with each other in part or in whole, and may be technically interoperable and driven with each other in various ways. These examples may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0033] Hereinafter, an example of a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When adding reference marks to the elements in each figure, it should be noted that similar reference marks that have been used to represent similar elements in other drawings should be used for the elements as much as possible. For the convenience of description, the proportions of the components shown in the drawings are different from the actual proportions, so the present invention is not limited to the proportions shown in the drawings.

[0034] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0035] Reference Figure 1 , the display device 1000 may include a substrate 100 , a data driver 200 , a gate driver 300 , a power line 400 , and a crack preventing part 500 .

[0036] The substrate 100 may include a display area AA and a non-display area NA surrounding the display area AA. The display area AA may be an area where an image is actually displayed on the display device 1000, and a light emitting element and various driving elements for driving the light emitting element may be disposed in the display area AA. The non-display area NA may be an area where an image is not displayed and may be an area surrounding the display area AA. Various components for driving a plurality of pixels disposed in the display area AA may be disposed in the non-display area NA. For example, Figure 1 As shown in FIG. 1 , various signal lines such as a gate line GL and a data line DL, a gate driver 300 , a power line 400 , etc. may be disposed in the non-display area NA of the substrate 100 .

[0037] In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels are arranged in a matrix form to display an image. Therefore, there are a plurality of sub-pixel lines, and the sub-pixel lines may be sub-pixel rows or sub-pixel columns. Hereinafter, the sub-pixel rows are described as sub-pixel lines. Each sub-pixel SP includes a thin film transistor operating as a pixel driving circuit, and a light emitting element connected to the thin film transistor.

[0038] The sub-pixel SP is formed as a top emission type, a bottom emission type, or a double-sided emission type according to its structure. The sub-pixel SP includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel or includes a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The sub-pixel SP may have one or more different emission areas according to emission characteristics.

[0039] The controller (not shown) provides various control signals to the data driver 200 and the gate driver 300 to control the data driver 200 and the gate driver 300 .

[0040] The controller starts scanning according to the timing implemented in each frame, converts image data input from an external source into a data signal format used by the data driver 200, outputs the converted image data, and controls data driving at an appropriate time according to the scanning.

[0041] In the display device according to the embodiment of the present invention, the controller may be separately formed outside the substrate or may be integrally formed with the data driver 200 .

[0042] The data driver 200 supplies data voltages to the plurality of data lines DL to drive the plurality of data lines DL. Here, the data driver 200 is also referred to as a source driver.

[0043] The gate driver 300 sequentially supplies scan signals to the plurality of gate lines GL to sequentially drive the plurality of gate lines GL. Here, the gate driver 300 is also referred to as a scan driver.

[0044] The gate driver 300 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals having an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller.

[0045] The gate driver 300 may be Figure 1 , or in some cases may be disposed on both sides of the substrate 100 according to a driving method or a panel design method. In addition, the gate driver 300 may include one or more gate driver integrated circuits (GDICs) or may be implemented in the substrate 100 in a gate-in-panel (GIP) type, thereby being directly disposed on the substrate 100, but the present invention is not limited thereto.

[0046] When a specific gate line is activated, the data driver 200 converts image data received from the controller into a data voltage Vdata having an analog form and supplies the converted data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL.

[0047] The data driver 200 may include one or more source driver integrated circuits (SDICs) to drive the plurality of data lines DL.

[0048] Each of the above-mentioned GDIC or SDIC may be connected to a bonding pad of the substrate 100 by a tape automated bonding (TAB) method or a chip on glass (COG) method, may be directly disposed on the substrate 100, or may be disposed to be integrated into the substrate 100 in some cases.

[0049] Each SDIC may include: a logic unit including a shift register, a latch circuit, etc.; a digital-to-analog converter (DAC); an output buffer, etc. In some cases, a sensing compensator for sensing characteristics of a sub-pixel may be provided to compensate for the characteristics of the sub-pixel (e.g., a threshold voltage and mobility of a transistor, a threshold voltage of an organic light emitting diode, and brightness of a sub-pixel).

[0050] In addition, each SDIC may be implemented by a chip on film (COF) method. In this case, one end of each SDIC is bonded to at least one source printed circuit board, and the other end thereof is bonded to the substrate 100.

[0051] Meanwhile, the controller receives input image data and various control signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE), and a clock signal (CLK) from an external source (eg, a host system).

[0052] The controller not only converts image data input from an external source into a data signal format used in the data driver 200 to output the converted image data, but also receives various timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE), and a clock signal, and generates and outputs various control signals to the data driver 200 and the gate driver 300.

[0053] For example, the controller outputs various gate control signals (GCS) including a gate start pulse (GSP), a gate shift clock (GSC) signal, a gate output enable (GOE) signal, etc., in order to control the gate driver 300 .

[0054] Here, the GSP controls the operation start timing of one or more GDICs constituting the gate driver 300. The GSC signal is a clock signal commonly input to one or more GDICs and controls the shift timing of a scan signal (gate pulse). The GOE signal specifies the timing information of one or more GDICs.

[0055] In addition, the controller outputs various data control signals (DCS) including a source start pulse (SSP), a source sampling clock (SSC) signal, a source output enable (SOE) signal, etc., in order to control the data driver 200 .

[0056] Here, the SSP controls the data sampling start timing of one or more SDICs constituting the data driver 200. The SSC signal is a clock signal for controlling the data sampling timing of each SDIC. The SOE signal controls the output timing of the data driver 200.

[0057] The power line 400 is connected to the second driving electrode 149 (see Figure 2C ) is electrically connected to supply power. In this case, the supplied power may be provided as a common voltage. Figure 1 As shown in FIG, the power line 400 is formed outside the display area AA and the gate driver 300 and is arranged to surround the display area AA and the gate driver 300. The power line 400 may be made of the same material as the source electrode and the drain electrode of the thin film transistor. However, the present invention is not limited thereto, and the power line 400 may be made of the same material as the gate electrode of the thin film transistor.

[0058] The crack preventing portion 500 is formed at the outermost portion of the non-display area NA and is disposed to surround the display area AA and the gate driver 300. The crack preventing portion 500 may detect damage to the substrate 100, etc. The crack preventing portion 500 may be made of the same material as the gate electrode of the thin film transistor. However, the present invention is not limited thereto, and the crack preventing portion 500 may be made of the same material as the source electrode and the drain electrode of the thin film transistor.

[0059] Figure 2A and Figure 2B is a diagram for describing formation of a bank layer of a display device according to an embodiment of the present invention.

[0060] Figure 2A and Figure 2B is a diagram for describing the principle of reducing damage to the active layer caused by the conductive pattern on the substrate 100 according to an embodiment of the present invention. For example, Figure 2A is a diagram used to describe the principle due to the microscopic loading effect. Figure 2B is a diagram for describing the principle due to the aspect ratio dependent etch rate (ARDE) effect.

[0061] The micro loading effect refers to a phenomenon in which the etching rate of a region where the pattern is relatively dense is reduced compared to a region where the pattern is relatively less dense. For example, when the same etching process is performed, etching can be performed to a shallower depth due to a low etching rate in a region where the pattern is relatively dense, and etching can be performed to a deeper depth due to a high etching rate in a region where the pattern is relatively less dense.

[0062] Regarding this, see Figure 2A The bank layer 117 or the bank etch layer 141 may be etched according to the patterns PTA and PTB of the photoresist PR coated on the material layer ML (see Figure 2C ). In this case, due to a micro loading effect, the etching rates of the patterns PTA and PTB may be different according to the density of the patterns PTA and PTB.

[0063] Specifically, refer to Figure 2AAs the pattern PTA becomes denser, the etching rate decreases; on the contrary, when the pattern PTB is set alone, the etching rate increases, so that the depth d2 of the pattern PTB in the second pattern area A2 where the pattern PTB is relatively less dense can be greater than the depth d1 of the pattern PTA in the first pattern area A1 where the pattern PTA is denser.

[0064] Next, the ARDE effect refers to a phenomenon in which the etching rate decreases during etching as the aspect ratio (depth / width) of the pattern increases. For example, when the same etching process is performed, as the width increases, the aspect ratio decreases, so the etching rate increases, so that a deeper pattern can be formed.

[0065] Regarding this, see Figure 2B , the bank layer 117 or the bank etching layer 141 may be etched according to the patterns PT1, PT2, PT3, and PT4 coated with the photoresist PR. In this case, due to the ARDE effect, the etching rate may be different according to the aspect ratio of the patterns PT1, PT2, PT3, and PT4.

[0066] Specifically, before etching patterns PT1, PT2, PT3 and PT4, the aspect ratios of patterns PT1, PT2, PT3 and PT4 are zero, and as etching proceeds, the aspect ratios gradually increase. Therefore, over time, the etching rates of all patterns PT1, PT2, PT3 and PT4 gradually decrease, but the degree of reduction in the etching rate may vary depending on their widths.

[0067] For example, assuming that the width W4 of the first pattern PT1 is the widest, and the width becomes narrower in the order of the second pattern PT2, the third pattern PT3, and the fourth pattern PT4, immediately after the etching process starts, since the aspect ratios of the first pattern PT1 to the fourth pattern PT4 are the same, that is, zero, their etching rates may also be the same. In this case, the time taken until the width W and the depth d become the same as each other so that the aspect ratio becomes one may be the longest in the first pattern PT1 having the widest width, and may be the shortest in the fourth pattern PT4 having the narrowest width.

[0068] Therefore, the etching rate of the first pattern PT1 having the slowest increase in aspect ratio may be relatively slowest reduced, and the etching rate of the fourth pattern PT4 having the fastest increase in aspect ratio may be fastest reduced.

[0069] Therefore, as the width of the patterns PT1, PT2, PT3, and PT4 to be etched increases, their aspect ratios may slowly increase, and thus their etching rates may slowly decrease. For example, as the width of the patterns increases, the depth of etching may also increase. Therefore, as Figure 2BAs shown in , when etching is performed for the same time, the depth d1 of the first pattern PT1, the depth d2 of the second pattern PT2, the depth d3 of the third pattern PT3, and the depth d4 of the fourth pattern PT4 may decrease in sequence.

[0070] Figure 2C is a cross-sectional view of a pixel in a display area of ​​a display device according to an embodiment of the present invention. For example, Figure 2C is a cross-sectional view of a pixel designed using a microscopic loading effect in a display region of a display device according to an embodiment of the present invention.

[0071] Reference Figure 2C , the first driving electrode 143 and the bank etching layer 141 having an inorganic insulating film component are sequentially deposited on the substrate 100, and then the bank etching layer 141 and the first driving electrode 143 are selectively removed and separated corresponding to the region of each sub-pixel SP, thereby forming the first driving electrode 143. In this process, the bank etching layer 141 on the first driving electrode 143 remains to have the same or similar width as the first driving electrode 143.

[0072] Next, a bank layer 117 having an organic layer component is coated on the stacked first driving electrode 143 and the bank etch layer 141, and then the bank layer 117 is selectively removed to form the bank layer 117. The bank layer 117 may be made of a material having an etching rate different from that of the bank etch layer 141. When the bank layer 117 is selectively removed, an etchant having a higher etching rate may be used for the bank etch layer 141 compared to the bank layer 117, and in the etching process, the bank etch layer 141 formed outside the bank layer 117 is completely removed according to the micro loading effect and the ARDE effect, and only the bank etch layer 141 formed within the width of the lower end portion of the bank layer 117 remains. Subsequently, the bank layer 117 may be solidified by sintering the bank layer 117.

[0073] The bank opening 117O in which the bank layer 117 is not formed in the display area AA (see Figure 3 ) may vary according to the element characteristics of each sub-pixel SP and the efficiency of each color. For example, since the blue sub-pixel SP has low efficiency, the width of the bank opening 117O in the blue sub-pixel SP may be the largest, and the width of the bank opening 117O in the green sub-pixel SP or the red sub-pixel SP having high efficiency may be relatively small.

[0074] In the display device according to the present invention, since the bank layer 117 is formed due to the difference in etching rates between the bank layer 117 and the bank etch layer 141 , a separate mask process may not be added to form the bank etch layer 141 .

[0075] Figure 2Dis a plan view of a non-display area of ​​a display device according to an embodiment of the present invention. For example, Figure 2D 1 is a plan view of a bank layer 117 and a bank hole 117H formed using a micro loading effect in a non-display region of a display device according to an embodiment of the present invention.

[0076] A plurality of patterned bank holes 117H may be formed by coating the non-display area NA with a photoresist PR. The plurality of bank holes 117H formed in the non-display area NA may be formed more densely than the bank opening 117O in the display area AA in which the bank layer 117 is not formed. The height s1 and the width s1 of the bank holes 117H are the same, and the bank holes 117H may be formed to be smaller than the bank opening 117O in the display area AA in which the bank layer 117 is not formed, by 1 / 3 to 1 / 5 of the size thereof. In addition, the interval s2 between the plurality of bank holes 117H may also be formed to be smaller than the interval between the bank layers 117 of the display area AA, by 1 / 3 to 1 / 5 of the size thereof.

[0077] Since the widths of the plurality of bank holes 117H and the intervals between the bank holes 117H are formed to be smaller than those in the display area AA, the bank etching layer 141 under the bank layer 117 may be less etched than in the display area AA according to the micro loading effect and the ARDE effect. Therefore, unlike in the display area AA, the bank etching layer 141 of the non-display area NA may be formed to have a width smaller than the width of the lower end portion of the bank layer 117, but a portion of the bank etching layer 141 formed within the width of the lower end portion of the bank layer 117 may be smaller than the width of the lower end portion of the bank layer 117. For example, the bank etching layer 141 in the non-display area NA may also be formed so that the bank layer 117 has an undercut structure.

[0078] In the present invention, for convenience of description, the bank hole 117H is shown to have a rectangular shape, but the present invention is not limited thereto. For example, the bank hole 117H may be formed in a circular or polygonal shape.

[0079] Figure 3 A cross-sectional view of a display region in a display device according to an embodiment of the present invention is illustrated, illustrating a boundary between adjacent sub-pixels.

[0080] Reference Figure 3, the display device may include: a substrate 100 including a plurality of sub-pixels SP; a bank layer 117, the bank layer 117 being located at a boundary between the sub-pixels SP and exposing a light-emitting portion of each sub-pixel SP; a first driving electrode 143 provided for each sub-pixel SP; a bank etching layer 141, the bank etching layer 141 being located between the bank layer 117 and the first driving electrode 143 so that a lower end portion of the bank layer 117 adjacent to the light-emitting portion is vertically separated from an upper portion of the first driving electrode 143; a hole injection layer 144, the hole injection layer 144 being located on a surface of the bank layer 117 and in the light-emitting portion and being separated at a lower end portion of the bank layer 117; and one or more common layers 145, 148 and 149 formed on the hole injection layer 144.

[0081] Here, the "common layer" may be formed in a plurality of sub-pixels SP in at least the display area AA without being separated. Each common layer is formed in the entire display area AA and has an extension extending outward from the display area AA to partially overlap with the non-display area NA. In addition, the hole injection layer 144 disposed at the lower end of the bank layer also has an extension extending outward from the display area AA to partially overlap with the non-display area NA.

[0082] In addition to the hole transport layer 145 and the electron transport layer 148 , a second driving electrode 149 may also be included in the common layer as a counter electrode with respect to the first driving electrode 143 .

[0083] In addition to the above-described layers, as common layers, a hole control layer may be further provided between the hole transport layer 145 and the light emitting layer 147 , and an electron control layer may be further provided between the light emitting layer 147 and the electron transport layer 148 .

[0084] In the bank layer 117 described in the present invention, the region where the light emitting layer 147 emits light, for example, the portion where the pattern for defining the light emitting portion is not formed can be the light emitting portion. The bank layer 117 can be made of a material having an etching rate different from that of the bank etching layer 141 of the present invention, for example, can be made of an organic material such as polyimide, but the present invention is not limited thereto. In addition, for example, the bank etching layer 141 can be made of an inorganic material or other insulating material having an etching rate different from that of the bank layer 117.

[0085] The light emitting layer 147 is provided to correspond to at least the light emitting portion of each sub-pixel SP. The light emitting layer 147 may be formed by depositing a light emitting material of a color corresponding to a predetermined color of light emitted from each sub-pixel SP using a fine metal mask (FMM) having an opening. The light emitting layer 147 may be separately provided between the hole transport layer 145 and the electron transport layer 148 for each sub-pixel SP. Unlike common layers such as the hole transport layer 145, the electron transport layer 148, and the second driving electrode 149 formed using a common mask having an opening larger than the display area AA, since the light emitting layer 147 is formed in the light emitting portion of a specific sub-pixel SP using an FMM having a fine opening, the area of ​​each sub-pixel SP may be distinguished.

[0086] As another example, the structure of the light emitting layer 147 may be formed in a structure in which a plurality of light emitting layers 147 are stacked. A plurality of light emitting layers 147 may be stacked to ultimately emit white light, or a plurality of light emitting layers 147 having the same color as light emitted from the corresponding sub-pixel SP may be stacked. For optimal combination between holes and electrons, a charge generation layer or a transport layer may be further provided between the light emitting layers 147 in the stacked structure of the plurality of light emitting layers 147.

[0087] More specifically, on the first driving electrode 143, at least one light-emitting layer 147 may include a hole transport layer, a hole injection layer, a hole blocking layer, an organic light-emitting layer, an electron injection layer, an electron blocking layer, an electron transport layer, etc., which may be stacked sequentially or reversely according to the emission direction thereof. In addition, the light-emitting layer 147 may include a first light-emitting stack and a second light-emitting stack that are opposite to each other with a charge generation layer sandwiched therebetween. In this case, the organic light-emitting layer of one of the first light-emitting stack and the second light-emitting stack generates blue light, and the organic light-emitting layer of the other of the first light-emitting stack and the second light-emitting stack generates yellow-green light, thereby generating white light through the first light-emitting stack and the second light-emitting stack. Since the white light generated by the light-emitting stack is incident on a color filter located above or below the light-emitting layer 147, a color image may be realized. As another example, in the absence of a separate color filter, each light-emitting layer 147 may generate color light corresponding to each sub-pixel SP, thereby realizing a color image. For example, the light emitting layer 147 of the red (R) sub-pixel SP may generate red light, the light emitting layer 147 of the green (G) sub-pixel SP may generate green light, and the light emitting layer 147 of the blue (B) sub-pixel SP may generate blue light.

[0088] The hole injection layer 144 may include 5 wt% (weight percentage) or less of a p-type dopant in the hole transport material, and thus may be a p-type layer. The hole injection layer 144 may play a role in facilitating hole injection. For example, when a current is applied between the first drive electrode 143 and the second drive electrode 149, and when holes flow from the first drive electrode 143, the interface resistance may be reduced at the interface where the first drive electrode 143 intersects with the hole injection layer 144 as an organic layer, thereby facilitating hole injection.

[0089] Since the hole injection layer 144 includes a p-type dopant having high conductivity, when the hole injection layer 144 is not separated and formed in the shape of a common layer in the sub-pixel SP, the hole injection layer 144 may cause leakage current in the lateral direction. Therefore, in the display device 1000 of the present invention, the hole injection layer 144 may be formed using a common mask like a common layer, and the structure formed thereunder may be changed, so that the hole injection layer 144 may be implemented so that the sub-pixels SP are separated and spaced apart from each other.

[0090] The bank etch layer 141 may separate the hole injection layer 144 for each sub-pixel SP, and the bank etch layer 141 may be formed under the bank layer 117. The bank etch layer 141 is made of a material having an etch selectivity different from that of the bank layer 117. Here, the bank layer 117 may be made of an organic insulating material such as benzocyclobutene (BCB), an acrylic resin, or an imide resin, and the bank etch layer 141 may be formed as an inorganic film. The bank etch layer 141 may include, for example, at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon nitride oxide (SiOxNy) and may be formed as a single layer made of a material, a multilayer made of the same material, or a multilayer made of different materials. As another example, the bank etch layer 141 and the bank layer 117 may be made of organic materials having different etch selectivities.

[0091] Since the bank etching layer 141 is a layer having no electrical or optical function and no function of regionally separating the hole injection layer 144 initially deposited after forming the bank layer 117, the bank etching layer 141 should be deposited thinly. In addition, since the bank etching layer 141 should be formed to have a width smaller than that of the bank layer 117, it is advantageous that the bank etching layer 141 can be formed as an inorganic insulating film that is easy to form relatively thinly and has an etching selectivity different from that of an organic film.

[0092] The bank etch layer 141 is formed to have a width smaller than that of the lower end of the bank layer 117 and an edge thereof is located at a point spaced inwardly from the edge of the lower end of the bank layer 117. Therefore, since the edges of the bank layer 117 and the bank etch layer 141 are formed at different positions, the bank layer 117 may be vertically spaced apart from the first driving electrode 143 at a portion of the lower end of the bank layer 117 that relatively protrudes further than the bank etch layer 141. Since the bank etch layer 141 disposed below the bank layer 117 is etched more than the bank layer 117, the exposed lower end of the bank layer 117 is referred to as an "undercut".

[0093] When the p-type layer forming material is deposited in a state where the bank etching layer 141 having a width different from that of the bank layer 117 is provided below the bank layer 117 , the hole injection layer 144 is separated in a vertical separation region between the bank layer 117 and the first driving electrode 143 .

[0094] The light-emitting element 140 is arranged in each sub-pixel SP, and the light-emitting element 140 includes a first driving electrode 143, a hole injection layer 144, a hole transport layer 145, a light-emitting layer 147, an electron transport layer 148 (144, 145, 147 and 148 constitute an electroluminescent layer EL) and a second driving electrode 149 deposited in sequence in a vertical direction.

[0095] In the display device according to the embodiment of the present invention, the reason why the hole injection layer 144 is separated between the regions of the sub-pixels SP is because the hole injection layer 144 includes a p-type dopant having high conductivity and is just adjacent to the first driving electrode 143. The hole injection layer 144 is provided to be connected without interruption in each sub-pixel SP like other common layers, and due to the high conductivity of the hole injection layer 144, a lateral leakage current may occur between adjacent first driving electrodes 143. In order to prevent the lateral leakage current, the hole injection layer 144 provided on the upper surface of the bank layer 117 vertically spaced apart from the first driving electrode 143 and the hole injection layer 144 provided on the first driving electrode 143 may be separated from each other at the lower end of the bank layer 117.

[0096] The hole transport layer 145 formed after the hole injection layer 144 may be continuously formed in the region of the sub-pixel SP without separation. Since the hole transport layer 145 is made of only a relatively pure hole transport material compared to the hole injection layer 144 and has a very low conductivity compared to the hole injection layer 144, the hole transport layer 145 does not cause the problem of current flowing to the side even when the hole transport layer 145 is formed in a plane continuous state. In addition, the hole injection layer 144 is relatively thinly formed to have a thickness of about 1000 Å. or smaller, e.g. or less, and the bank etching layer 141 may be formed to have a thickness greater than or equal to that of the hole injection layer 144. For example, when the thickness of the bank etching layer 141 is approximately one to four times the thickness of the hole injection layer 144, since the vertical separation distance between the bank layer 117 and the upper portion of the first driving electrode 143 may be greater than the thickness of the hole injection layer 144, the hole injection layer 144 does not contact the hole injection layer 144 on the bank layer 117 even if the hole injection layer 144 is stacked on the first driving electrode 143 when deposited.

[0097] The light emitting element 140 is connected to a thin film transistor TFT located at a lower side of the substrate 100. The substrate 100 including the thin film transistor TFT and a plurality of thin film transistors required to drive the light emitting element 140 is also referred to as an array substrate.

[0098] The thin film transistor TFT includes a semiconductor layer 131A located at a predetermined portion on the base layer 101, a second insulating layer 107 covering the semiconductor layer 131A, a gate electrode 135G arranged to overlap the semiconductor layer 131A, and a source electrode 137S and a drain electrode 137D connected to both sides of the semiconductor layer 131A.

[0099] The semiconductor layer 131A may be made of, for example, amorphous silicon, polycrystalline silicon, or an oxide semiconductor, and may also be formed by stacking semiconductor layers of different types.

[0100] The third insulating layer 109 may be formed between the gate electrode 135G and the source and drain electrodes 137S and 137D except for connection portions between the semiconductor layer 131A and the source and drain electrodes 137S and 137D.

[0101] The protective layer 111, the first intermediate layer 113, and the second intermediate layer 115 may be formed to cover the thin film transistor TFT. The first intermediate layer 113, the second intermediate layer 115, and the protective layer 111 may be selectively removed to form a contact hole exposing a predetermined portion of the source electrode 137S and the drain electrode 137D to be connected to the first driving electrode 143 of the light emitting element 140.

[0102] Figure 4 is a cross-sectional view of a non-display area at a peripheral portion of a display device according to an embodiment of the present invention.

[0103] Reference Figure 4 , Figure 4The cross section of the gate driver 300 located outside the display area AA is illustrated. Due to the structure including the bank etching layer 141 (the bank etching layer 141 is disposed at the lower end of the bank layer 117 and protrudes inward from the edge of the lower end of the bank layer 117 even in the non-display area NA), the display device according to the embodiment of the present invention can be considered to protect the upper electrode, for example, the second driving electrode 149 to prevent it from being short-circuited.

[0104] The non-display area NA at the peripheral portion of the substrate 100 may be classified according to function. For example, the first area may be in contact with the display area AA to transmit various signals, voltages, etc. applied from the gate driver 300 to the display area AA. The gate driver 300 may be formed in the second area. The third area may be an area designed so that the second encapsulation layer 153 does not cross the weir portion DAM. The weir portion DAM and the power line 400 may be formed in the fourth area. The ends of the first encapsulation layer 151 and the third encapsulation layer 155 may be formed in the fifth area. The rupture prevention portion 500 may be formed in the sixth area.

[0105] The bank etching layer 141 and the edge of the second driving electrode 149 may be disposed in the second region of the non-display area NA where the gate driver 300 is formed. The second driving electrode 149 may be disposed to extend to the second region and may be formed not to be broken in the bank hole 117H.

[0106] Each of the bank etching layer 141 and the second driving electrode 149 may be formed by depositing corresponding organic materials using a common mask that opens the entire display area AA and a portion of the non-display area NA, wherein the bank etching layer 141 is formed to prevent leakage current between pixels in the display area AA, and the second driving electrode 149 is formed as a common layer. In the non-display area NA, the second driving electrode 149 connected to the lower connection line 143c is formed to protrude toward the gate electrode 300 at the peripheral portion of the non-display area NA, wherein the lower connection line 143c is made of the same material as the first driving electrode 143 to receive a ground voltage or a driving voltage, and the bank etching layer 141 is formed up to the outermost area of ​​the non-display area NA including the gate driver 300 and the dam DAM.

[0107] The bank etching layer 141 is formed by being deposited over the entire area of ​​the substrate 100, and the second driving electrode 149 is deposited on the bank layer 117 formed in an undercut structure due to the bank etching layer 141. The bank layer 117 may be patterned by an optical process so that the second driving electrode 149 is connected to a lower connection line 143c made of the same material as the first driving electrode 143. The bank etching layer 141 may protect the lower connection line 143c from being damaged.

[0108] Due to the formation of the bank etching layer 141, the hole injection layer 144 is disconnected, thereby preventing driving due to leakage current between adjacent sub-pixels in the display area AA, but since a plurality of common layers or light-emitting layers 147 are not formed in the non-display area NA, the non-display area NA may become a structure in which the disconnection of the second driving electrode 149 is unfavorable compared to the display area AA.

[0109] Therefore, in the second area of ​​the non-display area NA, one or more embankment holes 117H are formed in the embankment layer 117 and the embankment etching layer 141 to connect the lower connecting line 143c and the second driving electrode 149 at least once or contact them at at least one position, thereby preventing driving failure due to a short circuit of the second driving electrode 149 formed on the embankment layer 117.

[0110] In addition, in the second area of ​​the non-display area NA, in order to constitute the gate driver 300, a plurality of gate metal patterns 131 and 135 separated from each other may be patterned coplanarly with the gate line GL, and a plurality of first source / drain metal patterns 137 separated from each other may be patterned coplanarly with the data line DL.

[0111] The bank hole 117H may be formed by utilizing a micro loading effect to prevent disconnection of the second driving electrode 149. To this end, the bank hole 117H in the non-display area NA may be formed smaller than the bank hole 117H in the display area AA by about 1 / 3 to 1 / 5 thereof.

[0112] Since the second driving electrode 149 is multiple connected to the lower connection line 143c arranged coplanar with the first driving electrode 143 in the display area AA through the embankment hole 117H, the electrical stability of the second driving electrode 149 can be further improved, and a portion of the lower connection line 143c can be connected to the first and second source / drain metal patterns 137 and 139 arranged therebelow to apply a ground voltage or a driving voltage.

[0113] In the fourth region of the non-display area NA, a power line VSS may be formed at an end of the non-display area NA to be coplanar with the first source / drain metal pattern 137, a second source / drain metal pattern 139 may be disposed to be connected to the power line VSS through a contact hole formed in the first intermediate layer 113, and a lower connection line 143c formed on the second intermediate layer 115 may be connected to the second source / drain metal pattern 139 to apply a ground voltage or a driving voltage to the second driving electrode 149. The power line VSS may be formed not only in the fourth region of the non-display area NA but also in the third region.

[0114] In the display device according to the embodiment of the present invention, since the bank etching layer 141 is provided in the non-display area NA to protrude inwardly toward the lower end of the bank layer 117, in order to prevent the short circuit of the second driving electrode 149 formed in each layer on the upper side of the bank layer 117, one or more bank holes 117H may be formed at least in the non-display area NA so that the second driving electrode 149 is stably in contact with the lower connection line 143c. In addition, the second driving electrode 149 can be electrically connected to the power supply line VSS provided coplanar therewith through the lower connection line 143c.

[0115] In addition, in the sixth region of the non-display area NA, a crack preventing portion or a crack detector 500 may be formed using the first gate metal pattern 131 and the second gate metal pattern 135. Damage to the substrate 100 may be detected by a crack detection signal provided in the first gate metal pattern 131 and the second gate metal pattern 135 in the sixth region of the non-display area NA.

[0116] Reference Figure 3 and Figure 4 , the pixel driving circuit and the light emitting element 140 are not provided in the non-display area NA, but the base layer 101 and the organic / inorganic layers 103, 105, 107, 109, 111 and 115 may be present. In addition, for other purposes, the material for constituting the display area AA may be provided in the non-display area NA. For example, a second gate metal pattern 135 made of the same material as the gate electrode 135G of the thin film transistor TFT in the display area AA or a first source / drain metal pattern 137 made of the same material as the source electrode 137S and the drain electrode 137D in the display area AA may be provided in the non-display area NA as a line or electrode. In addition, a second source / drain metal pattern 139 may be provided in the non-display area NA as a line or electrode. These metal patterns may be provided on different layers and may be insulated from each other by a plurality of layers 103, 105, 107, 109, 111, 113 and 115. For example, the source electrode 137S and the drain electrode 137D may be used as a power line 400. The power line 400 may be connected to the second source / drain metal pattern 139, and the first driving electrode 143 of the light emitting element 140 may be connected to the source electrode 137S, the drain electrode 137D, and the second source / drain metal pattern 139 to receive power. The second source / drain metal pattern 139 may contact the power line 400 and may extend along the outermost sidewall of the second intermediate layer 115 to intersect or contact the first driving electrode 143 on the second intermediate layer 115.

[0117] The base layer 101 may be made of a plastic material having flexibility. When the base layer 101 is made of a plastic material, for example, the base layer 101 may be made of polyimide (PI), but the present invention is not limited thereto. When the base layer 101 is made of PI, the manufacturing process of the display device 1000 is performed in a state where a supporting substrate made of glass is disposed below the base layer 101, and after the manufacturing process of the display device 1000 is completed, the supporting substrate may be released. In addition, after the supporting substrate is released, a backplane for supporting the base layer 101 may be disposed below the base layer 101. However, the present invention is not limited thereto, and in some cases, a supporting substrate made of glass may be used without change.

[0118] The buffer layer 103 having a single layer or a multi-layer structure may be disposed on the base layer 101. The buffer layer 103 disposed on the base layer 101 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multi-layer in which silicon nitride (SiNx) and silicon oxide (SiOx) are alternately formed.

[0119] The buffer layer 103 can improve the bonding strength between the base layer 101 and the layers formed on the buffer layer 103 and can protect the thin film transistor TFT from the influence of impurities such as alkaline ions leaking from the base layer 101 or the layers below. The buffer layer 103 can be formed of silicon oxide (SiOx), silicon nitride (SiNx) or a multilayer thereof, but the present invention is not limited thereto. The buffer layer 103 may include a multi-buffer and / or an active buffer. In addition, based on the type and material of the base layer 101 and the structure and type of the thin film transistor TFT, the buffer layer 103 may be omitted.

[0120] In the display area AA of the base layer 101, a thin film transistor TFT for driving the light emitting element 140 may be disposed on the buffer layer 103. A first insulating layer 105 may be further disposed between the thin film transistor TFT and the buffer layer 103 to form the thin film transistor TFT more stably.

[0121] The thin film transistor TFT may include a semiconductor layer 131A, a gate electrode 135G, a source electrode 137S, and a drain electrode 137D. Here, according to the design of the pixel circuit, the source electrode 137S may be a drain electrode, and the drain electrode 137D may be a source electrode. In the display area AA of the base layer 101, the semiconductor layer 131A of the thin film transistor TFT may be disposed on the first insulating layer 105.

[0122] The semiconductor layer 131A may include low temperature polysilicon (LTPS). Since polysilicon material has (100 cm 2 / Vs or greater) high mobility, low energy consumption and excellent reliability, so the polysilicon material can be applied to a gate driver and / or a multiplexer (MUX) as a driving element, and the driving element is used to drive a thin film transistor as a display element. In addition, in the display device 1000 according to the embodiment of the present invention, the polysilicon material can be applied to the semiconductor layer 131A of the driving thin film transistor, but the present invention is not limited thereto. For example, according to the characteristics of the display device 1000, the polysilicon material can be applied to the semiconductor layer of the switching thin film transistor. Polysilicon can be formed by depositing amorphous silicon (a-Si) on the first insulating layer 105 and performing a dehydrogenation process and a crystallization process, and the polysilicon can be patterned to form the semiconductor layer 131A.

[0123] The semiconductor layer 131A may include a channel region 131C that forms a channel when the thin film transistor TFT is driven, and a source region 131S and a drain region 131D on both sides of the channel region 131C. The source region 131S may be a portion of the semiconductor layer 131A connected to the source electrode 137S, and the drain region 131D may be a portion of the semiconductor layer 131A connected to the drain electrode 137D. The source region 131S and the drain region 131D may be formed of the semiconductor layer 131A doped with ions, such as impurities. The source region 131S and the drain region 131D may be formed of a polysilicon material doped with ions, and the channel region 131C may be a portion that is not doped with ions and is retained as a polysilicon material.

[0124] The semiconductor layer 131A may be made of an oxide semiconductor. Since the oxide semiconductor material is a material having a band gap larger than that of a silicon material, electrons do not cross the band gap in the off state, so the off current may be lower. Therefore, a thin film transistor including a semiconductor layer made of an oxide semiconductor may be suitable for a switching thin film transistor having a shorter on time and a longer off time, but the present invention is not limited thereto. According to the characteristics of the display device 1000, a thin film transistor including a semiconductor layer made of an oxide semiconductor may be applied as a driving thin film transistor. Since the off current may be lower, the size of the auxiliary capacitor may be reduced, and thus a thin film transistor including a semiconductor layer made of an oxide semiconductor may be suitable for a high-resolution display element. For example, the semiconductor layer 131A may be made of a metal oxide, for example, various metal oxides such as indium gallium zinc oxide (IGZO). It has been assumed that the semiconductor layer 131A is made of IGZO among various metal oxides to describe the semiconductor layer 131A forming a thin film transistor TFT based on an IGZO layer. However, the present invention is not limited thereto, and the semiconductor layer 131A may be made of other metal oxides other than IGZO, such as indium zinc oxide (IZO), indium gallium tin oxide (IZTO), and indium gallium oxide (IGO). The semiconductor layer 131A may be formed by depositing the metal oxide on the first insulating layer 105, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0125] The semiconductor layer 131A may be formed in the non-display area NA as a first gate metal pattern 131. The first gate metal pattern 131 may be a portion of a driving element disposed on the first insulating layer 105 in the gate driver 300, may be disposed coplanar with the semiconductor layer 131A of the thin film transistor TFT, and may be made of the same material as the semiconductor layer 131A, but the present invention is not limited thereto.

[0126] A second insulating layer 107 covering the upper surface of the semiconductor layer 131A of the thin film transistor TFT may be provided on the first insulating layer 105. The second insulating layer 107 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx). Contact holes may be formed in the second insulating layer 107 to connect the source electrode 137S and the drain electrode 137D of the thin film transistor TFT to the source region 131S and the drain region 131D of the semiconductor layer 131A of the thin film transistor TFT, respectively.

[0127] In the display area AA, the second insulating layer 107 may be disposed on the semiconductor layer 131A. In the non-display area NA, the second insulating layer 107 may be disposed on the first insulating layer 105. Figure 3 and Figure 4As shown in , the second insulating layer 107 may be formed on the entire surface of the substrate. However, the present invention is not limited thereto. For example, the second insulating layer 107 may be patterned to have the same width as the gate electrode 135G.

[0128] In the display area AA of the base layer 101, the gate electrode 135G and the gate line GL connected to the gate electrode 135G of the thin film transistor TFT, a storage capacitor (not shown), etc. may be disposed on the second insulating layer 107. The gate electrode 135G and the gate line GL may be formed as a single layer or multiple layers made of one selected from molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The gate electrode 135G may be formed on the second insulating layer 107 to overlap with the channel region 131C of the semiconductor layer 131A of the thin film transistor TFT.

[0129] The gate electrode 135G may be formed in the non-display area NA as a second gate metal pattern 135. The second gate metal pattern 135 may be a portion of a driving element disposed on the second insulating layer 107 in the gate driver 300, and may be coplanarly disposed with the gate electrode 135G of the thin film transistor TFT and may be made of the same material as the gate electrode 135G.

[0130] A third insulating layer 109 may be disposed on the second insulating layer 107 to cover the gate electrode 135G and the gate line GL of the display area AA and the second gate metal pattern 135 of the non-display area NA. The third insulating layer 109 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx). A contact hole may be formed in the third insulating layer 109 to expose the source region 131S and the drain region 131D of the semiconductor layer 131A of the thin film transistor TFT. Figure 3 and Figure 4 As shown in FIG. 1 , the third insulating layer 109 may be formed on the entire surface of the substrate, but the present invention is not limited thereto. For example, the third insulating layer 109 may be patterned to have the same width as the semiconductor layer 131A.

[0131] In the display area AA of the base layer 101, a source electrode 137S and a drain electrode 137D of the thin film transistor TFT may be disposed on the third insulating layer 109. The source electrode 137S and the drain electrode 137D of the thin film transistor TFT may be connected to the semiconductor layer 131A of the thin film transistor TFT through contact holes formed in the second insulating layer 107 and the third insulating layer 109. Therefore, the source electrode 137S of the thin film transistor TFT may be connected to the source region 131S of the semiconductor layer 131A through the contact holes formed in the second insulating layer 107 and the third insulating layer 109. The drain electrode 137D of the thin film transistor TFT may be connected to the drain region 131D of the semiconductor layer 131A through the contact holes formed in the second insulating layer 107 and the third insulating layer 109. The source electrode 137S and the drain electrode 137D may be made of one selected from molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof, and may be formed as a single layer or multiple layers. For example, the source electrode 137S and the drain electrode 137D may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) made of a conductive metal material. The materials of the source electrode 137S and the drain electrode 137D are not limited to the above materials. For ease of description, Figure 3 Only the driving thin film transistor among various thin film transistors that may be included in the display device 1000 is illustrated, but other thin film transistors such as a switching thin film transistor may also be included in the display device 1000. In addition, although it has been described herein that the thin film transistor TFT has a coplanar structure, the thin film transistor may be implemented in other structures such as a staggered structure.

[0132] In the non-display area NA of the base layer 101, a first source / drain metal pattern 137 serving as a portion of a driving element of the gate driver 300 may be disposed on the third insulating layer 109. The first source / drain metal pattern 137 may be disposed coplanar with a source electrode 137S and a drain electrode 137D of the thin film transistor TFT and may be made of the same material as the source electrode 137S and the drain electrode 137D. Figure 3 and Figure 4 As shown in FIG. 1 , the gate driver 300 may include various components such as a first gate metal pattern 131, a second gate metal pattern 135, and a first source / drain metal pattern 137. The first source / drain metal pattern 137 may be electrically connected to the power line 400 and the first driving electrode 143 to provide power to the first driving electrode 143.

[0133] In the display area AA and the non-display area NA, a protective layer 111 may be disposed on the thin film transistor TFT, the first source / drain metal pattern 137, and the gate driver 300. The protective layer 111 may be disposed to cover the thin film transistor TFT, the first source / drain metal pattern 137, and the gate driver 300. The protective layer 111 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx). In the display area AA, a contact hole for exposing the drain electrode 137D of the thin film transistor TFT may be formed in the protective layer 111. In the non-display area NA, a contact hole for exposing the first source / drain metal pattern 137 may be formed in the protective layer 111.

[0134] The first intermediate layer 113 is an insulating layer that protects the thin film transistor TFT, the gate driver 300 and a plurality of lines or electrodes and reduces steps on the base layer 101 so that a surface on the base layer 101 has a uniform height.

[0135] The first intermediate layer 113 may be disposed in both the display area AA and the non-display area NA. In the display area AA and the non-display area NA, the first intermediate layer 113 may be disposed on the protective layer 111 to overlap with the thin film transistor TFT of the display area AA, the gate driver 300 of the non-display area NA, and the like. Figure 3 and Figure 4 As shown in FIG. 1 , the first intermediate layer 113 may be disposed in the display area AA and in the area where the gate driver 300 is located in the non-display area NA. In the area where the first source / drain metal pattern 137 is located, a contact hole exposing the first source / drain metal pattern 137 may be formed by partially removing the first intermediate layer 113.

[0136] The first intermediate layer 113 may be made of one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, PI resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, BCB, and photoresist, but the present invention is not limited thereto.

[0137] As the first intermediate layer 113 is formed thinner, the first intermediate layer 113 becomes more process-friendly. However, the first intermediate layer 113 may have a thickness value ranging from at least 1 μm to 5 μm, thereby maintaining an appropriate interval between the first source / drain metal pattern 137 and the second source / drain metal pattern 139 and filling the concave portion of the first source / drain metal pattern 137.

[0138] The first intermediate layer 113 may be provided to cover the thin film transistor TFT and the gate driver 300. In the display area AA, a contact hole exposing the drain electrode 137D may be formed in the first intermediate layer 113. In the non-display area NA, the first intermediate layer 113 may include a contact hole exposing the second source / drain metal pattern 139 together with the protective layer 111 provided on the first source / drain metal pattern 137. The first intermediate layer 113 may be an organic material layer that protects the thin film transistor TFT and the gate driver 300 and reduces the step on the base layer 101 so that the surface on the base layer 101 has a uniform height. For example, the first intermediate layer 113 may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a PI resin, but the present invention is not limited thereto.

[0139] In the display area AA of the base layer 101, a connection electrode 139C made of the same material as the second source / drain metal pattern 139 may be disposed on the first intermediate layer 113 (see FIG. 1 ). Figure 3 ). The connection electrode 139C may be connected to the drain electrode 137D of the thin film transistor TFT through the contact hole of the first intermediate layer 113 and the protective layer 111 exposing the drain electrode 137D. The connection electrode 139C may be used to electrically connect the thin film transistor TFT and the light emitting element 140. For example, the connection electrode 139C may be used to electrically connect the drain electrode 137D of the thin film transistor TFT and the first driving electrode 143 of the light emitting element 140. The connection electrode 139C may be formed as a single layer or a multilayer made of one selected from molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof, but the present invention is not limited thereto. The connection electrode 139C may be made of the same material as the source electrode 137S and the drain electrode 137D of the thin film transistor TFT.

[0140] In the non-display area NA of the base layer 101, a second source / drain metal pattern 139 may be disposed on the first intermediate layer 113. The second source / drain metal pattern 139 may be connected to the first source / drain metal pattern 137 through a contact hole exposing the first intermediate layer 113 and the protective layer 111 of the first source / drain metal pattern 137. The second source / drain metal pattern 139 may be formed as a single layer or multiple layers made of one selected from molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The second source / drain metal pattern 139 may be formed to be coplanar with the connection electrode 139C or the source electrode 137S and the drain electrode 137D of the thin film transistor TFT, and may be made of the same material as the connection electrode 139C or the source electrode 137S and the drain electrode 137D, but the present invention is not limited thereto.

[0141] A plurality of contact holes through which the second source / drain metal pattern 139 passes may be formed in the first intermediate layer 113 and the protective layer 111 disposed below the second source / drain metal pattern 139 , and the second source / drain metal pattern 139 may be electrically connected to the first source / drain metal pattern 137 through the contact holes.

[0142] Since the first source / drain metal pattern 137 and the second source / drain metal pattern 139 used as signal lines in the non-display area NA are electrically connected to each other, the resistance can be reduced compared to the case where the first source / drain metal pattern 137 or the second source / drain metal pattern 139 is formed as a separate line, thereby improving image quality.

[0143] In the display area AA of the base layer 101, the second intermediate layer 115 may be disposed on the connection electrode 139C and the first intermediate layer 113. For example, the second intermediate layer 115 may be disposed on the first intermediate layer 113 to cover the connection electrode 139C. Figure 3 and Figure 4 As shown in , a contact hole exposing the connection electrode 139C may be formed in the second intermediate layer 115. The second intermediate layer 115 may be an organic material layer that further reduces the step of the underlying structure due to the connection electrode 139C on the first intermediate layer 113 and additionally protects the underlying structure. For example, the second intermediate layer 115 may be made of at least one selected from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and PI resin, but the present invention is not limited thereto. The second intermediate layer 115 may be made of the same material as the first intermediate layer 113, but the present invention is not limited thereto.

[0144] In the non-display area NA of the base layer 101, the second intermediate layer 115 may be disposed to cover the second source / drain metal pattern 139. Figure 3 and Figure 4 As shown in FIG. 1 , the second intermediate layer 115 may be formed to contact the first intermediate layer 113 through the opening portion of the second source / drain metal pattern 139. Since the first intermediate layer 113 and the second intermediate layer 115 contact each other in the opening portion of the second source / drain metal pattern 139, the adhesive strength may be improved, thereby reducing defects caused by delamination of the second source / drain metal pattern 139.

[0145] In the display device 1000 according to an embodiment of the present invention, the first intermediate layer 113 and the second intermediate layer 115 may be formed in the display area AA as an insulating layer for reducing a step generated on an upper layer of the thin film transistor TFT so that a surface on the base layer 101 has a uniform height. Therefore, an additional space may be provided in which various lines used in the display area AA of the display device 1000 may be disposed.

[0146] For example, compared with the case of using one intermediate layer, an additional space in which a wire can be arranged can be provided in the space between the first intermediate layer 113 and the second intermediate layer 115, that is, on the upper surface of the first intermediate layer 113. Therefore, in the display device 1000 according to the embodiment of the present invention, the design freedom of the wire arrangement can be increased. As a result, the display device 1000 with higher resolution can be provided, and the brightness uniformity problem that may occur due to the high resistance of the wire arranged in the display area AA of the display device 1000 can be solved.

[0147] Since the first intermediate layer 113 and the second intermediate layer 115 are made of an organic material, the first intermediate layer 113 and the second intermediate layer 115 may be easily affected by external moisture. To prevent this problem, in the second area of ​​the non-display area NA, the first intermediate layer 113 and the second intermediate layer 115 may be partially removed and thus may be formed to be disconnected by the lower connection line 143c and the second driving electrode 149.

[0148] The first driving electrode 143 of the light emitting element 140 may be disposed on the second intermediate layer 115. The first driving electrode 143 may be electrically connected to the connection electrode 139C through a contact hole formed in the second intermediate layer 115. Therefore, the first driving electrode 143 may be connected to the connection electrode 139C through a contact hole formed in the second intermediate layer 115, thereby being electrically connected to the thin film transistor TFT.

[0149] The first drive electrode 143 may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film having high reflection efficiency. The transparent conductive film may be made of a material having a relatively large work function value, such as indium tin oxide (ITO) or IZO. The opaque conductive film may be formed as a single layer or multilayer structure including at least one selected from Al, Ag, Cu, Pb, Mo and Ti or an alloy thereof. For example, the first drive electrode 143 may be formed as a structure in which a transparent conductive film, an opaque conductive film and a transparent conductive film are stacked in sequence. However, the present invention is not limited thereto, and the first drive electrode 143 may be formed as a structure in which a transparent conductive film and an opaque conductive film are stacked in sequence.

[0150] The display device 1000 according to the embodiment of the present invention may be a top emission type display device 1000 or a bottom emission type display device 1000. Therefore, the first driving electrode 143 disposed on the second intermediate layer 115 may be an anode, and the first driving electrode 143 may also be a cathode.

[0151] The bank layer 117 is a structure for separating adjacent sub-pixels in the display area AA, and the bank layer 117 may define a plurality of sub-pixels. The bank layer 117 may be made of an organic material. The bank layer 117 may be disposed on the first driving electrode 143 and the second intermediate layer 115.

[0152] In the display area AA, an opening exposing the first driving electrode 143 may be formed in the bank layer 117. The bank layer 117 may also be referred to as a pixel defining film because the bank layer 117 may define a light emitting portion of the display device 1000. The bank layer 117 may be provided to cover both ends of the first driving electrode 143.

[0153] A spacer may be further disposed on the bank layer 117 in the fourth region of the non-display area NA where the dam DAM is formed. Also, in the third region of the non-display area NA, a portion of the bank layer 117 may be removed from the bank layer 117 to form the dam DAM of the fourth region.

[0154] The bank layer 117 and the spacer may be made of the same material. The bank layer 117 and the spacer may be made of an organic material. For example, the bank layer 117 and the spacer may be made of a PI-based, acrylic-based, or BCB-based resin, but the present invention is not limited thereto.

[0155] A light emitting element 140 including a light emitting layer 147 may be further disposed on the second intermediate layer 115 and the bank layer 117 . Figure 3 The light-emitting layer 147 is illustrated to be patterned for each sub-pixel, but the present invention is not limited thereto. The light-emitting layer 147 may be a common layer formed in a plurality of sub-pixels in common. On the first driving electrode 143, the light-emitting layer 147 may include a hole transport layer, a hole blocking layer, a hole injection layer, an organic light-emitting layer, an electron injection layer, an electron blocking layer, an electron transport layer, etc., which may be stacked sequentially or reversely stacked according to the emission direction. In addition, the light-emitting layer 147 may include a first light-emitting stack and a second light-emitting stack that are opposite to each other with a charge generation layer sandwiched therebetween. In this case, the light-emitting layer of one of the first light-emitting stack and the second light-emitting stack may generate blue light, and the light-emitting layer of the other of the first light-emitting stack and the second light-emitting stack may generate yellow-green light, thereby generating white light through the first light-emitting stack and the second light-emitting stack. The white light generated by the light-emitting layer 147 may be incident on a color filter located on the light-emitting layer 147, thereby realizing a color image. In addition, in the absence of a separate color filter, each light-emitting layer 147 may generate a color light corresponding to each sub-pixel SP, thereby realizing a color image. For example, the light emitting layer 147 of the red (R) sub-pixel SP may generate red light, the light emitting layer 147 of the green (G) sub-pixel SP may generate green light, and the light emitting layer 147 of the blue (B) sub-pixel SP may generate blue light.

[0156] A second driving electrode 149 may be further disposed on the light emitting layer 147. The second driving electrode 149 may be disposed on the light emitting layer 147 to be opposite to the first driving electrode 143 with the light emitting layer 147 interposed therebetween.

[0157] The display device 1000 according to the embodiment of the present invention may be a top emission type display device 1000 or a bottom emission type display device 1000. Therefore, the second driving electrode 149 may be a cathode, and the first driving electrode 143 may be an anode.

[0158] In the display area AA of the base layer 101, an encapsulation layer 150 may be disposed on the light emitting element 140. For example, an encapsulation layer 150 that suppresses moisture penetration may be further disposed on the second driving electrode 149.

[0159] The encapsulation layer 150 prevents the penetration of external oxygen or moisture so as to prevent oxidation of the light-emitting material and the electrode material. When the organic light-emitting element is exposed to moisture or oxygen, a pixel shrinkage phenomenon in which the light-emitting area is reduced may occur, or dark spots may appear in the light-emitting area. The encapsulation layer 150 may be formed as an inorganic film made of glass, metal, aluminum oxide (AlOx) or silicon (Si) type materials, or may have a structure in which organic films and inorganic films are alternately stacked. The inorganic film is used to block the penetration of moisture or oxygen, and the organic film is used to make the surface of the inorganic film have a uniform height. Compared with the case of a single layer, when the encapsulation layer is formed as a multi-layer thin film layer, the movement path of moisture or oxygen becomes longer and more complicated, which makes it difficult for moisture / oxygen to penetrate into the organic light-emitting element.

[0160] In the display device 1000 according to an embodiment of the present invention, the encapsulation layer 150 may include a first encapsulation layer 151, a second encapsulation layer 153, and a third encapsulation layer 155. The first encapsulation layer 151 of the encapsulation layer 150 may be disposed on the second driving electrode 149. The second encapsulation layer 153 may be disposed on the first encapsulation layer 151. In addition, the third encapsulation layer 155 may be disposed on the second encapsulation layer 153. The first encapsulation layer 151 and the third encapsulation layer 155 of the encapsulation layer 150 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second encapsulation layer 153 of the encapsulation layer 150 may be made of at least one selected from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and PI resin, but the present invention is not limited thereto.

[0161] The edge of the bank etching layer 141 disposed in the display area AA is disposed inside the edge of the lower end portion of the bank layer 117, compared to the edge of the bank etching layer 141 disposed in the non-display area NA. In the display device 1000 according to the embodiment of the present invention, a bank etching layer 141 is further disposed below the bank layer 117, and the bank etching layer 141 protrudes inward toward the lower end portion of the bank layer 117, so that due to the shape of the bank etching layer, the hole injection layer 144 formed in contact with the first driving electrode 143 is separated into a portion formed on the first driving electrode 143 and a portion formed on the bank layer 117, thereby allowing the hole injection layer 144 to be separately disposed for each sub-pixel SP. By forming the bank etching layer 141 inside the edge of the bank layer 117 and forming the bank etching layer 141 to have a thickness greater than a target thickness of the hole injection layer 144, the hole injection layer 144 can be separated.

[0162] By separating the material having high conductivity of the hole injection layer 144 for each sub-pixel SP, the hole injection layer 144 that may cause leakage current can be formed collectively without changing the deposition mask. That is, leakage current is prevented to prevent the defect that adjacent pixels are turned on and driven in a low brightness state, thereby improving visibility.

[0163] Furthermore, a driving voltage may be reduced by separating a layer that may cause leakage current for each sub-pixel SP in the display device, and the light emitting layer 147 driven at a low voltage may be applied.

[0164] Even when the concentration of the p-type dopant increases, there is no problem of lateral leakage current, the device characteristics can be improved, and the life span can be increased. In particular, despite the low threshold voltage, the p-type dopant can be applied as a material for a hole transport layer, a hole transport auxiliary layer, or a light emitting layer, thereby significantly increasing the life span.

[0165] Furthermore, the first driving electrode 143 is cleaned before and after forming the bank etching layer 141 , thereby improving the bonding characteristics between the hole injection layer 144 having an interface with the first driving electrode 143 , reducing point defects, and increasing the lifespan.

[0166] The display device according to the embodiment of the present invention can be described as follows.

[0167] A display device according to an embodiment of the present invention includes: a substrate having a display area and a non-display area; a lower connection line arranged in the non-display area; a bank layer, the bank layer being arranged on the lower connection line and having an undercut structure at the edge of the lower end of the bank layer; a bank etching layer, the bank etching layer being arranged between the lower connection line and the bank layer and having an edge inside the edge of the lower end of the bank layer; and a second driving electrode, the second driving electrode being arranged on the bank layer and being electrically connected to the lower connection line at least once. A plurality of bank holes may be formed in the bank layer.

[0168] In the display device according to the embodiment of the present invention, the second driving electrode may be connected to the lower connection line through the bank hole, and the second driving electrode may be disposed to be spaced apart from the bank etching layer.

[0169] In the display device according to the embodiment of the present invention, the bank layer may include a bank opening in the light emitting portion of the display region, and the bank holes may be more densely disposed than the bank opening.

[0170] In the display device according to the embodiment of the present invention, the bank hole may be formed to be smaller than the bank opening, and to be 1 / 3 to 1 / 5 of the bank opening.

[0171] In the display device according to the embodiment of the present invention, the edge of the bank etching layer disposed in the display area may be disposed inside the edge of the lower end portion of the bank layer compared to the edge of the bank etching layer disposed in the non-display area.

[0172] In the display device according to the embodiment of the present invention, the bank etching layer may be formed as an inorganic insulating film.

[0173] In the display device according to the embodiment of the present invention, the inorganic insulating film may include at least one selected from silicon nitride, silicon oxide, and silicon nitride oxide.

[0174] The display device according to an embodiment of the present invention may further include: a plurality of sub-pixels arranged in the display area; a first driving electrode arranged for each sub-pixel, the first driving electrode being made of the same material as the lower connection line; and a hole injection layer arranged on the first driving electrode and the bank layer. The hole injection layer may be separately arranged at the edge of the bank layer.

[0175] In the display device according to the embodiment of the present invention, the hole injection layer may be provided to be separated from the first driving electrode.

[0176] In the display device according to the embodiment of the present invention, the thickness of the bank etching layer may be greater than or equal to the thickness of the hole injection layer.

[0177] A display device according to an embodiment of the present invention includes: a substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a first driving electrode provided for each sub-pixel; a lower connection line made of the same material as the first driving electrode and provided in the non-display area; a bank layer provided on the first driving electrode and the lower connection line and having an undercut structure at an edge of the bank layer adjacent to the lower connection line; a second driving electrode provided on the bank layer, separated from the first driving electrode and electrically connected to the lower connection line at least once; and a bank etching layer provided so that an upper surface of the bank etching layer is covered by the bank layer. The second driving electrode may contact a side of the bank layer.

[0178] In a display device according to an embodiment of the present invention, the non-display area may include: a first area, which is in contact with the display area to transmit the signal of the gate driver to the display area; a second area, in which the gate driver is arranged; a third area and a fourth area, in which a power line for supplying power to the second driving electrode is arranged; a fifth area, in which an end of an encapsulation layer for preventing oxygen or moisture penetration is arranged; and a sixth area, in which a crack detector is arranged.

[0179] In the display device according to the embodiment of the present invention, a plurality of bank holes may be provided in the second region.

[0180] In the display device according to the embodiment of the present invention, a dam portion may be provided on the power supply line in the fourth region.

[0181] In the display device according to the embodiment of the present invention, the dam portion may be formed by stacking a first intermediate layer, a second intermediate layer, the bank layer, and a spacer.

[0182] In the display device according to the embodiment of the present invention, the second region may be implemented such that the first intermediate layer and the second intermediate layer are separated by the lower connection line and the second driving electrode to block moisture penetration.

[0183] In the display device according to the embodiment of the present invention, the second driving electrode may be provided to extend to the second region and may be formed not to be broken in the bank hole.

[0184] In the display device according to the embodiment of the present invention, the second driving electrode may be connected to the lower connection line at least once through the bank hole and may be disposed to be spaced apart from the bank etching layer.

[0185] In the display device according to the embodiment of the present invention, the edge of the bank etching layer disposed in the display area may be disposed inside the edge of the lower end portion of the bank layer compared to the edge of the bank etching layer disposed in the non-display area.

[0186] In the display device according to the embodiment of the present invention, the bank layer may include a bank opening in the light emitting portion of the display area, and the bank hole may be formed to be smaller than the bank opening by 1 / 3 to 1 / 5 of the bank opening.

[0187] According to an embodiment of the present invention, a bank etching layer is formed to cause disconnection of a hole injection layer in a display region, thereby preventing driving due to leakage current between adjacent sub-pixels.

[0188] Furthermore, the bank etching layer formed by deposition in the entire region of the substrate can prevent the lower connection line from being damaged when the bank layer is patterned by a photo process.

[0189] In the second area of ​​the non-display region, one or more bank holes are formed in the bank layer and the bank etching layer to connect the lower connection line and the second driving electrode, thereby preventing driving failure due to short circuit of the second driving electrode formed on the bank layer.

[0190] It should be noted that the effects of the present invention are not limited to those described above, and other effects are included in the present invention.

[0191] The features, structures, effects, etc. described in the above examples of the present invention are included in at least one example of the present invention, and the present invention is not necessarily limited to one example. In addition, those skilled in the art to which the present invention belongs may combine or modify the features, structures, effects, etc. described in at least one example into other examples. Therefore, the contents related to the combination or modification should be interpreted as included in the scope of the present invention.

[0192] The present invention described above is not limited to the above-mentioned embodiments and drawings, and it will be clear to those skilled in the art that various substitutions, modifications and changes can be made without departing from the technical spirit or scope of the present invention. Therefore, the scope of the present invention is represented by the claims described below, and the meaning and scope of the claims and all changes or modifications derived from their equivalents should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: A substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor comprising a gate electrode, a source electrode, and a drain electrode; A first intermediate layer and a second intermediate layer sequentially disposed on the thin film transistor; a light emitting element on the second intermediate layer, the light emitting element being connected to the thin film transistor and comprising a first driving electrode, an electroluminescent layer, and a second driving electrode; a lower connection line in the non-display area; a bank layer on the lower connection line; a power line connected to the second driving electrode through the lower connecting line, the power line having the same material as one of the gate electrode, the source electrode, and the drain electrode; at least two dam portions on the power supply line, each of the at least two dam portions comprising the first intermediate layer, the second intermediate layer, the bank layer and a spacer, and the first intermediate layer and the second intermediate layer of the at least two dam portions are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector surrounding the at least two dam portions in the non-display area, the rupture detector comprising a same material as one of the gate electrode, the source electrode, and the drain electrode; as well as The encapsulation layer on the light emitting element includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer, an end of the first encapsulation layer is arranged to be farther away from the display area than an end of the second encapsulation layer, and the first encapsulation layer overlaps the rupture detector.

2. The display device according to claim 1, further comprising a bank etching layer between the lower connection line and the bank layer, The second driving electrode is arranged to be separated from the bank etching layer. 3 . The display device of claim 1 , wherein the bank layer comprises a plurality of bank holes in the non-display area. 4 . The display device of claim 3 , wherein the plurality of bank holes are a plurality of holes separated from each other by the bank layer. 5 . The display device according to claim 3 , wherein the second driving electrode is connected to the lower connection line through the plurality of bank holes. 6 . The display device according to claim 3 , wherein the bank layer includes a bank opening portion in a light emitting portion of the display region, and the plurality of bank holes are more densely arranged than the bank opening portion. 7 . The display device according to claim 1 , wherein the semiconductor layer of the thin film transistor comprises one of an amorphous semiconductor material, a polycrystalline semiconductor material, and an oxide semiconductor material.

8. The display device according to claim 1, further comprising a source / drain metal pattern between the first intermediate layer and the second intermediate layer, The source / drain metal pattern on the first intermediate layer is connected to the power line, and the lower connection line on the second intermediate layer is connected to the source / drain metal pattern.

9. The display device according to claim 1, further comprising a hole injection layer on the first driving electrode and the bank layer, wherein the bank layer includes a bank opening portion in the display area and a plurality of bank holes in the non-display area, The size of the embankment opening is larger than the size of each of the multiple embankment holes, so that the hole injection layer on the first driving electrode is separated from the hole injection layer on the embankment layer, and the second driving electrode on the lower connecting line is connected to the second driving electrode on the embankment layer.

10. A display device, comprising: A substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor comprising a gate electrode, a source electrode, and a drain electrode; A first intermediate layer and a second intermediate layer sequentially disposed on the thin film transistor; a light emitting element on the second intermediate layer, the light emitting element being connected to the thin film transistor and comprising a first driving electrode, an electroluminescent layer, and a second driving electrode; a lower connection line in the non-display area; a bank layer on the lower connection line, the bank layer having a plurality of bank holes in the non-display area; a power line connected to the second driving electrode through the lower connecting line, the power line having the same material as one of the gate electrode, the source electrode, and the drain electrode; at least two dam portions on the power supply line, each of the at least two dam portions comprising the first intermediate layer, the second intermediate layer, the bank layer and a spacer, and the first intermediate layer and the second intermediate layer of the at least two dam portions are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector surrounding the at least two dam portions in the non-display area, the rupture detector comprising a same material as one of the gate electrode, the source electrode, and the drain electrode; as well as A packaging layer is provided on the light emitting element, wherein the packaging layer includes a first packaging layer, a second packaging layer and a third packaging layer, and the first packaging layer overlaps with the rupture detector.

11. The display device according to claim 10, further comprising a bank etching layer between the lower connection line and the bank layer, The second driving electrode is arranged to be separated from the bank etching layer. 12 . The display device of claim 10 , wherein the plurality of bank holes are a plurality of holes spaced apart from each other by the bank layer. 13 . The display device according to claim 10 , wherein the second driving electrode is connected to the lower connection line through the plurality of bank holes. 14 . The display device according to claim 10 , wherein the bank layer includes a bank opening portion in a light emitting portion of the display region, and the plurality of bank holes are more densely arranged than the bank opening portion. 15 . The display device according to claim 10 , wherein the semiconductor layer of the thin film transistor comprises one of an amorphous semiconductor material, a polycrystalline semiconductor material, and an oxide semiconductor material.

16. The display device according to claim 10, further comprising a source / drain metal pattern between the first intermediate layer and the second intermediate layer, The source / drain metal pattern on the first intermediate layer is connected to the power line, and the lower connection line on the second intermediate layer is connected to the source / drain metal pattern.

17. The display device according to claim 10, further comprising a hole injection layer on the first driving electrode and the bank layer, wherein the bank layer includes a bank opening portion in the display area and a plurality of bank holes in the non-display area, The size of the embankment opening is larger than the size of each of the multiple embankment holes, so that the hole injection layer on the first driving electrode is separated from the hole injection layer on the embankment layer, and the second driving electrode on the lower connecting line is connected to the second driving electrode on the embankment layer.

18. A display device comprising: A substrate having a display area including a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor in each of the plurality of sub-pixels, the thin film transistor comprising a gate electrode, a source electrode, and a drain electrode; A first intermediate layer and a second intermediate layer sequentially disposed on the thin film transistor; a light emitting element on the second intermediate layer, the light emitting element being connected to the thin film transistor and comprising a first driving electrode, an electroluminescent layer, and a second driving electrode; a lower connection line in the non-display area; a bank layer on the lower connection line, the bank layer having a plurality of bank holes in the non-display area; a power line connected to the second driving electrode through the lower connecting line, the power line having the same material as one of the gate electrode, the source electrode, and the drain electrode; at least two dam portions on the power supply line, each of the at least two dam portions comprising the first intermediate layer, the second intermediate layer, the bank layer and a spacer, and the first intermediate layer and the second intermediate layer of the at least two dam portions are separated from the first intermediate layer and the second intermediate layer in the display area; a rupture detector located at the outermost portion of the non-display area to surround the at least two dam portions and the power supply line, the rupture detector comprising the same material as one of the gate electrode, the source electrode, and the drain electrode; as well as The encapsulation layer on the light emitting element includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer.

19. The display device according to claim 18, further comprising a bank etching layer between the lower connection line and the bank layer, The second driving electrode is arranged to be separated from the bank etching layer. 20 . The display device of claim 18 , wherein the plurality of bank holes are a plurality of holes spaced apart from each other by the bank layer.

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