Voltage trimming for qubit control

Abstract

A quantum device including an array of quantum dots is disclosed. The quantum device comprises a silicon layer in which quantum dots (201) can be induced by respective gates; the grid electrode capable of inducing the quantum dots (201) is used for controlling and limiting the potential of the induced quantum dots (201); and an integrated circuit element (204), in particular an integrated circuit element (204) comprising a floating gate field effect transistor, for controlling the voltage of the respective gates, the integrated circuit element (204) having an adjustable non-volatile resistance value RF. The integrated circuit element (204) has an input voltage (Vin) and an output voltage (Vout), where the output voltage depends on the input voltage and the non-volatile resistance value RF of a different integrated circuit element. The integrated circuit elements (204) are electrically connected such that their respective output voltages are applied to the gates of the respective inducible quantum dots (201). Accordingly, the gate of each quantum dot may be addressed using a single input voltage.

Description

Technical Field

[0001] The present invention relates to a quantum device suitable for quantum computing. Background Art

[0002] Qubits are often arranged in dense arrays as part of a quantum device. In order to perform quantum computations using qubits in an array, each qubit must be addressable.

[0003] For small qubit arrays, each qubit can be addressed using a separate control line. However, this mechanism requires a lot of power and is therefore difficult to scale up for larger qubit arrays.

[0004] It is desirable to reduce the number of control lines and equipment needed to address the qubits within an array. This generally requires a certain degree of uniformity across the array.

[0005] There are often multiple input elements used to address qubits within the array, such as electron spin resonance and tunnel coupling. It is desirable for each input element to globally address the qubits in the array; however, each input may depend on qubit properties that vary across the array at the individual qubit level. Therefore, for each qubit in the array, each of the multiple input elements may need to be adjusted accordingly.

[0006] For example, in the case of electron spin qubits in silicon, it is desirable to be able to drive multiple qubits using a single frequency. However, such global control of electron spins is not easy to achieve due to the natural variation of the electron g-factor across the device. Although the g-factor can be tuned using an external electric field, the adjustable range for each qubit is typically at least an order of magnitude smaller than the overall g-factor variation across the entire device. Therefore, the application of a single frequency may only address 1–10% of the spin qubits in a device.

[0007] This problem can be solved using cavity amplitude modulation, which can be used to convert a single frequency input into multiple frequencies covering the range of electron g-factors. In this way, a single frequency can be effectively used to globally control the electron spins.

[0008] However, the above mechanism requires adjusting the voltage reference for each individual qubit, which, as mentioned above, is inefficient and difficult to scale.

[0009] It is desirable to manipulate arrays of qubits on a global scale. Summary of the invention

[0010] One aspect of the present invention provides a quantum device, comprising: a silicon layer, wherein a plurality of quantum dots can be induced in the silicon layer; a first gate of a first inducible quantum dot, used to control the potential defining the first induced quantum dot, wherein the first gate of the first inducible quantum dot is a plunger gate or a barrier gate; a second gate of a second inducible quantum dot, used to control the potential defining the second induced quantum dot, wherein the second gate of the second inducible quantum dot is a plunger gate or a barrier gate; a first integrated circuit element, used to control the voltage of the first gate; and a second integrated circuit element, used to control the voltage of the second gate. The first integrated circuit element has an adjustable first non-volatile resistance value R F . The second integrated circuit element has an adjustable second non-volatile resistance value. The first integrated circuit element has an input voltage and a first output voltage, wherein the first output voltage depends on the input voltage and the first non-volatile resistance value. The second integrated circuit element has an input voltage and a second output voltage, wherein the second output voltage depends on the input voltage and the second non-volatile resistance value. The first and second integrated circuit elements are electrically connected to the first and second gates, respectively, so that the first and second output voltages are applied to the first gate of the first inducible quantum dot and the second gate of the second inducible quantum dot, respectively.

[0011] For a fixed input voltage, adjusting the resistor value can modify the output voltage applied to the inducible quantum dot gate. Advantageously, this means that the output voltage can be tuned based on the physical and electronic properties of each inducible quantum dot.

[0012] The resistance value is non-volatile. This means that once the resistance value is adjusted, the resistance value remains stable and fixed. Those skilled in the art will understand that the term "non-volatile" in this context means that the resistance value of the integrated circuit element, i.e. the encoded memory state, can be maintained in the absence of power input. Therefore, a memory state can be encoded and that state can be maintained.

[0013] The non-volatility of the resistance value has the advantage that the resistance value can be adjusted to a set value and then maintained for a long time. The resistance value can be maintained at a fixed value during the life of the quantum circuit, and at least for the duration of the quantum computation performed using the quantum device. The resistance value can be readjusted as needed, although advantageously, readjustment is not necessary if a fixed resistance value is required; the resistance value does not need to be refreshed. The integrated circuit element advantageously provides an addressable, non-volatile analog memory that is capable of providing a constant direct current (DC) voltage offset to the quantum dots in the quantum device.

[0014] The gate of the inducible quantum dot is a gate for controlling the potential that defines the induced quantum dot. Preferably, the quantum dot that can be induced in the silicon layer is a gate-defined quantum dot. Typically, the gate-defined quantum dot has multiple gates to confine the quantum charge carriers in the quantum dot. Typically, one or more gates used to define the quantum dot are arranged so that the quantum dot can be induced when a suitable bias potential is applied to the gate. The gate of the inducible quantum dot is optionally a plug gate. The plug gate can be used to raise or lower the potential well of the quantum dot to reduce or increase the number of charge carriers confined in the quantum dot, respectively.

[0015] Advantageously, applying a customized output voltage to the plunger gate of the inducible quantum dot can be used to configure the induced quantum dot so that during device operation, one and only one electron is confined in the quantum dot. To achieve this, the non-volatile resistance value of the integrated circuit element is preferably adjusted so that the output voltage applied to the plunger gate is higher than the voltage V required to capture or confine one electron. 1e , and is lower than the voltage V required to capture or confine two electrons 2e . V 1e and V 2e This can vary from one quantum dot to the next, and the variation can be significant.

[0016] Optionally, the gate of the inducible quantum dot is a barrier gate. The barrier gate can be used to raise or lower an electrostatic potential barrier to reduce or increase the coupling strength between the quantum dot and an adjacent confinement region, the electrostatic potential barrier defining the edge of the potential well of the quantum dot. The adjacent confinement region can be a zero-dimensional confinement region (i.e., another quantum dot), a one-dimensional confinement region (e.g., an elongated quantum dot), or a two-dimensional confinement region (i.e., a charge carrier storage pool).

[0017] Advantageously, a customized output voltage can be applied to the barrier gate of the inducible quantum dots to adjust the coupling strength, depending on the performance requirements. For example, the height of the electrostatic barrier between two adjacent quantum dots can be reduced by modifying the output voltage applied to the barrier gate, thereby enabling the two qubits to interact. The desired output voltage applied to the barrier gate will vary across the quantum device, so it is beneficial to be able to modify the voltage applied to the barrier gate as needed.

[0018] Optionally, an inducible quantum dot may have more than one barrier gate to define multiple edges of the potential well of the quantum dot. For example, an inducible quantum dot may be defined by a plunger gate and two barrier gates. Each of the barrier gate and the plunger gate may have a corresponding integrated circuit element for controlling the voltage of the gate. Preferably, the non-volatile resistance value of each integrated circuit element can be independently adjusted. Advantageously, the adjustment of each integrated circuit element provides a mechanism by which changes in quantum dot properties on the device can be met at the level of a single quantum dot.

[0019] The properties of the induced quantum dots can vary significantly in a quantum device depending on their location within the device and any differences introduced during fabrication. For example, the electronic g factor can vary significantly due to differences in the silicon and silicon oxide layers (Si / SiO x ) varies due to the surface roughness of the interface between the two electrodes, even on the scale of a single atomic step. Single-atom displacements in the interface (i.e., steps of a single atom) result in a reversal of the sign of the Dresselhaus coefficient (β), but the Rashba coefficient (α) remains unchanged. The electronic g-factor and Stark shift in the relative valleys of the same point are also significantly different. Similarly, the first electron energy can vary across the device due to changes in the fundamental physical properties of the device. In addition, the second electron energy can vary across the device for similar reasons. In addition, the tunnel coupling properties between adjacent confined regions in the device (such as quantum dots or charge storage pools) can change due to changes in the surface roughness or other physical properties of the device. The output voltage applied to the tunnel barrier may need to be adjusted to account for changes in the tunnel coupling strength.

[0020] The quantum device is a silicon-based quantum device having a silicon layer. For example, the silicon layer can be intrinsic silicon, isotopically pure silicon Si 28 (isotopicallypure silicon Si 28 Quantum devices typically include additional layers to support the silicon layer and to provide control circuitry.

[0021] The integrated circuit element has an adjustable non-volatile resistance value. This can be achieved by adjusting the threshold voltage of the integrated circuit element. A gate voltage can be applied to the integrated circuit element. If the gate voltage is greater than the threshold voltage of the n-type integrated circuit element, the integrated circuit element is "on". If the gate voltage is lower than the threshold voltage of the n-type integrated circuit element, the integrated circuit element is "off". Below the threshold voltage, i.e., in the sub-threshold range, the channel resistance of the circuit element is high and generally increases exponentially as the gate voltage decreases. The channel resistance of the circuit element is a non-volatile resistance value.

[0022] Integrated circuit components can be n-type, p-type or bipolar. If the gate voltage is lower, i.e. more negative, than the threshold voltage of a p-type integrated circuit component, the integrated circuit component is "on". If the gate voltage is higher than the threshold voltage of a p-type integrated circuit component, the integrated circuit component is "off". Bipolar integrated circuit components have two threshold voltages. Below a first threshold voltage, the integrated circuit component is "on" and the transmission is p-type, i.e. the charge carriers are holes. Between the first threshold voltage and the second threshold voltage, the integrated circuit is "off". Above the second threshold voltage, the integrated circuit component is "off" and the transmission is n-type, i.e. the charge carriers are electrons.

[0023] The integrated circuit element is electrically connected to the gate so as to apply an output voltage to the gate of the inducible quantum dot. When the quantum dot is induced in the silicon layer, the integrated circuit element is electrically connected to the induced quantum dot.

[0024] The output voltage controls the gate voltage, which controls the potential that defines the quantum dot. In the example where the gate is a plunger gate, the output voltage is typically adjusted so that the quantum dot contains one electron (i.e., the dot is filled), or contains zero electrons (i.e., the dot is empty). This is typically achieved by modifying the input voltage.

[0025] Preferably, the quantum device is fabricated using complementary metal-oxide-semiconductor (CMOS) manufacturing technology, which advantageously facilitates the production of the device.

[0026] Optionally, the integrated circuit element includes a field-effect transistor (FET). FETs typically include three terminals: a gate, a source, and a drain. Optionally, the input and output voltages correspond to the source terminal and the drain terminal. Current flows between the source and the drain, characterized by a channel resistance. The channel resistance is determined by the applied gate voltage (i.e., the gate voltage applied to the integrated circuit element) and the threshold voltage, and the channel resistance is non-volatile and adjustable. Different types of FETs may be suitable for use as integrated circuit elements. Preferably, the integrated circuit element is non-volatile and has long-term charge stability.

[0027] Preferably, the integrated circuit element comprises an electrically isolated element capacitively coupled to the source-drain channel and the gate via close mixing. The electrically isolated element can advantageously be charged and discharged to encode different non-volatile memory states. Advantageously, the encoded memory state does not require refreshing to maintain.

[0028] For example, the first and / or second integrated circuit element may include a floating gate metal-oxide-semiconductor (FGMOS) field effect transistor. The integrated circuit element may be an FGMOS. An FGMOS typically includes a control gate and a floating gate (also referred to as a floating island). The floating gate typically provides an electrically isolated element of the integrated circuit element. Advantageously, FGMOS devices have shown hysteresis behavior, resulting in an adjustable and non-volatile resistance value.

[0029] Typically, the electrically isolated element can be charged or discharged to adjust the resistance value. The charging and discharging of the electrically isolated or "floating" element preferably modifies the threshold voltage so that for a fixed gate voltage applied to the integrated circuit element, the resistance value is modified. The programmed charge state of the electrically isolated element is typically non-volatile and stable. This property enables the adjustable resistance value to be adjusted to a set resistance value and maintained at the set resistance value over time, thereby ensuring stable, reliable operation of the quantum device.

[0030] Alternatively, the first and / or second integrated circuit element may include a gate-defined multi-quantum dot device. Advantageously, it has also been found that these devices exhibit hysteresis behavior. The resistance value of the multi-quantum dot device can be adjusted to a set resistance value and maintained at the set resistance value for a long time. Hysteresis behavior involves the ability to move the threshold voltage to a more positive (more positive) or more negative (more negative) value to adjust the channel resistance value of the integrated circuit element. Optionally, the gate-defined multi-quantum dot device may include a silicon nanowire. Typically, the gate-defined multi-quantum dot device includes multiple gates.

[0031] The quantum device is preferably arranged so that the induced quantum dots have a fixed resistance (for a fixed temperature) and the integrated circuit element has a variable resistance. The induced quantum dots and the integrated circuit element are preferably arranged so that the voltage applied to the induced quantum dots is less than the voltage applied to the integrated circuit element. By adjusting the modifiable resistance value of the integrated circuit element to control the output voltage, the level of reduction can be controlled.

[0032] Preferably, the first induced quantum dot has a first resistance value R D The resistance value of the induced quantum dot R D Usually depends on the temperature of the quantum device: As the temperature decreases, the first resistance value R D The first resistance value may increase. Quantum computing is usually performed at cryogenic temperatures, so the first resistance value is usually large. For example, at 4 Kelvin, the first resistance value may be about 1×10 6 to 1×10 9 Advantageously, the resistance value is nonvolatile even at low temperatures, so the set resistance value can be maintained at the device operating temperature.

[0033] Non-volatile resistance value, that is, the channel resistance R of the integrated circuit component F , usually depends on the threshold voltage. For a fixed input voltage and an n-type integrated circuit component, for a larger threshold voltage, the nonvolatile resistor value R F Larger. The integrated circuit element preferably operates in the deep sub-threshold range. This means that during the operation of the quantum device, the gate voltage is preferably below the threshold voltage. In the sub-threshold range, the channel resistance of the integrated circuit element generally increases exponentially with decreasing gate voltage.

[0034] The integrated circuit components and the induced quantum dots are preferably arranged so that the input voltage is distributed between the components. The device may be referred to as a resistor divider, a voltage divider, or a potential divider. In such a device, the first output voltage V out Preferably with input voltage V in proportional to, where the proportionality constant is equal to R D / (R F +R D ).

[0035] Advantageously, when the integrated circuit element operates in the deep subthreshold range, the nonvolatile resistor R F is large and can be adjusted to match the large fixed resistance R of the quantum dot D This means that the possible output voltage V outThe quantum dot can be empty or full, depending on the range of electrons in the dot. Usually, "empty" means there are no electrons in the dot, and "full" means there is one electron in the dot. In general, it is possible for more than one electron to be confined in a quantum dot, but this is usually avoided if the quantum dot is to be used as a qubit in a quantum device.

[0036] The quantum device may further include a regulating field effect transistor FET, wherein the regulating FET is electrically connected to the first or second integrated circuit element. The regulating FET may be configured to enable or disable a regulating voltage of the first or second integrated circuit element, respectively.

[0037] The regulating FET can be advantageously used to enable or disable the regulating voltage by charging and discharging the integrated circuit element. Specifically, the regulating FET can be used to charge and discharge the floating element of the integrated circuit element. Typically, the output of the regulating FET is connected to the gate of the integrated circuit element. For example, the regulating FET may include a source, a drain, and a gate terminal, and the drain terminal of the regulating FET may be connected to the control gate of the FGMOS. The regulating FET preferably acts as a switch. When the regulating FET is "off", the voltage applied to the source terminal of the regulating FET is not transmitted, and the regulating voltage or regulating signal is disabled. When the regulating FET is "on", current can flow between the source terminal and the drain terminal of the regulating FET, so that the voltage applied to the source terminal can be transmitted to the drain terminal which can be connected to the integrated circuit element. Therefore, when the regulating FET is "on", the regulating voltage or regulating signal is enabled.

[0038] The adjustment FET can be used to adjust the non-volatile resistance value of the integrated circuit element to control the occupancy of the quantum dot by modifying the voltage applied to the quantum dot gate. The first and second quantum dots of the quantum device can be induced in the silicon layer, and the first and / or second induced quantum dots are preferably suitable for use as qubits. The quantum dots are preferably gate-defined quantum dots, and the gate voltage of the induced quantum dots can be modified to add electrons or remove electrons from the dots. If the quantum dots are filled, the quantum dots may be suitable for use as qubits. For example, the qubit can be an electron spin qubit. In this example, the two measurable states of the qubit are spin up and spin down. Therefore, the induced quantum dots can advantageously provide carriers of quantum information in quantum devices.

[0039] In order to address and manipulate qubits to perform quantum operations, the quantum device optionally includes a qubit pulse control circuit configured to modify the state of the first and / or second qubit. The qubit pulse control circuit is preferably electrically connected between the first and / or second integrated circuit element and the first and / or second induced quantum dot, respectively. Preferably, the qubit pulse control circuit is electrically connected between the integrated circuit element and the gate of the inducible quantum dot. As part of quantum computing, the combination of the qubit pulse control circuit advantageously provides a mechanism for controlling the state of the qubit. The qubit pulse control circuit can be coupled using a bias-tee configuration, for example, the qubit pulse control circuit can be electrically connected using a capacitor to provide AC (Alternating Current) coupling. The qubit pulse control circuit can include, for example, an arbitrary waveform generator (AWG). The AWG can be used to provide a signal to the quantum device to control the state of one or more qubits.

[0040] In addition, in order to read out the state of the qubit, the quantum device optionally includes a qubit readout control circuit configured to read out the state of the first and / or second qubit. The qubit readout control circuit is preferably connected between the first and / or second integrated circuit element and the first and / or second induced quantum dot, respectively. Preferably, the qubit readout control circuit is electrically connected between the integrated circuit element and the gate of the inducible quantum dot. The combination of the qubit readout control circuit advantageously allows the state of the qubit to be read out or inferred as part of quantum computing. For example, after performing one or more quantum operations on the qubit, the state of the qubit can be read out. For example, the qubit readout control circuit may include an inductor and a capacitor. The qubit readout control circuit may include an LC (inductor-capacitor) resonator circuit, also known as a tank circuit, an LC resonator, or a resonator circuit.

[0041] There are multiple qubits involved in quantum computing. Therefore, a quantum device includes multiple quantum dots that act as qubits.

[0042] The first output voltage is applied to the first gate of the first inducible quantum dot. The second output voltage is applied to the second gate of the second inducible quantum dot. Alternatively, both the first and second gates can be used to control the potential defining the same inducible quantum dot. For example, the first gate can be a plunger gate of the first inducible quantum dot and the second gate can be a barrier gate of the first inducible quantum dot. In this alternative example, the first output voltage is applied to the plunger gate of the first inducible quantum dot and the second output voltage is applied to the barrier gate of the first inducible quantum dot.

[0043] This advantageously allows global control of the quantum dots. The same input voltage can be used to apply two output voltages; the first and second output voltages can be different. The first and second non-volatile resistance values ​​can be adjusted to control the respective voltages of the first and second gates of the first and second induced quantum dots, respectively, based on their properties. Beneficially, this provides the ability to adjust the first and second output voltages based on the properties of the first and second inducible quantum dots, respectively. If the first and second inducible quantum dots have similar properties, the first and second output voltages can be similar.

[0044] More generally, any number of quantum dots can be induced in the silicon layer, subject to practical manufacturing constraints. For example, the device can be configured so that approximately 10 9 quantum dots. For each gate of the inducible quantum dot, the quantum device preferably includes a corresponding integrated circuit element for applying a voltage to the gate of the induced quantum dot. There are usually multiple inducible quantum dots and multiple gates for defining each quantum dot. Each integrated circuit element usually has an adjustable non-volatile resistance value. Each integrated circuit element preferably has the same input voltage. The output voltage of each integrated circuit element usually depends on the input voltage and non-volatile resistance value of the integrated circuit element. Each integrated circuit element is preferably arranged so that the output voltage is applied to the corresponding gate of the inducible quantum dot. Advantageously, when the quantum device includes an integrated circuit element for each gate of the inducible quantum dot, the voltage of each gate can be individually customized using a single input voltage.

[0045] In another example, a quantum device may have a unit cell configuration, where each unit cell typically contains two or more quantum dots, and the unit cell is repeated in a one-dimensional or two-dimensional array. The quantum device optionally has two or more input voltages corresponding to each quantum dot in the unit cell. This configuration advantageously provides a mechanism for performing complex operations between multiple qubits while reducing the required control circuitry.

[0046] In another example, each quantum dot in the array may be defined by a plunger gate and two barrier gates. A first input voltage may be used to address the plunger gate of each quantum dot in the array. Second and third input voltages may be used to address first and second barrier gates, respectively, for each quantum dot in the array. Each gate preferably has a corresponding integrated circuit component to adjust the output voltage applied to the gate.

[0047] If the quantum device includes more than one gate and / or more than one inducible quantum dot, the quantum device may further include a crossbar array configured to selectively electrically connect to the first and / or second integrated circuit elements. The selective electrical connection advantageously allows individual adjustment of the first and / or second integrated circuit elements to take into account their different properties.

[0048] Another aspect of the present invention provides a method for using a quantum device, the quantum device comprising: a silicon layer, in which a plurality of quantum dots can be induced; a first gate of a first inducible quantum dot, used to control the potential defining the first induced quantum dot, wherein the first gate of the first inducible quantum dot is a plug gate or a barrier gate; a second gate of a second inducible quantum dot, used to control the potential defining the second induced quantum dot, wherein the second gate of the second inducible quantum dot is a plug gate or a barrier gate; a first integrated circuit element, used to control the voltage of the first gate, the first integrated circuit element having an adjustable first non-volatile resistance value R F ; a second integrated circuit element for controlling the voltage of the second gate, the second integrated circuit element having an adjustable second non-volatile resistance value; and a cross-type array for selecting one or more integrated circuit elements. The method includes: inducing first and second quantum dots; selecting a first integrated circuit element; adjusting the first non-volatile resistance value of the first integrated circuit element to a first set non-volatile resistance value; selecting a second integrated circuit element; adjusting the second non-volatile resistance value of the second integrated circuit element to a second set non-volatile resistance value; applying an input voltage to the first and second integrated circuit elements, wherein a first output voltage of the first integrated circuit element and a second output voltage of the second integrated circuit element depend on the input voltage and the first and second set non-volatile resistance values, respectively; applying the first output voltage of the first integrated circuit element to the first gate of the first induced quantum dot; and applying the second output voltage of the second integrated circuit element to the second gate of the second induced quantum dot.

[0049] Adjusting the resistance value of the integrated circuit element can modify the corresponding output voltage. The advantage of this method is that the non-volatile resistance value can be controlled to control the voltage applied to the gate that can induce the quantum dot according to the specific properties of the quantum dot.

[0050] The set point of the non-volatile resistance value can be chosen so that the qubit resonance line is targeted. It is desirable to apply the drive frequency globally to the qubit, but the qubit resonance varies according to the electronic g factor, which often varies widely across the device. Advantageously, this approach can be used to provide a customized voltage to each quantum dot in a quantum device to control the occupancy of the quantum dot.

[0051] The set point of the nonvolatile resistance value can be selected according to alternative requirements, such as target tunnel coupling strength, etc. For example, for a specific potential well, the barrier height required to provide a specific tunnel coupling strength can be different depending on the device properties in the region where the potential well is formed. Therefore, the quantum device requires a different output voltage.

[0052] Typically, the nonvolatile resistor value can be selected to produce different output voltages from the same input voltage for any selected output requirement. Different output voltages are often required due to variations in the electronic and / or physical properties of the quantum device. Typically, a quantum device can have multiple input voltages corresponding to different functions.

[0053] Optionally, if the quantum device further comprises an adjustment field effect transistor (FET) comprising a source terminal, a drain terminal and a gate terminal, the step of adjusting the first or second non-volatile resistance value of the first or second integrated circuit element to the first or second set non-volatile resistance value, respectively, may comprise: enabling the adjustment FET by applying a voltage to the gate terminal of the adjustment FET to allow current to pass between the source terminal and the drain terminal of the adjustment FET; and applying the adjustment voltage to the adjustment FET. The adjustment FET is preferably configured to enable or disable the adjustment voltage of the integrated circuit element. The adjustment FET is preferably electrically connected to the first or second integrated circuit element so that applying the adjustment voltage to the enabled adjustment FET modifies the non-volatile resistance value of the first or second integrated circuit element, respectively. Preferably, applying the adjustment voltage to the enabled adjustment FET modifies the channel resistance of the integrated circuit element, while applying the adjustment voltage to the disabled adjustment FET does not modify the channel resistance of the integrated circuit element. The first and second set non-volatile resistance values ​​are typically dependent on the adjustment voltage.

[0054] The regulating FET includes a source terminal, a drain terminal and a gate terminal. The regulating FET can be n-type, p-type or bipolar. Enabling an n-type regulating FET typically includes applying a voltage greater than the threshold voltage of the regulating FET to the gate terminal. This turns the regulating FET "on". In this state, the channel resistance of the regulating FET is low and there is a conductive path between the source and drain terminals. Once the regulating FET is enabled, the regulating voltage applied to the source terminal of the regulating FET can be passed to the integrated circuit element. Preferably, the drain terminal of the regulating FET is electrically connected to the gate terminal of the integrated circuit element. For example, this can be a control gate or a top gate.

[0055] The enabled regulation FET can be advantageously used to adjust the resistance value by charging and discharging the integrated circuit element. The enabled regulation FET can be used to charge and discharge the electrically isolated element of the integrated circuit element. For example, if the integrated circuit element is an FGMOS device, charge may accumulate on the floating gate and the level of charge will affect the threshold voltage, which will affect the channel resistance of the device. The channel resistance is typically a non-volatile resistance value. The floating gate that holds the accumulated charge is capacitively coupled to the location of the quantum dot. This directly adds a voltage potential V to the quantum dot based on the charge Q held by the floating gate and the capacitive coupling C. FG , where V FG =Q / C.

[0056] Optionally, the quantum device can be configured so that there are multiple inducible quantum dots in the silicon layer. For example, the gate can be a first gate of a first inducible quantum dot, used to control the potential defining the first induced quantum dot; and the integrated circuit element can be a first integrated circuit element, which is used to control the voltage of the first gate, and the first integrated circuit element has an adjustable first non-volatile resistance value. Optionally, a second quantum dot can be induced in the silicon layer, and the quantum device also includes: a second gate of a second inducible quantum dot, used to control the potential defining the second induced quantum dot; a second integrated circuit element, used to control the voltage of the second gate. The second integrated circuit element preferably has an adjustable second non-volatile resistance value. The quantum device may also include a cross array, which is used to select one or more integrated circuit elements.

[0057] For a quantum device including first and second inducible quantum dots, the method generally includes: selecting a first integrated circuit element; adjusting a first nonvolatile resistance value of the first integrated circuit element to a first set nonvolatile resistance value; selecting a second integrated circuit element; adjusting a second nonvolatile resistance value of the second integrated circuit element to a second set nonvolatile resistance value; applying an input voltage to the first and second integrated circuit elements, wherein a first output voltage of the first integrated circuit element and a second output voltage of the second integrated circuit element depend on the input voltage and the first and second set nonvolatile resistance values, respectively; applying the first output voltage of the first integrated circuit element to a first gate of the first inducible quantum dot; and applying the second output voltage of the second integrated circuit element to a second gate of the second inducible quantum dot.

[0058] The method advantageously allows global control of the induced quantum dots. The same input voltage can be used to apply two different output voltages. Advantageously, different g-factors, electron energies, and tunnel coupling strengths can be addressed with different output voltages using the same input voltage. Typically, different input voltages are used to address different functions, for example, one input voltage can be used to apply multiple output voltages to address different tunnel coupling strengths, while another input voltage can be used to apply multiple output voltages to address different first electron energies. The first and second non-volatile resistance values ​​can be adjusted to first and second set non-volatile resistance values ​​to control the voltage of the first and second gates of the corresponding induced quantum dots. Thus, the gates of the quantum dots can be individually addressed using a single input voltage.

[0059] Typically, a quantum device may include: n inducible quantum dots, m gates for each quantum dot, and m×n integrated circuit elements, each gate of the quantum dot being electrically connected to a corresponding integrated circuit element. In an alternative example, the number of gates for each inducible quantum dot may vary in the quantum device. For example, a barrier gate may provide a barrier for two adjacent quantum dots. Typically, the method may include selecting each integrated circuit element in turn and adjusting its non-volatile resistance value to its set value. Subsequently, the method may typically include applying an input voltage to the m×n integrated circuit elements; the output voltage applied to the quantum dot gate depends on the input voltage and the set non-volatile resistance value. The method advantageously provides global control of the quantum dot array. One input voltage can be used to apply multiple output voltages to quantum dots with different properties. This advantageously reduces the complexity of the method and reduces the required control circuitry.

[0060] Optionally, there may be m input voltages. Typically, each input voltage may be applied to n integrated circuit elements, wherein each of the n integrated circuit elements corresponds to an inducible quantum dot and each of the m input voltages corresponds to a gate having a different function.

[0061] One aspect of the present invention provides a quantum device, comprising: a silicon layer in which quantum dots can be induced; a gate for inducing quantum dots, for controlling an electric potential defining the induced quantum dots; and an integrated circuit element for controlling a gate voltage. The integrated circuit element has an adjustable nonvolatile resistance value R F The integrated circuit element has an input voltage and an output voltage, wherein the output voltage depends on the input voltage and the value of the nonvolatile resistor. The integrated circuit element is electrically connected to the silicon layer so that the output voltage is applied to the gate of the inducible quantum dot.

[0062] Another aspect of the present invention provides a method of using a quantum device, the quantum device comprising: a silicon layer in which quantum dots can be induced; a gate of the inducible quantum dots for controlling the potential defining the induced quantum dots; and an integrated circuit element for controlling the gate voltage, the integrated circuit element having an adjustable non-volatile resistance value. The method comprises: adjusting the non-volatile resistance value of the integrated circuit element to a set non-volatile resistance value; applying an input voltage to the integrated circuit element, wherein the output voltage of the integrated circuit element depends on the input voltage and the set non-volatile resistance value; and applying the output voltage of the integrated circuit element to the gate of the inducible quantum dots.

[0063] BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0065] Figure 1 A circuit diagram of a prior art quantum device;

[0066] Figure 2 A circuit diagram for a quantum device;

[0067] Figure 3 A circuit diagram for a quantum device;

[0068] Figure 4 A circuit diagram for a quantum device;

[0069] Figure 5 A circuit diagram for a quantum device; and

[0070] Figure 6 A cross-sectional side view of an integrated circuit component. DETAILED DESCRIPTION

[0071] Figure 1 A circuit diagram of a prior art quantum device. The device is described in “Silicon CMOS architecture for a spin-based quantum computer” by Veldhorst et al., DOI: 10.1038 / s41467-017-01905-6 (2017). Figure 1 Four quantum dots QD1, QD2, QD3, QD4 are shown. Each quantum dot QD1, QD2, QD3, QD4 is a single quantum dot and is schematically shown as a resistor R D and capacitor C D The resistance and capacitance of each quantum dot are typically different. The quantum dots QD1-QD4 can be addressed using word lines and bit lines 101-105 connected to the quantum dots QD1-QD4 through transistors 106-109. Each transistor 106-109 has a source terminal, a drain terminal, and a gate terminal.

[0072] Figure 1 A word line 101 is shown electrically connected to the source terminals of four transistors 106, 107, 108, 109. Each bit line 102, 103, 104, 105 is electrically connected to the gate terminal of transistors 106, 107, 108, 109. Each quantum dot QD1, QD2, QD3, QD4 is electrically connected to the drain terminal of transistors 106, 107, 108, 109. For example, the gate terminal of the first transistor 106 is electrically connected to the first bit line 102; the source terminal of the first transistor 106 is electrically connected to the word line 101; and the drain terminal of the first transistor 106 is electrically connected to the first quantum dot QD1.

[0073] Bit lines 102-105 can be used to address individual quantum dots QD1-QD4. This can be done by applying a bias potential V to the associated bit line. B1 、VB2 、V B3 and V B4 When the appropriate bias potential is applied to the bit line, the electrically connected transistor is turned on. When the transistor is on, the channel resistance (i.e., the resistance between the source and drain terminals of the transistor) is low. When the transistor is off, the channel resistance is high.

[0074] For example, to address the second quantum dot QD2, a bias potential V may be applied to the second bit line 103. B2 Apply a sufficiently large bias potential V to the second bit line 103 B2 To turn on the second transistor 107. When the second transistor 107 is turned on, current can flow between the word line 101 and the second quantum dot QD2 because the channel resistance is low. The current flow will depend on the bias potential V applied to the word line 101. W : Apply a large bias potential V W Will increase current flow.

[0075] Figure 1 The quantum device shown includes charge storage electrodes 111, 112, 113, 114 or floating memory gate electrodes. When transistors 106-109 are turned on, the bias potential V applied to word line 101 can be controlled. W , to charge or discharge the electrically connected charge storage electrodes 111-114. The charging or discharging of the charge storage electrodes 111-114 can be used to adjust the electrical properties of the electrically connected quantum dots QD1-QD4.

[0076] The charge storage electrodes 111-114 are adjusted so that the voltage applied to the quantum dots QD1-QD4 is within the acceptable range for qubit control. However, the voltage on the charge storage electrodes 111-114 decays according to the voltage decay time constant T=RC, where R is the resistance of the quantum dot R. D The total resistance, where C is the quantum dot capacitance C D and other parasitic capacitances within the quantum device. The total capacitance C typically includes the input capacitance on the source side of transistors 106-109. Because the voltage on the charge storage electrodes 111-114 decays, the applied voltage must be refreshed periodically to keep the voltage within an acceptable range. The decay may be due to leakage or coupling to capacitance changes in nearby structures. The system is similar to a dynamic random access memory (DRAM) system.

[0077] In order to refresh the charge levels on the charge storage electrodes 111-114 to recondition the memory after decay, the transistors 106-109 must be re-enabled using the bit lines and word lines 101-105. Figure 1 The quantum device shown in can be used to individually adjust qubits in a qubit array. However, this solution has many disadvantages. For example, the periodic refresh of the volatile memory elements (charge storage electrodes 111-114) requires a large amount of control circuitry to be enabled periodically during device operation. This results in relatively high power consumption. In addition, when the desired control signal is applied, it is difficult to achieve the initial writing of the individual adjustment points to the charge storage electrodes 111-114 and to keep them from being destroyed.

[0078] Figure 2 1 is a circuit diagram showing a portion of a quantum device according to an embodiment of the present invention. The circuit includes a quantum dot 201, which is a single quantum dot. By applying a bias potential V to the quantum dot 201, out , a quantum dot 201 can be induced in a silicon layer (not shown). When the quantum dot 201 is occupied by a single electron, the induced quantum dot 201 is suitable for use as a qubit in a quantum device. A voltage is applied to the plunger gate of the quantum dot to raise or lower the potential well of the quantum dot, thereby reducing or increasing the number of confined electrons. The plunger gate voltage required to occupy the quantum dot 201 with a single electron depends on the properties of the quantum dot 201.

[0079] The quantum dot 201 schematically shows a resistor 202 and a capacitor 203 arranged in parallel. The quantum dot 201 is electrically grounded. The resistor 202 has a resistance R D ; Capacitor 203 has a capacitance C D . Resistance R D and capacitor C D depends on the properties of the quantum dot 201. Thus, for a typical device comprising an array of quantum dots used as qubits, the resistance and capacitance of each quantum dot varies across the array.

[0080] Figure 2 The circuit shown also includes an integrated circuit element 204. The integrated circuit element 204 has a source terminal, a drain terminal, and a gate terminal. In this example, the integrated circuit element 204 has two gate terminals: a control gate terminal and a floating gate terminal. The control gate is electrically connected to a voltage source (not shown). The floating gate is an electrically isolated element that is capacitively coupled by close proximity to the control gate and the source and drain terminals.

[0081] The integrated circuit element 204 has an adjustable non-volatile resistance value R F, can be used to encode memory states in a quasi-analogue manner. During the operation of the quantum device, the non-volatile resistance value can be adjusted and maintained for a long time. Quantum devices are typically operated at cryogenic temperatures. Integrated circuit element 204 provides a flash memory-like element that is stable for a long time at the device operating temperature. This eliminates the need to refresh the memory state because once the memory state has been encoded, there is almost no decay. The set memory state will not drift significantly over time.

[0082] Non-volatile resistance R F is the channel resistance of the integrated circuit element 204. F The input voltage V in can be applied to the source terminal of the integrated circuit element 204. The output voltage V out Depends on the adjustable channel resistance R F (i.e., the resistance between the source and drain terminals), and the resistance R of the quantum dot 201 D .

[0083] In this example, the integrated circuit element 204 is an n-type field effect transistor. The integrated circuit element 204 has a threshold voltage V th When a bias potential below the threshold voltage is applied to the control gate, the integrated circuit element 204 is “off” and the channel resistance R F Very large. In the subthreshold range, as the gate voltage decreases, the channel resistance R F When a bias potential above the threshold voltage is applied to the control gate, the integrated circuit element 204 is turned “on” and the channel resistance R F Very small. During normal operation of a quantum device, i.e. when performing quantum operations, the integrated circuit components are in the subthreshold range.

[0084] The nonvolatile resistance value R of the integrated circuit element 204 can be adjusted by adjusting the charge on the electrical isolation element. F The electrically isolated element can be charged and discharged by adjusting the bias potential applied to the control gate. For a particular control gate voltage applied to the integrated circuit element 204, the larger the channel resistance R F Corresponding to the more positive threshold voltage V of n-type integrated circuit components th Therefore, the channel resistance R can be modified by changing the threshold voltage F , which is achieved by changing the charge level on the electrically isolated components.

[0085] therefore, Figure 2 The circuit shown provides a resistor divider. The input voltage V in According to the resistance R of the quantum dot 201 D and the channel resistance R of the integrated circuit element 204 F The output voltage V of the integrated circuit element 204 is reduced. out Depends on the input voltage V in and nonvolatile resistance R F . The output voltage V out Applied to the gate of the induced quantum dot 201, the output voltage V can be calculated according to the following formula out .

[0086]

[0087] The resistance element R of the quantum dot 201 D It is usually due to the accumulated leakage to electrical ground present in complementary metal oxide semiconductor (CMOS) manufacturing technology. D Depends on the temperature. At cryogenic temperatures, R D Usually very large. In order to operate from a single input voltage V in Provides a range of output voltage V out , channel resistance R F Therefore, the integrated circuit element 204 generally operates in a deep subthreshold regime.

[0088] exist Figure 2 In the example shown, the gate of the quantum dot 201 is electrically connected to the drain terminal of the integrated circuit element 204. In an alternative example, the gate of the quantum dot may be electrically connected to an electrically isolated element, and the drain terminal may be electrically grounded.

[0089] Figure 3 FIG. 1 is a circuit diagram showing a portion of a quantum device according to an embodiment of the present invention. The circuit includes four quantum dots 301, 302, 303 and 304, each of which is schematically shown as a parallel arrangement with a resistance R n The resistor and capacitor C n capacitor, where n = 1, 2, 3, 4. Due to manufacturing tolerances and underlying material properties, the resistance R of each quantum dot 301-304 n and capacitor C n Each of the quantum dots 301-304 is electrically grounded and can be induced in the silicon layer of the quantum device by applying a suitable voltage to the gate used to define the quantum dot.

[0090] Figure 3The quantum device shown includes an inducible quantum dot array including a first quantum dot 301, a second quantum dot 302, a third quantum dot 303, and a fourth quantum dot 304. When occupied by a single electron, each of the quantum dots 301-304 can be used as a qubit in the quantum device. The occupation is controlled by controlling the voltage V supplied to the plunger gate of the quantum dot, such that V 1e ≤V <V 2e , where V 1e is the minimum voltage required to occupy a quantum dot with one electron, V 2e is the minimum voltage required to occupy a quantum dot with two electrons.

[0091] In this example, the array is a one-dimensional array. However, in an alternative example, the array is a two-dimensional array. Individual quantum dots can be addressed within the array using a crossbar array including bit lines and word lines. Alternatively, two or more quantum dots can be grouped together so that the bit lines and word lines address more than one quantum dot at the same time. This helps reduce the required circuitry. Figure 3 A bit line 305 and a word line 306 are shown. In this example, each of the first, second, third, and fourth quantum dots 301-304 are connected to the same bit line 305 and word line 306. In an alternative example, each quantum dot can be connected to a separate bit line. The quantum dots can still be connected to the same word line.

[0092] Figure 3 The circuit shown includes first, second, third and fourth integrated circuit elements 307, 308, 309, 310. In this example, each integrated circuit element 307-310 includes a floating gate metal oxide semiconductor (FGMOS) field effect transistor. Each integrated circuit element 307-310 includes a source, a drain, a control gate and a floating gate. In this example, the drain terminal of each integrated circuit element 307-310 is electrically connected to the respective quantum dot 301-304. Specifically, the drain terminal of each integrated circuit element 307-310 is electrically connected to the gate of the corresponding quantum dot 301-304. Each of the first to fourth integrated circuit elements 307-310 is electrically connected to the silicon layer (not shown) of the quantum device so that the first output voltage V QD1 , the second output voltage V QD2 , the third output voltage V QD3 and the fourth output voltage V QD4 Applied to the gates of the first, second, third and fourth induced quantum dots 301-304, respectively.

[0093] The source terminal of each integrated circuit element 307-310 is electrically connected to a voltage source. In this example, each integrated circuit element 307-310 is connected to the same voltage source, so that the input voltage Vset In an alternative example, there may be one or more additional voltage sources, and the circuit may be configured such that each voltage source is electrically connected to one or more integrated circuit elements. The resistance value of each integrated circuit element is adjustable, so that the voltage of the corresponding gate of the induced quantum dot can be controlled to respond to the same input voltage V set Modifying the threshold voltage of any one of the first to fourth integrated circuit elements 307-310 can be used to adjust the channel resistance R between the source and the drain. Fn (n=1, 2, 3, 4).

[0094] The output voltage V applied to each quantum dot 301-304 QDn It can be determined as follows, where n = 1, 2, 3, 4:

[0095]

[0096] For example, according to the resistance R1 of the first quantum dot 301 and the channel resistance R F1 Divide the input voltage V set , thereby according to the modifiable and non-volatile channel resistance R of the first integrated circuit element 307 F1 Reduce the output voltage V applied to the gate of the first quantum dot 301 QD1 . Channel resistance R F1 Also depends on the adjustable threshold voltage V th .

[0097] exist Figure 3 In the embodiment, the voltage source is configured to provide an input voltage V to the source terminal of each integrated circuit element 307-310. set . In this way, a single voltage source can be used to address all four quantum dots 301-304. This reduces the number of voltage sources and associated control circuits required to address the qubit array. In addition, using one voltage source to address multiple qubits reduces the number of operations required to perform a quantum computing process and can speed up computing because the qubits can be manipulated globally and simultaneously across the entire quantum device. In a further example, there can be any number of quantum dots in a quantum device, typically arranged in a one-dimensional or two-dimensional array.

[0098] Figure 3The circuit shown also includes four field effect transistors 311, 312, 313 and 314. Each field effect transistor 311-314 includes a source, a drain and a gate. The control gate of each integrated circuit element 307-310 is electrically connected to the drain terminal of the corresponding field effect transistor 311-314. The source terminal of each field effect transistor 311-314 is electrically connected to the word line 306. The gate terminal of each field effect transistor 311-314 is electrically connected to the bit line 305. In this example, each field effect transistor 311-314 is connected to the same word line 306 and bit line 305. In alternative examples, each field effect transistor can be connected to different word lines and bit lines, or can be connected to the same word line and different bit lines, or can be connected to different word lines and the same bit line. The word lines and bit lines form a cross-type array on the qubit array within the quantum device, and can be used to selectively address specific qubits within the qubit array.

[0099] Each field effect transistor 311-314 can be biased by applying a suitable bias potential V FB The bias potential V applied to the word line 306 can be adjusted to adjust the bias potential V applied to the word line 306 to turn the field effect transistor "on" and the channel resistance is low. If the gate voltage is higher than the threshold voltage, the field effect transistor is "off" and the channel resistance is high. When a bias potential is applied to the bit line 305 to turn the field effect transistor "on", current can flow from the source to the drain terminal of each field effect transistor 311-314 due to the low channel resistance. The bias potential V applied to the word line 306 can be adjusted to adjust the bias potential V applied to the word line 306 to turn the field effect transistor "on". FW The current flow generally increases with increasing bias potential applied to the word line 306, and the current may be proportional to the bias potential.

[0100] Thus, field effect transistors 311-314 can be used to adjust the resistance value of each integrated circuit element 307-310. When the field effect transistor is enabled using an electrically connected bit line, the electrically isolated gate of the integrated circuit element electrically connected to the field effect transistor can be charged or discharged. The charging and discharging of the electrically isolated gate can be controlled by modifying the bias potential applied to the word line electrically connected to the field effect transistor. A cross-type array including bit lines 305 and word lines 306 can be used to address a single integrated circuit element 307-310, or a group of two or more integrated circuit elements 307-310.

[0101] As about Figure 2 As described above, the circuit provides a resistor divider to reduce the input voltage V setFor each quantum dot 301-304, the voltage division depends on the channel resistance of the respectively connected integrated circuit element 307-310, which depends on the adjusted resistance value. The resistance value of each integrated circuit element 307-310 can be adjusted using the respectively connected field effect transistor 311-314.

[0102] Each integrated circuit element 307-310 provides an integrated addressable analog memory in the quantum device and is capable of providing a constant DC voltage offset to each quantum dot 301-304, which is tailored to maintain the voltage within an acceptable range for qubit control. Specifically, for the plunger gate of the induced quantum dot, the acceptable range for qubit control is the voltage V corresponding to a quantum dot containing a single electron, i.e., V 1e ≤V <V 2e , where V 1e is the minimum voltage required for a single electron to occupy a quantum dot, V 2e is the minimum voltage required for two electrons to occupy the quantum dot. Each integrated circuit element 307-310 is used to control the voltage of each plunger gate of the induced quantum dot 301-304. Figure 4 and Figure 5 As shown, providing a regulated constant DC voltage offset to each quantum dot 301-304 can be combined with AC coupling of the control signal.

[0103] Selectable input voltage V set , so that the output voltage V QDn Adjust to an acceptable range, that is, V 1e ≤V QDn <V 2e . V of each quantum dot 1e and V 2e The exact values ​​of will vary, but these nominal voltages can be used to determine the appropriate input voltage V set Typically, V 1e ~0.4V, V 2e <2V 1e . V QDn No need to exceed V 2e To occupy the quantum dot using a single quantum dot, the output voltage should be adjusted so that V 1e ≤V QDn <V 2e To empty the quantum dot, V should be adjusted QDn , so that V <V 1e .

[0104] In the example, V set Can be approximately equal to V 2e In this example, if the channel resistance R of the first integrated circuit element 307 isF1 is much smaller than the resistance of the first quantum dot 301, i.e., R F1 <<R1, then the output voltage V applied to the first quantum dot 301 QD1 Approximately equal to V 2e If the channel resistance R F1 Similar to the channel resistance of the first quantum dot 301, that is, R F1 ~R1, the output voltage V QD1 Approximately equal to the input voltage V set Half of V QD1 ~V 1e Therefore, V set Set to approximately V 2e Provides an output voltage V QDn of sufficient range to cover the necessary operating mechanisms for each quantum dot.

[0105] By increasing the channel resistance R Fn , can further reduce the input voltage V set , to generate a smaller output voltage V QDn However, because the resistance R n Usually very large, especially at cryogenic temperatures, so it is difficult to obtain very high channel resistance R Fn , so that R Fn >>R n .

[0106] Figure 4 1 is a circuit diagram showing a portion of a quantum device according to an embodiment of the present invention. The quantum device includes a qubit layer having quantum dots 401, which can be used as qubits. The circuit also includes a trimming layer having an integrated circuit element 404 for voltage trimming as described herein. The circuit also includes a trimming layer for trimming a signal input, which includes a first field effect transistor 405. The circuit also includes a trimming selection layer, which includes a second field effect transistor 406, which is electrically connected to a word line and a bit line 409, 410 in a cross-type configuration. In this example, the integrated circuit element 404 includes a trimming layer similar to Figure 6 Silicon nanowire multi-quantum dot device shown. In alternative examples, the integrated circuit element may include any gate-defined multi-quantum dot device.

[0107] Each of the integrated circuit element 404 and the first and second field effect transistors (FETs) 405, 406 includes respective source, drain and gate terminals. The integrated circuit element 404 also includes an electrically isolating element capacitively coupled to the gate terminal and capacitively coupled to the source-drain channel. The quantum device includes additional quantum dots, which are not shown in this section for simplicity.

[0108] In this example, for each quantum dot (such as Figure 4 The device includes an integrated circuit element and two electrically connected FETs for each gate of the induced quantum dot (shown as a quantum dot 401). This configuration provides control for each individual gate of each individual quantum dot to account for variations in the properties of the quantum dot. The non-volatile resistance value of each integrated circuit element connected to the gate of the quantum dot can be adjusted to control the output voltage applied to the gate of the induced quantum dot. In the example described below, the gate is a plunger gate. In an alternative example, the gate is a barrier gate, and the output voltage applied by the integrated circuit element 404 can be used to adjust the height of the electrostatic barrier that defines the edge of the inducible quantum dot.

[0109] The quantum dot 401 is electrically grounded and is schematically shown as having a resistance R D The resistor 402 and the capacitor C D Capacitor 403. Quantum dot 401 is an electron spin quantum dot formed in the silicon layer of the quantum device. Quantum dot 401 can be induced by applying a voltage to the gate of quantum dot 401; the number of electrons in quantum dot 401 can be controlled by modifying the voltage applied to the gate of the quantum dot plunger.

[0110] The integrated circuit element 404 is electrically connected to the silicon layer in which the quantum dot 401 can be induced. In this example, the drain terminal of the integrated circuit element 404 is electrically connected to the quantum dot 401; the source terminal of the integrated circuit element 404 is electrically connected to a transistor configured to provide an input voltage V DD the gate terminal of the integrated circuit element 404 is electrically connected to the drain terminal of the first FET 405.

[0111] This configuration enables the output voltage of the integrated circuit element 404 to be applied to the gate of the induced quantum dot 401. The output voltage depends on the input voltage applied to the source terminal of the integrated circuit element 404 and the non-volatile resistance value of the integrated circuit element 404. The input voltage applied using a voltage source is usually applied to more than one quantum dot (not shown). This reduces the number of voltage sources required. The resistance value of each integrated circuit element connected to the gate of each quantum dot can be adjusted so that the same input voltage can provide different output voltages to the gates of different quantum dots as needed, depending on the properties of each quantum dot.

[0112] In this example, a first FET 405 (which may be referred to as an adjustment FET 405) is used to adjust the nonvolatile resistance value. The drain terminal of the first FET 405 is electrically connected to the gate terminal of the integrated circuit element 404; the source terminal of the first FET 405 is electrically connected to a gate terminal configured to provide an adjustment signal V P The gate terminal of the first FET 405 is electrically connected to the drain terminal of the second FET 406. By applying a sufficiently large bias potential to the gate terminal using the second FET 406, the first FET 405 can be turned on and off. When the first FET 405 is "on", the first FET 405 is enabled and current can flow between the source terminal and the drain terminal of the first FET 405. When the first FET 405 is "off", the first FET 405 is disabled and the source-drain current can be ignored. Therefore, when the first FET 405 is enabled, the regulation signal V P is passed to the integrated circuit element 404, and when the first FET 405 is disabled, the regulation signal V P is not passed to the integrated circuit element 404 .

[0113] The current through the first FET 405 can be controlled by modifying the bias potential applied to the source terminal using a connected voltage source. The non-volatile resistance value of the integrated circuit element 404 can be adjusted by changing the charge level of its electrically isolated element. By controlling the current flowing through the first FET 405, the electrically isolated element can be charged and discharged. For example, if the enabled first FET 405 is provided with a positive source-drain bias potential, that is, if the adjustment signal V P If V is positive, the charge on the electrically isolated element will increase. Conversely, if the enabled first FET 405 is set with a negative source-drain bias potential, i.e., if the regulation signal V P is negative, the charge on the electrically isolated element will decrease (ie, the electrically isolated element will discharge). Thus, the adjustment FET 405 acts as a switch and is configured to adjust the non-volatile resistance value of the integrated circuit element 404 only when the adjustment FET 405 is enabled.

[0114] In this example, the first FET 405 is selected using the second FET 406. The second FET 406 may be referred to as a selector FET 406. The drain terminal of the second FET 406 is electrically connected to the gate terminal of the first FET 405; the source terminal of the second FET 406 is electrically connected to the word line 409; and the gate terminal of the second FET 406 is electrically connected to the bit line 410. The bit line 410 and the word line 409 form part of a crossbar array. The second FET can be turned on and off by applying a suitable bias potential to the bit line 410. By adjusting the bias potential applied to the source terminal of the second FET 406, the current through the second FET 406 can be modified.

[0115] The second FET 406 can be enabled by applying a bias potential to the electrically connected bit line 410 and word line 409. The crossbar array includes a plurality of bit lines and word lines (not shown) and is configured so that each second FET corresponding to a quantum dot can be selected. When the first and second FETs 405, 406 are enabled, an electrical connection is provided between the crossbar array and the integrated circuit element 404. For a quantum device having a plurality of quantum dots and therefore a plurality of integrated circuit elements, the crossbar array is configured to be selectively electrically connected to any integrated circuit element. In this way, the non-volatile resistance value of each integrated circuit element can be individually adjusted.

[0116] The first and second FETs 405, 406 form a regulation control circuit and are used to set the quantum device in the setting phase. The integrated circuit element 404 forms a fine-tuning layer and is used to fine-tune the input voltage, that is, to reduce the input voltage. The integrated circuit element 404 is enabled and adjustable in the setting phase. Subsequently, during normal operation, the integrated circuit element 404 operates in a subthreshold regime. Quantum operations can be performed during normal operation, and the quantum device also includes a pulse and readout layer, which includes a qubit pulse control circuit 407 and a qubit readout control circuit 408 to control the qubit during device operation.

[0117] The qubit pulse control circuit 407 and the qubit readout control circuit 408 are electrically connected between the integrated circuit element and the induced quantum dot. In this example, the qubit pulse control circuit 407 includes a capacitor C C The qubit pulse control circuit 407 is configured to modify the state of the qubit by applying a bias potential using a voltage source. The output voltage V of the integrated circuit element 404 is QD Configured to provide a constant DC offset voltage to induce the quantum dots, the qubit pulse control circuit 407 is configured to provide an AC control signal to the electrons in the induced quantum dots, thereby modifying the state of the electron spin qubit.

[0118] In this example, the qubit readout control circuit 408 includes: a capacitor C C A first capacitor having a capacitance C to ground G and an inductor having an inductance L. Qubit readout control circuit 408 is configured to read out or infer the state of the qubit. Any suitable qubit readout control circuit may be used, and may be referred to as, for example, a tank circuit, an LC resonator, an LC tank circuit, a resonant circuit, or a conditioning circuit.

[0119] The qubit pulse control circuit and the qubit readout control circuit are electrically connected to multiple quantum dots within the array so that the qubit states of the multiple quantum dots can be manipulated and read out. Optionally, the qubit pulse control circuit and the qubit readout control circuit can be electrically connected to all quantum dots to control each quantum dot simultaneously in the same manner on the quantum device. Alternatively, the quantum dots within the device can be divided into two or more quantum dot subgroups, and each subgroup can be electrically connected to the qubit pulse and qubit readout control circuits. Global control of quantum dots in this way reduces the control circuits required to perform quantum operations.

[0120] exist Figure 4 In the embodiment, the integrated circuit element 404 provides an addressable analog memory, which can be adjusted using the first FET 405 to provide a constant DC voltage offset V to the quantum dot 401. QD . The qubit pulse control circuit 407 and the qubit readout control circuit 408 are electrically connected between the integrated circuit element 404 and the quantum dot 401, and provide AC-coupled control signals to adjust and control the induced quantum dot 401. A quantum device typically includes multiple quantum dots. Addressable analog memory in the form of an integrated circuit element for each quantum dot can be used to individually adjust the DC voltage offset of each quantum dot. AC-coupled control signals are applied to multiple quantum dots with different DC voltage offsets to achieve global control of a scaled qubit array.

[0121] To perform quantum operations using a quantum device, the quantum device is first set up in a setup phase. During the setup phase, a memory state is written by modifying the charge on the floating element of the integrated circuit element 404. The memory state remains stable during device operation; the memory is non-volatile relative to the operating conditions of the integrated circuit element 404.

[0122] In the setting stage, the non-volatile resistance value R of the integrated circuit element 404 F is adjusted to set the nonvolatile resistance value R F，set In this example, the integrated circuit element 404 is used to control the voltage of the plug gate that can induce the quantum dot 401. Setting the non-volatile resistance value R F，set , so that when the input voltage V DDWhen applied to the integrated circuit element 404, the induced quantum dot 401 will be occupied by one electron, that is, V 1e ≤V QD <V 2e Voltage V 1e and V 2e Depending on the properties of the quantum dots 401, the required set nonvolatile resistance value R of the plug gate of each quantum dot in the array F，set will vary accordingly.

[0123] The resistance value can be set using the adjustment FET 405. Because the resistance value is non-volatile, the resistance value can be set and maintained at a fixed value without power input. This eliminates the need to refresh the set point during quantum device operation. To set the resistance value using the adjustment FET 405, first a bias potential V is applied to the word line 409 and the bit line 410 electrically connected to the second FET 406. BT 、V WT To enable the regulating FET 405, the regulating FET 405 is selected and turned “on”. When the regulating FET 405 is enabled, the resistance value of the integrated circuit element 404 can be adjusted by applying the regulating voltage V to the source terminal of the regulating FET 405. P The regulating FET 405 is electrically connected to the integrated circuit element 404 so that the regulating voltage V can be applied to the enabled regulating FET 405. P , to modify the resistance value R of the integrated circuit element 404 F . Set the nonvolatile resistor value R F，set Depends on the regulation voltage V P .

[0124] Once the resistance value of the integrated circuit element 404 is adjusted to the set resistance value R F，set , the control circuit used in the setting phase, i.e., the first and second FETs 405, 406, can be disabled and disconnected. This reduces power consumption. The electrostatic charge stored by the electrically isolated or floating elements of the integrated circuit element 404 is non-volatile, so the set resistance value can be maintained for a long time without the need for refreshing. The integrated circuit element 404 operates in a deep subthreshold state and does not require power input.

[0125] During operation, the input voltage V DD Applied to the integrated circuit element 404. The output voltage V QD Depends on the input voltage V DD and set the resistance value R F，set The output voltage V of the integrated circuit element 404 is QD is applied to the gate of the induced quantum dot 401. In this example, the output voltage V of the integrated circuit element 404 QDis applied to the plunger gate of the induced quantum dot 401 to control the electron occupancy of the quantum dot 401. In another example, the output voltage of the integrated circuit element is applied to the barrier gate of the induced quantum dot to control the height of the tunnel barrier and / or control the tunnel coupling strength between the induced quantum dot and the adjacent confinement region.

[0126] For a quantum device comprising a plurality of quantum dots, the gate of each quantum dot is electrically connected to a respective integrated circuit element, which can be tuned according to the properties of the quantum dot. For example, the device may include first and second gates of first and second induced quantum dots connected to first and second integrated circuit elements, respectively, the first and second integrated circuit elements having first and second resistance values ​​R F1 , R F2 and the first and second threshold voltages V th1 、V th2 In the setting phase, a crossbar array for selecting one or more integrated circuit components is used to select a first integrated circuit component by applying appropriate bias potentials to word lines and bit lines connected to FETs, which are electrically connected to the first integrated circuit component. After the first integrated circuit component is selected, the first non-volatile resistance value R F1 is adjusted to the first set nonvolatile resistance value R as described above F1，set .

[0127] Subsequently, the second integrated circuit element is selected by applying appropriate bias potentials to the word line and the bit line connected to the FET, which is electrically connected to the first integrated circuit element. One of the word line or the bit line may be shared with the two FETs connected to each of the first and second integrated circuit elements. If both the word line and the bit line are shared, then the first and second resistance values ​​R will be performed simultaneously. F1 , R F2 However, due to the nature of the property variation between quantum dots, individual control is usually required. After selecting the second integrated circuit element, the second non-volatile resistance value R F2 is adjusted to the second set nonvolatile resistance value R as described above F2,set .

[0128] Each nth integrated circuit element in the quantum device can be selected and adjusted during the setting phase. An arbitrary channel resistance can be set for each integrated circuit element to form an analog memory. The resistance value and, accordingly, the threshold voltage and output voltage of the integrated circuit element applied to the gate of the relevant quantum dot remain constant during the life of the device and do not require refreshing.

[0129] The resistance value set point for each quantum dot is typically chosen so that the qubit resonance line is targeted. It is desirable to apply the drive frequency globally to the qubits, but the qubit resonance varies according to the electronic g factor, which varies widely across the device. e Nominally equal to 2, but g e -2 changes by about 10 -2 The electron g-factor can be modified using an applied electric field, causing a Stark shift, but this is not sufficient to overcome the g-factor change because the Stark shift range is δg e =10 -4 –10 -3 Cavity amplitude modulation can be used to overcome this problem: a single drive frequency can be split into 2N+1 bands, so that most or even all qubits can be addressed using a single drive frequency, despite their different g-factors. However, this requires tailoring the voltage for each quantum dot in the device so that each quantum dot is occupied by one and only one electron. The resistance value set point for each quantum dot can be chosen to meet this requirement.

[0130] Once the resistance value of each of the plurality of integrated circuit components is adjusted to the set resistance value, the control circuit used in the set stage can be disabled and idle. For non-volatile integrated circuit components, the idle adjustment control circuit can be disconnected to reduce any potential power consumption or thermal load. During operation, the same input voltage V DD can be applied to the first and second integrated circuit elements (and any other integrated circuit elements within the quantum device). The first and second output voltages of the integrated circuit elements depend on the input voltage V DD and the first and second set resistance values ​​R F1，set , R F2，set The first output voltage of the first integrated circuit element is applied to the plunger gate of the first induced quantum dot to control the voltage occupied by a single electron thereof. The second output voltage of the second integrated circuit element is applied to the plunger gate of the second induced quantum dot to control the voltage occupied by a single electron thereof. Similarly, the nth output voltage of the nth integrated circuit element is applied to the plunger gate of the nth induced quantum dot to control the voltage occupied by a single electron thereof.

[0131] Typically, quantum devices can be operated at cryogenic temperatures. The properties of quantum devices, such as threshold voltage and channel resistance, typically vary with temperature. Therefore, a setup phase is typically performed at the desired operating temperature prior to device operation. The device can be reset by following the setup phase process as described above. The device can be reset when it is necessary to re-adjust or reconfigure the device.

[0132] Figure 51 is a circuit diagram showing a portion of a quantum device according to an embodiment of the present invention. The circuit includes: an adjustment layer 514, which includes an adjustment element and a crossbar array for realizing the selection of the adjustment element; a fine-tuning layer 515, which includes an integrated circuit element configured to output a constant DC offset voltage; a pulse and readout layer 516, which includes an AC-coupled input configured to modify the DC offset voltage to control the qubit; and a qubit layer 517, which includes an electron spin qubit formed by a single quantum dot, which is induced by applying a voltage to the gate of the inducible quantum dot.

[0133] The circuit includes: first and second quantum dots 501, 502 in the qubit layer 517; first and second integrated circuit elements 503, 504 in the fine-tuning layer 515; first and third field effect transistors (FETs) 505, 506 in the adjustment layer 514; and second and fourth FETs 507, 508 in the adjustment layer 514. The first and second quantum dots 501, 502 are electrically connected to a ground potential. The circuit also includes a qubit pulse input 509 forming a qubit pulse control circuit and a tank circuit input 510 forming a qubit readout control circuit. The qubit pulse and readout control circuits 509, 510 are arranged in the pulse and readout layer 516.

[0134] exist Figure 5 In the embodiment, the circuit elements associated with the first quantum dot 501 are electrically connected according to the first configuration, and the circuit elements associated with the second quantum dot 502 are electrically connected according to the second configuration. Typically, the quantum dots in the quantum device will each be connected to the associated circuit elements according to the first configuration or the second configuration. Optionally, some quantum dots in the device are connected according to the first configuration, while other quantum dots in the device are connected according to the second configuration.

[0135] In a first configuration, the first quantum dot 501, the first integrated circuit element 503, the first FET 505 and the second FET 507 are arranged in accordance with Figure 4 The resistance value of the first integrated circuit element 503 can be relative to the input voltage V connected to the drain terminal of the first integrated circuit element 503. DD To adjust. Input voltage V DD is the global voltage reference. The nonvolatile resistance value of the first integrated circuit element 503 is the channel resistance of the first integrated circuit element 503. When compared with the resistance R of the first quantum dot 501, D When the channel resistance is connected in series with the load resistance, the channel resistance forms a common voltage divider configuration. Therefore, the voltage seen at the load (i.e., the first quantum dot 501) is relative to the power supply (i.e., the input voltage V DD )reduce.

[0136] In the second configuration, the second quantum dot 502 is electrically connected to the electrically isolated element of the second integrated circuit element 504. The drain of the second integrated circuit element 504 is grounded. The electrical connections between the second integrated circuit element 504, the third FET 506 and the fourth FET 508 are configured the same as the electrical connections between the first integrated circuit element 503, the first FET 505 and the second FET 507. The electrically isolated element is capacitively coupled to the source-drain channel and the gate terminal of the second integrated circuit element 504, so there is a DC voltage offset that can be applied to the gate of the second quantum dot 502. The electrically isolated element of the second integrated circuit element is directly connected to the gate of the second quantum dot 502.

[0137] Figure 5 The circuit shown includes a crossbar array having a first bit line 511, a second bit line 512, and a word line 513. In this example, the source terminals of both the second FET 506 and the fourth FET 508 are electrically connected to the word line 513. The gate terminals of the second and fourth FETs 506, 508 are electrically connected to separate bit lines: the first bit line 511 is electrically connected to the second FET 506, and the second bit line 512 is electrically connected to the fourth FET 508. In an alternative example of connecting the first quantum dot and the second quantum dot according to the same configuration, the arrangement of the second FET 506 and the fourth FET 508 relative to the word lines and bit lines 511-513 can also be as shown. Figure 5 as shown in .

[0138] The crossbar array is configured to selectively electrically connect to the first and / or second integrated circuit elements 503, 504. The selective electrical connection is achieved by modifying the bias potential applied to each of the first and second bit lines 511, 512 and the word line 513. Each of the first and second bit lines 511, 512 and the word line 513 is electrically connected to a voltage source configured to provide a controllable bias potential. When the bias potential V is greater than the threshold voltage of the second FET 506, the bias potential V BT(a) When applied to the first bit line 511, the second FET 506 is enabled, i.e., the source-drain channel resistance is low, and the second FET 506 is in the "on" state. When the bias potential V is greater than the threshold voltage of the fourth FET 508, BT(b) When the bias potential V applied to the first or second bit line 511, 512 is BT(a) 、V BT(b) Below the threshold voltage of the second or fourth FET 506, 508, respectively, the FET is disabled, ie, the source-drain channel resistance is high, and the second or fourth FET 506, 508 is in the "off" state.

[0139] When the second and / or fourth FETs 506, 508 are enabled, the bias potential V applied to the word line 513 may be adjusted. WT , to control the source-drain current through the second and / or fourth FETs 506, 508. In the example, the bias potential V applied to the first bit line 511 is BT(a) is greater than the threshold voltage of the second FET 506, and the bias potential V applied to the second bit line 512 BT(b) is lower than the threshold voltage of the fourth FET 508. In this example, when the bias potential V WT When applied to the word line 513, the signal passes through the second FET 506 to enable the first FET 505, but does not pass through the fourth FET 508 to the third FET 507. Therefore, the bias potential V applied to the source terminals of the first and third FETs 505, 507 is P It can be used to modify the resistance value of the first integrated circuit component 503 , but the signal will not be transmitted to the second integrated circuit component 504 .

[0140] Figure 6 A cross-sectional side view of an integrated circuit element 600 is schematically shown. Figure 6 The integrated circuit element 600 shown is a silicon nanowire multi-quantum dot device fabricated by patterning silicon nanowires onto a thin silicon-on-insulator substrate. The integrated circuit element 600 has been found to exhibit hysteresis behavior in the threshold voltage and corresponding channel resistance.

[0141] The integrated circuit component 600 includes a silicon layer 601. A first dielectric layer 602 is placed on the silicon layer 601. In this example, the first dielectric layer 602 includes thermally grown silicon dioxide SiO2. The integrated circuit component 600 includes five polycrystalline silicon (polysilicon) gates 603-607 deposited in two stages. In the first stage, the first polysilicon gate 603 and the second polysilicon gate 604 are deposited. In this example, the first and second polysilicon gates 603, 604 are approximately 50 nanometers thick and are deposited simultaneously.

[0142] After depositing the first and second polysilicon gates 603, 604, a second dielectric layer 608 is deposited. In this example, the second dielectric layer 608 is approximately 35 nanometers thick SiO2 and is grown using low-pressure chemical vapor deposition (LPCVD). The third, fourth and fifth polysilicon gates 605, 606, 607 are deposited on top of the second dielectric layer 608. In this example, the third, fourth and fifth polysilicon gates 605, 606, 607 are approximately 80 nanometers thick and are deposited simultaneously.

[0143] Each of the first, second and fourth polysilicon gates 603, 604, 606 is approximately 100 nanometers wide. The fourth polysilicon gate 606 is located between the first and second polysilicon gates 603, 604 and may overlap each of these gates by approximately 10 nanometers. The third polysilicon gate 605 may overlap the first polysilicon gate 603 by approximately 10 nanometers. The fifth polysilicon gate 607 may overlap the second polysilicon gate by approximately 10 nanometers. The second dielectric layer 608 acts as an electrical insulation barrier between the first and second polysilicon gates 603, 604 and the third, fourth and fifth polysilicon gates 605, 606, 607.

[0144] The third and fifth polysilicon gates 605 , 607 provide source and drain terminals and extend to the charge storage reservoir. The first, second and fourth polysilicon gates 603 , 604 , 606 define quantum dots at the interface between the silicon layer 601 and the first dielectric layer 602 .

[0145] In alternative examples, the integrated circuit element may include a different number of polysilicon gates: for example, seven or three. Typically, the polysilicon gates are deposited in two layers separated by an electrically insulating layer. Other examples of devices that may be suitable for use as integrated circuit elements are disclosed in Duan et al., "Dispersive readout of reconfigurable ambipolar quantum dots in asilicon-on-insulator nanowire", arXiv:2009.13944v1[cond-mat.mes-hall](2020).

[0146] In other alternative examples, the integrated circuit element is a conventional floating gate metal oxide semiconductor field effect transistor.

[0147] It will be appreciated that a quantum device comprising an integrated circuit element for controlling a voltage applied to a gate of an inducible quantum dot, and a method of using the device is disclosed. The integrated circuit element provides an addressable analog memory: the resistance value of the integrated circuit element can be adjusted to provide a controllable voltage to the gate of the quantum dot, which voltage can be maintained during device operation at cryogenic temperatures and does not need to be refreshed. During device operation, an AC coupled control signal is used to modify and read out the state of the qubit in the device.

Claims

1. A quantum device comprising: a silicon layer in which a plurality of quantum dots can be induced; A first gate of a first inducible quantum dot, used to control a potential defining the first inducible quantum dot, wherein the first gate of the first inducible quantum dot is a plug gate or a barrier gate; A second gate of a second inducible quantum dot, used to control the potential defining the second inducible quantum dot, wherein the second gate of the second inducible quantum dot is a plug gate or a barrier gate; A first integrated circuit element, used to control the voltage of the first gate, the first integrated circuit element having a first non-volatile resistance value R F , the first nonvolatile resistance value R F is adjustable; and a second integrated circuit component, configured to control a voltage of the second gate, the second integrated circuit component having a second non-volatile resistance value, wherein the second non-volatile resistance value is adjustable; wherein the first integrated circuit element has an input voltage and a first output voltage, wherein the first output voltage depends on the input voltage and the first non-volatile resistance value; wherein the second integrated circuit element has an input voltage and a second output voltage, wherein the second output voltage depends on the input voltage and the second non-volatile resistance value; The first integrated circuit element and the second integrated circuit element are electrically connected to the first gate and the second gate, respectively, so that the first output voltage and the second output voltage are applied to the first gate of the first inducible quantum dot and the second gate of the second inducible quantum dot, respectively.

2. The quantum device according to claim 1, wherein: The first integrated circuit component and / or the second integrated circuit component comprises a floating gate metal oxide semiconductor field effect transistor.

3. The quantum device according to claim 1, wherein: The first integrated circuit element and / or the second integrated circuit element comprises a gate-defined multi-quantum dot device.

4. A quantum device according to any one of the preceding claims, wherein: The first induced quantum dot has a first resistance value R D ;as well as The first output voltage V out With the input voltage V in proportional to, where the proportionality constant is equal to R D / (R F +R D ).

5. A quantum device according to any one of the preceding claims, further comprising a regulating field effect transistor FET, wherein The regulating FET is electrically connected to the first integrated circuit element or the second integrated circuit element, and the regulating FET is configured to enable or disable a regulating voltage of the first integrated circuit element or the second integrated circuit element, respectively.

6. A quantum device according to any one of the preceding claims, wherein: The first induced quantum dot and / or the second induced quantum dot are used as a qubit.

7. The quantum device according to claim 6, wherein: It also includes a qubit pulse control circuit configured to modify the state of the first qubit and / or the second qubit, wherein the qubit pulse control circuit is electrically connected between the first integrated circuit element and / or the second integrated circuit element and the first induced quantum dot and / or the second induced quantum dot, respectively.

8. The quantum device according to claim 6 or 7, wherein: It also includes a qubit readout control circuit, which is configured to read out the state of the first qubit and / or the second qubit, wherein the qubit readout control circuit is electrically connected between the first integrated circuit element and / or the second integrated circuit element and the first induced quantum dot and / or the second induced quantum dot, respectively.

9. The quantum device according to claim 1, wherein: Also included is a crossbar array configured to selectively electrically connect to the first integrated circuit element and / or the second integrated circuit element.

10. A method of using a quantum device, the quantum device comprising: A silicon layer, in which a plurality of quantum dots can be induced; a first gate of a first inducible quantum dot, used to control a potential defining the first induced quantum dot, wherein the first gate of the first inducible quantum dot is a plug gate or a barrier gate; a second gate of a second inducible quantum dot, used to control a potential defining the second induced quantum dot, wherein the second gate of the second inducible quantum dot is a plug gate or a barrier gate; a first integrated circuit element, used to control a voltage of the first gate, wherein the first integrated circuit element has a first non-volatile resistance value R F , the first nonvolatile resistance value R F is adjustable; a second integrated circuit element for controlling the voltage of the second gate, the second integrated circuit element having a second non-volatile resistance value, the second non-volatile resistance value being adjustable; and a crossbar array for selecting one or more integrated circuit elements, wherein the method comprises: Inducing a first quantum dot and a second quantum dot; selecting the first integrated circuit component; adjusting a first non-volatile resistance value of the first integrated circuit element to a first set non-volatile resistance value; selecting the second integrated circuit component; adjusting a second non-volatile resistance value of the second integrated circuit element to a second set non-volatile resistance value; applying an input voltage to the first integrated circuit element and the second integrated circuit element, wherein a first output voltage of the first integrated circuit element and a second output voltage of the second integrated circuit element depend on the input voltage and the first set non-volatile resistance value and the second set non-volatile resistance value, respectively; applying a first output voltage of the first integrated circuit element to a first gate of the first induced quantum dot; and A second output voltage of the second integrated circuit element is applied to a second gate of the second induced quantum dot.

11. The method according to claim 10, wherein: The quantum device further includes an adjustment field effect transistor FET, the adjustment FET including a source terminal, a drain terminal and a gate terminal, wherein adjusting the first non-volatile resistance value or the second non-volatile resistance value of the first integrated circuit element or the second integrated circuit element to the first set non-volatile resistance value or the second set non-volatile resistance value respectively includes: enabling the regulating FET by applying a voltage to a gate terminal of the regulating FET to allow current to pass between a source terminal and a drain terminal of the regulating FET; and applying a regulation voltage to the regulation FET; wherein the regulating FET is electrically connected to the first integrated circuit element or the second integrated circuit element such that applying the regulating voltage to the enabled regulating FET modifies the nonvolatile resistance value of the first integrated circuit element or the second integrated circuit element, respectively; and The first set non-volatile resistance value and the second set non-volatile resistance value depend on the adjustment voltage.

Images