Band-gap reference circuit, ferroelectric memory and electronic device

Abstract

The invention discloses a band-gap reference circuit, a ferroelectric memory and electronic equipment, which can be applied to the technical field of electronic circuits. The starting circuit, the error amplifying circuit, the biasing circuit, the mirror image circuit, the stability coefficient control circuit and the voltage division circuit are arranged in the band-gap reference circuit, so that the temperature coefficient of the circuit in the working process can be adjusted through the band-gap reference circuit and the temperature coefficient control circuit; the error amplification circuit carries out clamping processing on the voltage of the bias circuit and then the bias circuit outputs bias current, and the mirror image circuit carries out mirror image processing on the bias current and then carries out voltage division processing through the voltage division circuit to obtain reference current meeting the requirement of the ferroelectric memory at the current working temperature. Therefore, the storage effect of the ferroelectric storage chip can be effectively maintained at high temperature.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a bandgap reference circuit, a ferroelectric memory and an electronic device. Background Art

[0002] In the related art, in analog integrated circuits, the voltage reference size mainly depends on the temperature. This dependence is precisely defined to ensure the reliability and consistency of the circuit under various temperature conditions. At the same time, this temperature-sensitive characteristic also provides a reliable reference point for analog integrated circuits, thereby ensuring the performance and stability of the circuit under different temperature environments. The core of the design of the bandgap reference circuit is to create a stable reference source that is minimally affected by temperature changes. This circuit cleverly utilizes the characteristics of semiconductor devices: the voltage of some devices increases with increasing temperature, showing a positive temperature coefficient; while the voltage of other devices decreases with increasing temperature, showing a negative temperature coefficient. Most of the current bandgap reference circuits have unadjustable temperature coefficients, and the output reference is almost unchanged within the temperature range of -40℃ to 125℃. However, since the ferroelectric characteristics of current ferroelectric memory chips will gradually lose their storage effect under high temperature conditions, the existing bandgap reference circuit cannot effectively maintain the storage effect of ferroelectric memory chips under high temperature conditions when applied to ferroelectric memory chips.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a bandgap reference circuit, a ferroelectric memory and an electronic device, which can maintain the storage effect of a ferroelectric memory chip under high temperature conditions.

[0005] To achieve the above object, an embodiment of the present application provides a bandgap reference circuit in one aspect, wherein the bandgap reference circuit comprises:

[0006] A start-up circuit, the start-up circuit is externally connected to an input voltage and generates an output current according to the input voltage;

[0007] Error amplifier circuit;

[0008] A bias circuit, wherein the error amplifier circuit clamps the voltage of the bias circuit; the bias circuit is connected to the error amplifier circuit and is used to output a bias current;

[0009] A mirror circuit, the mirror circuit is connected to the bias circuit and is used to output a reference voltage after mirroring the bias current;

[0010] A temperature coefficient control circuit, the temperature coefficient control circuit is respectively connected to the error amplifier circuit, the bias circuit and the mirror circuit, and is used to adjust the temperature coefficient of the mirror circuit during the mirror processing;

[0011] A voltage divider circuit, wherein the output end of the voltage divider circuit is connected to the ferroelectric memory, and is used for providing a reference current to the ferroelectric memory after performing voltage division processing on the reference voltage.

[0012] In some embodiments, the startup circuit includes a first PMOS transistor, a twelfth PMOS transistor and a first NMOS transistor;

[0013] The gate of the first NMOS tube is externally connected to an input voltage;

[0014] The drain of the first NMOS tube and the drain of the first PMOS tube are both connected to the gate of the twelfth PMOS tube;

[0015] The source stage of the first PMOS tube is connected to the source stage of the twelfth PMOS tube;

[0016] The gate of the first PMOS tube is connected to a first connection point, and the first connection point is a connection point between the bias circuit and the mirror circuit.

[0017] In some embodiments, the mirror circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube;

[0018] The source stage of the second PMOS tube, the source stage of the fourth PMOS tube, the source stage of the ninth PMOS tube and the source stage of the tenth PMOS tube are all connected to the source stage of the first PMOS tube;

[0019] The gate of the second PMOS tube, the drain of the second PMOS tube, the gate of the fourth PMOS tube, the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are all connected to the source of the third PMOS tube;

[0020] The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube;

[0021] The drain of the ninth PMOS tube is connected to the source of the eighth PMOS tube;

[0022] The drain of the tenth PMOS tube is connected to the source of the eleventh PMOS tube;

[0023] The drain of the third PMOS tube, the gate of the third PMOS tube, the gate of the fifth PMOS tube, the gate of the eighth PMOS tube, and the gate of the eleventh PMOS tube are all connected to the first connection point.

[0024] In some embodiments, the error amplification circuit includes a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube;

[0025] The gate of the sixth PMOS tube is connected to the drain of the fifth PMOS tube;

[0026] The gate of the seventh PMOS tube is connected to the drain of the eighth PMOS tube;

[0027] The source stage of the sixth PMOS tube is connected to the source stage of the seventh PMOS tube;

[0028] The drain of the sixth PMOS tube is respectively connected to the drain of the third NMOS tube, the gate of the third NMOS tube, the gate of the second NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube;

[0029] The drain of the seventh PMOS tube is connected to the drain of the fourth NMOS tube;

[0030] The source of the third NMOS tube is connected to the drain of the second NMOS tube;

[0031] The source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube;

[0032] The source of the second NMOS tube is connected to the source of the fifth NMOS tube and then grounded.

[0033] In some embodiments, the bias circuit includes a sixth NMOS transistor;

[0034] The drain of the sixth NMOS tube is connected to the first connection point;

[0035] The gate of the sixth NMOS tube is connected to the drain of the seventh PMOS tube;

[0036] The source of the sixth NMOS tube is grounded.

[0037] In some embodiments, the temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit;

[0038] The negative temperature coefficient control circuit includes a first transistor;

[0039] The emitter of the first transistor is connected to the voltage divider circuit;

[0040] The collector of the first transistor and the base of the first transistor are both grounded;

[0041] The positive temperature coefficient control circuit includes a second resistor, a second transistor and a third transistor;

[0042] The first end of the second resistor is connected to the drain of the eighth PMOS tube and the gate of the seventh PMOS tube respectively;

[0043] The second end of the second resistor is connected to the emitter of the second transistor;

[0044] The base of the second transistor and the collector of the second transistor are both grounded;

[0045] The emitter of the third triode is connected to the gate of the sixth NMOS tube;

[0046] The base of the third transistor and the collector of the third transistor are both grounded.

[0047] In some embodiments, the voltage divider circuit includes a third resistor and a fourth resistor;

[0048] The first end of the third resistor is connected to the drain of the eleventh PMOS tube;

[0049] The connection point between the second end of the third resistor and the first end of the fourth resistor outputs the reference current;

[0050] The second end of the fourth resistor is connected to the collector of the first transistor.

[0051] In some embodiments, the bandgap reference circuit further includes a first resistor, a first end of the first resistor is connected to the drain of the twelfth PMOS transistor.

[0052] To achieve the above objective, another aspect of an embodiment of the present application provides a ferroelectric memory, comprising the above bandgap reference circuit.

[0053] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, comprising the above ferroelectric memory.

[0054] The embodiments of the present application include at least the following beneficial effects: the present application provides a bandgap reference circuit, a ferroelectric memory and an electronic device. The present application can adjust the temperature coefficient of the circuit during operation through the bandgap reference circuit through the temperature coefficient control circuit by setting a startup circuit, an error amplifier circuit, a bias circuit, a mirror circuit, a stability coefficient control circuit and a voltage divider circuit in the bandgap reference circuit. The error amplifier circuit clamps the voltage of the bias circuit and then the bias circuit outputs a bias current. The mirror circuit mirrors the bias current and then divides the current through the voltage divider circuit to obtain a reference current that meets the ferroelectric memory at the current operating temperature, thereby effectively maintaining the storage effect of the ferroelectric memory chip under high temperature conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a schematic diagram of a bandgap reference circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application, they are only examples of devices and methods consistent with some aspects of the embodiments of the present application.

[0057] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0058] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0060] The embodiment of the present application provides a bandgap reference circuit, which includes a startup circuit, an error amplifier circuit, a bias circuit, a mirror circuit, a temperature coefficient control circuit and a voltage divider circuit. Among them, the startup circuit is externally connected to the input voltage, and when the input voltage exceeds the threshold voltage, the bandgap reference circuit is controlled to start, and an output current is generated according to the input voltage. The temperature coefficient control circuit is connected to the error amplifier circuit, the bias circuit and the mirror circuit respectively. When the bandgap reference circuit is started, it is used to adjust the temperature coefficient of the mirror circuit during the mirror processing; the error amplifier circuit clamps the voltage of the bias circuit using the "virtual short" characteristic; the bias circuit is connected to the error amplifier circuit for output bias current; the mirror circuit is connected to the bias circuit, and the bias current is mirrored and copied based on the Cascode mirror principle to output a constant reference voltage; the output end of the voltage divider circuit is connected to the ferroelectric memory, which is used to provide a reference current to the ferroelectric memory after the reference voltage is divided. Specifically, the bandgap reference circuit provided in this embodiment can provide a reference current with a temperature coefficient of 0 at room temperature and a reference current with a positive temperature coefficient at high temperature.

[0061] In the embodiments of the present application, Figure 1 As shown, the startup circuit includes a first PMOS tube PM1, a twelfth PMOS tube PM12 and a first NMOS tube NM1. The gate of the first NMOS tube NM1 is externally connected to the input voltage; the drain of the first NMOS tube NM1 and the drain of the first PMOS tube PM1 are both connected to the gate of the twelfth PMOS tube PM12, the source of the first NMOS tube NM1 is grounded; the source of the first PMOS tube PM1 is connected to the source of the twelfth PMOS tube PM12; the gate of the first PMOS tube PM1 is connected to the first connection point, and the first connection point is the connection point between the bias circuit and the mirror circuit. Specifically, this embodiment can break the degenerate state when the input voltage VDD rises by arranging the first PMOS tube, the twelfth PMOS tube and the first NMOS tube in the startup circuit, thereby reducing the energy loss during the operation of the circuit.

[0062] In the embodiments of the present application, Figure 1As shown, the mirror circuit includes a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10 and an eleventh PMOS tube PM11. The source of the second PMOS tube PM2, the source of the fourth PMOS tube PM4, the source of the ninth PMOS tube PM9 and the source of the tenth PMOS tube PM10 are all connected to the source of the first PMOS tube PM1; the gate of the second PMOS tube PM2, the drain of the second PMOS tube PM2, the gate of the fourth PMOS tube PM4, the gate of the ninth PMOS tube PM9 and the gate of the tenth PMOS tube PM10 are all connected to the source of the third PMOS tube PM3; the drain of the fourth PMOS tube PM4 is connected to the source of the fifth PMOS tube PM5; the drain of the ninth PMOS tube PM9 is connected to the source of the eighth PMOS tube PM8; the drain of the tenth PMOS tube PM10 is connected to the source of the eleventh PMOS tube PM11; the drain of the third PMOS tube PM3, the gate of the third PMOS tube PM3, the gate of the fifth PMOS tube PM5, the gate of the eighth PMOS tube PM8 and the gate of the eleventh PMOS tube PM11 are all connected to the first connection point. Specifically, the embodiment provides a mirror circuit, so that a constant current or a constant voltage under different temperature coefficients can be provided through the mirror circuit, thereby improving the stability of the circuit operation.

[0063] In the embodiments of the present application, Figure 1As shown, the error amplifier circuit includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5. The gate of the sixth PMOS tube PM6 is connected to the drain of the fifth PMOS tube PM5; the gate of the seventh PMOS tube PM7 is connected to the drain of the eighth PMOS tube PM8; the source of the sixth PMOS tube PM6 is connected to the source of the seventh PMOS tube PM7; the drain of the sixth PMOS tube PM6 is respectively connected to the drain of the third NMOS tube, the gate of the third NMOS tube NM3, the gate of the second NMOS tube NM2, the gate of the fourth NMOS tube NM4 and the gate of the fifth NMOS tube NM5; the drain of the seventh PMOS tube NM7 is connected to the drain of the fourth NMOS tube NM4; the source of the third NMOS tube NM3 is connected to the drain of the second NMOS tube NM2; the source of the fourth NMOS tube NM4 is connected to the drain of the fifth NMOS tube NM5; the source of the second NMOS tube NM2 is connected to the source of the fifth NMOS tube NM5 and then grounded. Specifically, in this embodiment, the gates of the sixth PMOS tube and the seventh PMOS tube are used as inputs to display a temperature coefficient of 0 at normal temperature; and then the positive temperature coefficient under high temperature is adjusted through the inverse coefficients of the second NMOS tube, the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube.

[0064] In the embodiments of the present application, Figure 1 As shown, the bias circuit includes a sixth NMOS transistor NM6; the drain of the sixth NMOS transistor NM6 is connected to the first connection point; the gate of the sixth NMOS transistor NM6 is connected to the drain of the seventh PMOS transistor PM7; and the source of the sixth NMOS transistor NM6 is grounded. In this embodiment, the bias current output by the bias circuit is controlled by the output of the error amplifier circuit.

[0065] The temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit. Figure 1As shown, the negative temperature coefficient control circuit includes a first triode Q1; the emitter of the first triode Q1 is connected to the voltage divider circuit; the collector of the first triode Q1 and the base of the first triode Q1 are both grounded; the positive temperature coefficient control circuit includes a second resistor R2, a second triode Q2 and a third triode Q3; the first end of the second resistor R2 is respectively connected to the drain of the eighth PMOS tube PM8 and the gate of the seventh PMOS tube PM7; the second end of the second resistor R2 is connected to the emitter of the second triode Q2; the base of the second triode Q2 and the collector of the second triode Q2 are both grounded; the emitter of the third triode Q3 is connected to the gate of the sixth NMOS tube NM6; the base of the third triode Q3 and the collector of the third triode Q3 are both grounded. Specifically, this embodiment sets the first transistor as a negative temperature coefficient transistor, sets the second transistor and the third transistor as positive temperature coefficient transistors, and controls the positive temperature coefficient ratio through the second resistor, so that the bandgap reference circuit can output a reference current that meets the ferroelectric memory at the current operating temperature.

[0066] In the embodiments of the present application, Figure 1 As shown, the voltage divider circuit includes a third resistor R3 and a fourth resistor R4; the first end of the third resistor R3 is connected to the drain of the eleventh PMOS transistor PM11; the connection point between the second end of the third resistor R3 and the first end of the fourth resistor R4 outputs a reference current; the second end of the fourth resistor R4 is connected to the collector of the first transistor Q1. After the voltage divider circuit is set in this embodiment, the resistor ratio in the voltage divider circuit can be adjusted to output a voltage corresponding to a special temperature coefficient.

[0067] And, if Figure 1 As shown, the bandgap reference circuit of the embodiment of the present application also includes a first resistor R1, and the first end of the first resistor R1 is connected to the drain of the twelfth PMOS tube PM12, so as to prevent the capacitor C1 of the circuit from being damaged at the startup moment, thereby improving the working life of the circuit.

[0068] In summary, the bandgap reference circuit provided in the embodiment of the present application has the following beneficial effects:

[0069] First, the output voltage has different temperature coefficients in different temperature ranges, so there is no need for two reference circuits with different temperature coefficients, which effectively reduces the circuit area and reduces the cost;

[0070] Second, by selecting a specific size load RC, the output anti-interference ability can maintain PSRR above 45 below 1GHz, which has ultra-high anti-interference ability.

[0071] Third, because the conventional bandgap reference circuit (bandgap) op amp output directly controls the PMOS gate terminal voltage to adjust the current, it cannot finely adjust the current size at different temperatures. The op amp output of the present application controls the NMOS gate and then adjusts the current through the current mirror control. Under high temperature conditions, the working state of the fifth NMOS tube changes, and the current suddenly changes to a positive temperature coefficient to achieve a 0 temperature coefficient at normal temperature and a positive temperature coefficient at high temperature.

[0072] Fourth, the existing bandgap outputs a zero temperature coefficient current through three-branch bipolar junction transistors (BJT) and then mirrors it to the fourth branch. The present application can achieve the same effect without the fourth branch, effectively reducing the circuit area.

[0073] In addition, the embodiment of the present application also provides a ferroelectric memory and an electronic device. The ferroelectric memory includes the above-mentioned bandgap reference circuit, and the electronic device includes the ferroelectric memory. It can be understood that the ferroelectric memory may include but is not limited to a ferroelectric chip and a bandgap reference circuit. The bandgap reference circuit is used to provide a reference current or a reference voltage of the ferroelectric chip.

[0074] It can be understood that the contents of the above-mentioned bandgap reference circuit embodiments are applicable to the present ferroelectric memory and electronic device embodiments, and the beneficial effects achieved by the present ferroelectric memory and electronic device embodiments are the same as the beneficial effects achieved by the above-mentioned bandgap reference circuit embodiments.

[0075] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0076] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0077] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0079] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0080] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0081] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0082] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0083] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0085] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A bandgap reference circuit, characterized in that: The bandgap reference circuit comprises: A start-up circuit, the start-up circuit is externally connected to an input voltage and generates an output current according to the input voltage; Error amplifier circuit; A bias circuit, wherein the error amplifier circuit clamps the voltage of the bias circuit; the bias circuit is connected to the error amplifier circuit and is used to output a bias current; A mirror circuit, the mirror circuit is connected to the bias circuit and is used to output a reference voltage after mirroring the bias current; A temperature coefficient control circuit, the temperature coefficient control circuit is respectively connected to the error amplifier circuit, the bias circuit and the mirror circuit, and is used to adjust the temperature coefficient of the mirror circuit during the mirror processing; A voltage divider circuit, wherein the output end of the voltage divider circuit is connected to the ferroelectric memory, is used for providing a reference current to the ferroelectric memory after performing voltage division processing on the reference voltage.

2. The bandgap reference circuit according to claim 1, characterized in that: The startup circuit includes a first PMOS tube, a twelfth PMOS tube and a first NMOS tube; The gate of the first NMOS tube is externally connected to an input voltage; The drain of the first NMOS tube and the drain of the first PMOS tube are both connected to the gate of the twelfth PMOS tube; The source stage of the first PMOS tube is connected to the source stage of the twelfth PMOS tube; The gate of the first PMOS tube is connected to a first connection point, and the first connection point is a connection point between the bias circuit and the mirror circuit.

3. The bandgap reference circuit according to claim 2, characterized in that: The mirror circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube; The source stage of the second PMOS tube, the source stage of the fourth PMOS tube, the source stage of the ninth PMOS tube and the source stage of the tenth PMOS tube are all connected to the source stage of the first PMOS tube; The gate of the second PMOS tube, the drain of the second PMOS tube, the gate of the fourth PMOS tube, the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are all connected to the source of the third PMOS tube; The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; The drain of the ninth PMOS tube is connected to the source of the eighth PMOS tube; The drain of the tenth PMOS tube is connected to the source of the eleventh PMOS tube; The drain of the third PMOS tube, the gate of the third PMOS tube, the gate of the fifth PMOS tube, the gate of the eighth PMOS tube, and the gate of the eleventh PMOS tube are all connected to the first connection point.

4. The bandgap reference circuit according to claim 3, characterized in that: The error amplification circuit includes a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; The gate of the sixth PMOS tube is connected to the drain of the fifth PMOS tube; The gate of the seventh PMOS tube is connected to the drain of the eighth PMOS tube; The source level of the sixth PMOS tube is connected to the source level of the seventh PMOS tube; The drain of the sixth PMOS tube is respectively connected to the drain of the third NMOS tube, the gate of the third NMOS tube, the gate of the second NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube; The drain of the seventh PMOS tube is connected to the drain of the fourth NMOS tube; The source of the third NMOS tube is connected to the drain of the second NMOS tube; The source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; The source of the second NMOS tube is connected to the source of the fifth NMOS tube and then grounded.

5. The bandgap reference circuit according to claim 4, characterized in that: The bias circuit includes a sixth NMOS tube; The drain of the sixth NMOS tube is connected to the first connection point; The gate of the sixth NMOS tube is connected to the drain of the seventh PMOS tube; The source of the sixth NMOS tube is grounded.

6. The bandgap reference circuit according to claim 5, characterized in that: The temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit; The negative temperature coefficient control circuit includes a first transistor; The emitter of the first transistor is connected to the voltage divider circuit; The collector of the first transistor and the base of the first transistor are both grounded; The positive temperature coefficient control circuit includes a second resistor, a second transistor and a third transistor; The first end of the second resistor is connected to the drain of the eighth PMOS tube and the gate of the seventh PMOS tube respectively; The second end of the second resistor is connected to the emitter of the second transistor; The base of the second transistor and the collector of the second transistor are both grounded; The emitter of the third triode is connected to the gate of the sixth NMOS tube; The base of the third transistor and the collector of the third transistor are both grounded.

7. The bandgap reference circuit according to claim 6, characterized in that: The voltage divider circuit includes a third resistor and a fourth resistor; The first end of the third resistor is connected to the drain of the eleventh PMOS tube; The connection point between the second end of the third resistor and the first end of the fourth resistor outputs the reference current; The second end of the fourth resistor is connected to the collector of the first transistor.

8. The bandgap reference circuit according to any one of claims 1 to 7, characterized in that: The bandgap reference circuit further includes a first resistor, a first end of which is connected to the drain of the twelfth PMOS tube.

9. A ferroelectric memory, characterized in that: The invention comprises the bandgap reference circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Includes the ferroelectric memory as claimed in claim 9.

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