Power-on sequence control method and circuit

Abstract

The invention provides a power-on sequence control method and circuit, and relates to the technical field of circuit control, negative voltage is obtained through conduction of a photoelectric coupler U1 and voltage division of resistors R3 and R4, time delay is carried out through charging of a capacitor C1, and then conduction of an NMOS tube M1 is controlled; calculating charging theoretical time, comparing the charging theoretical time with actual charging time to obtain a charging difference value, and judging whether time delay succeeds or not according to comparison between the charging difference value and a preset difference value threshold value to obtain a time delay judgment result; the grid voltage of the NMOS tube M1 is controlled to rise, so that the NMOS tube is switched on, negative voltage is output, the capacitor C1 is discharged, the grid voltage of the NMOS tube M1 is converted into the negative voltage, and output of the negative voltage is stopped; according to the method, the output of the negative voltage is controlled by using the positive voltage, two purposes are achieved, and the method is more efficient.

Description

Technical Field

[0001] The invention proposes a power-on sequence control method and circuit, and relates to the technical field of circuit control, and in particular to the technical field of power-on sequence control. Background Art

[0002] At present, most circuits are powered by multiple circuits, with one power supply input and multiple power supplies input at the same time. Some precision electronic components have extremely high requirements for power supply sequence and time. For the above situation, ordinary power supply circuits cannot guarantee a unified power-on sequence or power-on time, and have uncertainty and randomness. It is easy to cause circuit malfunction and damage components. Traditional circuit delays are difficult to achieve timely response of the circuit due to the fixed threshold, which is easy to cause circuit damage and difficult to adjust flexibly. Summary of the invention

[0003] The present invention provides a power-on sequence control method and circuit to solve the above problems: The present invention provides a power-on sequence control method and circuit, the method comprising: S1, after inputting positive voltage to the startup circuit, obtains negative voltage through the conduction of the photocoupler U1 and the voltage division of the resistors R3 and R4, and uses the charging of the capacitor C1 for delay, thereby controlling the conduction of the NMOS tube M1; S2. Calculate the theoretical charging time and compare it with the actual charging time to obtain the charging difference. According to the comparison between the charging difference and the preset difference threshold, determine whether the delay is successful and obtain the delay determination result. S3, by controlling the gate voltage of the NMOS tube M1 to rise, thereby turning on the NMOS tube, outputting a negative voltage, discharging the capacitor C1, converting the gate voltage of the NMOS tube M1 into a negative voltage, and stopping the output of the negative voltage; S4. Calculate the threshold adjustment coefficient, compare the calculated adjustment coefficient with the preset coefficient threshold, adjust the threshold according to the comparison result, and obtain the adjustment result.

[0004] Furthermore, the S1 includes: When a positive voltage is input to the circuit startup circuit, the photocoupler U1 is controlled to be turned on, and the negative voltage is divided by resistors R3 and R4 respectively, and the voltage of resistor R4 is greater than the negative voltage; When there is no voltage difference between the gate and source of the NMOS tube M1, the NMOS tube M1 is controlled not to be turned on, and there is no negative voltage output; The capacitor C1 is charged through the resistor R2, and the charging time is the negative voltage output delay time; Further, the S2 includes: The calculation formula of the theoretical charging time is: Among them, the resistance The unit is Ω, the unit of capacitance is F, V s is the input voltage at the resistor end, V c is the required rising voltage, is the theoretical charging time; Obtaining a theoretical charging time and an actual charging time, and obtaining a charging difference according to the theoretical charging time and the actual charging time; Comparing the charging difference with a preset difference threshold to obtain a difference comparison result; A charging delay determination is performed according to the difference comparison result to obtain a delay determination result.

[0005] Further, the S3 includes: When the capacitor C1 is successfully charged and delayed, the gate voltage of the NMOS tube M1 is controlled to rise and be greater than the source voltage, thereby controlling the voltage difference to be greater than 1V, controlling the NMOS tube M1 to be turned on, and the negative voltage is output through the NMOS tube M1; When there is no positive voltage input, the photocoupler U1 is controlled to be cut off, and the resistor R2 is short-circuited through the diode D1; The capacitor C1 is discharged through the resistor R3 and the diode D1, and the positive voltage of the gate of the NMOS tube M1 is converted into a negative voltage, so that there is no voltage difference between the gate and the source, and then the negative voltage is controlled to stop the data; Further, the S4 includes: Acquiring circuit control data, and calculating a threshold adjustment coefficient according to the circuit control data; The calculation formula of the threshold adjustment coefficient is: Among them, YTX is the threshold adjustment Coefficient, α is the basic adjustment factor, Δt s is the actual charging time, Δt l is the theoretical charging time, β is the time deviation index, r is the time standard deviation attenuation factor, is the standard deviation of charging time, Δt a is the average charging time, θ is the voltage gain factor, V g is the maximum voltage difference between the gate and source of the NMOS tube, V t is the threshold voltage of the NMOS tube, V s The supply voltage, i.e. the voltage supplied to the starting circuit; Compare the preset adjustment coefficient with the preset coefficient threshold to obtain a threshold comparison result; The threshold is adjusted according to the threshold comparison result to obtain an adjustment result.

[0006] Furthermore, the circuit comprises: A control circuit construction module, used for inputting voltage to a startup circuit through an external power supply, and constructing a power-on sequence circuit through the external power supply and the startup circuit; An isolation module is used to isolate the circuit input and output using a photocoupler; A voltage division module, used for voltage division control of input voltage; The delay control module is used to perform delay control of the circuit through capacitor C1 to obtain a delay control result.

[0007] Furthermore, the control circuit building module includes: Connecting the positive voltage output terminal of the external power supply to the positive voltage input terminal of the start-up circuit; A power-on sequence control circuit is constructed by an external power supply and a startup circuit, wherein the startup circuit includes a photocoupler U1, a capacitor C1, multiple resistors, a diode D1 and an NMOS tube M1; The plurality of resistors include a resistor R1 , a resistor R2 , a resistor R3 , and a resistor R4 .

[0008] Furthermore, the isolation module comprises: The positive voltage input terminal and the negative voltage input terminal of R1 are the positive voltage input terminal and the negative voltage input terminal of the startup circuit; The positive voltage output terminal of R1 is connected to the anode of the photoelectric coupler, and the cathode and collector of the photoelectric coupler are grounded respectively; the emitter of the photoelectric coupler is connected to the positive voltage input terminal of the resistor R4.

[0009] Furthermore, the voltage dividing module comprises: The positive voltage output end of the resistor R4 is connected to the positive voltage input end of the resistor R3, the positive voltage output end of the resistor R3 is connected to the negative voltage input end, the resistor R3 is connected in series with the resistor R4, and the central node where the resistor R4 and the resistor R3 are connected is respectively connected to the positive voltage input end of the resistor R2 and the cathode of the diode D1.

[0010] Furthermore, the delay control module includes: The positive voltage output end of the resistor R2 is connected to the positive electrode of the diode D1 to form a first intersection; The first intersection is connected to the positive voltage input terminal of the capacitor C1 and the gate of the NMOS tube respectively; The negative voltage input terminal of the capacitor C1 is connected to the source of the NMOS tube to form a second intersection; The second intersection is connected to the negative voltage input terminal; The NMOS tube MI is connected to the negative voltage output terminal.

[0011] Beneficial effects of the present invention: The present invention provides a circuit that can control the power-on sequence of positive voltage and negative voltage, and use positive voltage to control negative voltage output. The circuit design can effectively deal with electronic components with high power-on timing requirements and strict sequence requirements and circuit boards with corresponding functions. At the same time, it can avoid damage to components due to incorrect power-on sequence, and can also control negative voltage output by positive voltage. If the positive voltage stops outputting, the negative voltage output will be terminated at the same time, avoiding damage and burning of circuit boards caused by single-channel power supply. The advantage of the design of the present invention is that the interval power-on time can be adjusted by changing the selection of some components, and compared with the existing common designs, it has a more flexible application range. At the same time, compared with the existing technology, the present invention has a simpler and more efficient solution, a lower-cost device selection and a smaller number of components. Using positive voltage to control negative voltage output is also simpler than the existing technology, and there is no need to add additional power control design. While controlling the power-on sequence, power input control can also be achieved, killing two birds with one stone and being more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a power-on sequence control method; Figure 2 This is a schematic diagram of the power-on sequence control circuit. DETAILED DESCRIPTION

[0013] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0014] In one embodiment of the present invention, a power-on sequence control method and circuit are provided, and the method includes: S1, after inputting positive voltage to the startup circuit, obtains negative voltage through the conduction of the photocoupler U1 and the voltage division of the resistors R3 and R4, and uses the charging of the capacitor C1 for delay, thereby controlling the conduction of the NMOS tube M1; S2. Calculate the theoretical charging time and compare it with the actual charging time to obtain the charging difference. According to the comparison between the charging difference and the preset difference threshold, determine whether the delay is successful and obtain the delay determination result. S3, by controlling the gate voltage of the NMOS tube M1 to rise, thereby turning on the NMOS tube, outputting a negative voltage, discharging the capacitor C1, converting the gate voltage of the NMOS tube M1 into a negative voltage, and stopping the output of the negative voltage; S4, calculate the threshold adjustment coefficient, compare the calculated adjustment coefficient with the preset coefficient threshold, adjust the threshold according to the comparison result, and obtain the adjustment result, such as Figure 1 shown.

[0015] The working principle of the above technical solution is: when a positive voltage is input to the startup circuit, the photocoupler U1 is activated and turned on. At this time, a negative voltage signal is generated through the voltage division effect of resistors R3 and R4. This negative voltage signal does not come directly from the power supply, but is converted from the positive voltage through the voltage division circuit and is used for subsequent control logic. The generated negative voltage signal acts on capacitor C1 at the same time to start charging the capacitor. Due to the charging characteristics of the capacitor, its voltage will gradually rise, and this rising process takes time, that is, a delay effect is formed. The length of the delay time depends on the capacity of the capacitor, the charging resistor (here is R2, although it is not directly mentioned in the step, but it is usually used to limit the charging current) and the amplitude of the input voltage. When the voltage of capacitor C1 rises to a high enough level (usually higher than the threshold voltage of NMOS tube M1), a positive voltage difference is formed between the gate and source of NMOS tube M1, causing the NMOS tube to turn on. After NMOS tube M1 is turned on, the negative voltage signal can be output to the subsequent circuit through the NMOS tube. At the same time, capacitor C1 continues to charge until a certain upper limit is reached or external conditions change (such as the disappearance of the input positive voltage), causing charging to stop. When the input positive voltage disappears or the circuit logic needs to stop the negative voltage output, capacitor C1 is discharged through a certain mechanism (such as the optocoupler U1 is cut off, the diode D1 short-circuit resistor R2, etc.), so that the gate voltage of the NMOS tube M1 drops rapidly, and then the NMOS tube is cut off and the negative voltage output stops. During the delay process, by calculating the difference between the theoretical charging time and the actual charging time and comparing it with the preset difference threshold, it can be determined whether the delay is successful. This step helps to ensure the stability and reliability of the circuit. According to the historical delay data and the current working status, the threshold adjustment coefficient is calculated and compared with the preset coefficient threshold. If adjustment is required, the delay threshold is adjusted accordingly according to the comparison result to adapt to different working conditions and requirements.

[0016] The external power supply outputs positive electricity and negative electricity and is connected to the startup circuit. At this time, the positive electricity is connected to the anode of the photocoupler U1 through the resistor R1, and the resistors R3 and R4 are connected in series. One end of the resistor R4 is connected to the emitter of the photocoupler, and one end of the resistor R3 is connected to the negative electricity input. The cathode and collector of the photocoupler U1 are grounded. After the photocoupler is turned on, negative electricity is applied to the resistors R3 and R4, and the two resistors R3 and R4 are connected in series to divide the voltage. After the voltage is divided, the current flows through the resistor R2 and charges the capacitor C1. After the charging delay of the capacitor C1, the gate voltage is greater than the source voltage. At this time, the NMOS tube M1 is turned on and negative electricity is output. Finally, the positive electricity controls the negative electricity output and the negative electricity is slower than the positive electricity output.

[0017] When the external power supply stops outputting positive electricity, the U1 photocoupler is disconnected, and the capacitor C1 is quickly discharged through the D1 diode and the R3 resistor. The gate voltage of the MOS tube M1 is equal to the source voltage, M1 is cut off, and the negative electricity stops outputting.

[0018] By controlling the negative power through positive power, the power-on sequence is changed to ensure that the power is powered on in the normal sequence to avoid damage to electronic products. The circuit design is exquisite and simple, and the components used are low-cost, common and stable, which greatly improves the design stability.

[0019] This embodiment provides a startup circuit that can control the power-on sequence, such as Figure 2 As shown, it includes a photocoupler, several resistors, capacitors, diodes, and NMOS tubes.

[0020] The positive voltage input terminal is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the anode of the photocoupler U1. The cathode of the photocoupler is connected to the collector and the ground, and the emitter is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the resistor R3, and the other end of the resistor R3 is connected to the negative voltage input terminal, that is, the resistors R3 and R4 are connected in series. The central node where the resistors R3 and R4 are connected is respectively connected to one end of the resistor R2 and the cathode of the diode D1. The other end of the resistor R2 and the anode of the diode D1 converge at one point and are respectively connected to one end of the capacitor C1 and the gate of the NMOS tube M1. The other end of the capacitor C1 and the source of the NMOS tube M1 converge at one point and are connected to the negative voltage input terminal. The drain of the NMOS tube M1 is connected to the negative voltage output.

[0021] After the positive voltage and the negative voltage are input together, the photoelectric coupler U1 is turned on, and the negative voltage is divided at the resistors R3 and R4. The voltage at R4 is greater than the negative voltage, and the theoretical calculated value is -9.2V. At this time, due to the existence of capacitor C1, there is no voltage difference between the gate and the source of the NMOS tube M1, M1 is not turned on, and there is no negative power output. The capacitor C1 is then charged through resistor R2, and the charging time is the negative power output delay time. The theoretical calculation formula for charging time is t / RC=-ln(Vs-Vc) / Vs, where the unit of resistance is ohm, the unit of capacitance is F, Vs is the input voltage at the resistor end, and Vc is the required rise voltage. In this embodiment, the theoretical charging time is calculated to be 235ms, and the actual charging time is 244ms. For specific charging time, refer to Figure 2 As shown in the figure, after the capacitor C1 is charged for a delay, the voltage at the gate of the NMOS tube M1 rises to a value greater than the voltage at the source, the voltage difference is greater than 1V, the NMOS tube is turned on, and the negative voltage is normally output through M1.

[0022] When the positive voltage input disappears, the photocoupler U1 is turned off. The resistor R2 is short-circuited by the diode D1, and the capacitor C1 is discharged through the resistor R3 and the diode D1. The gate voltage of the NMOS tube M1 becomes a negative voltage, and there is no voltage difference between the gate and the source. M1 is turned off, and the negative voltage stops outputting.

[0023] This ultimately achieves positive electricity controlling negative electricity output, and negative electricity output is slower than positive electricity.

[0024] The technical effect of the above technical solution is: through means such as photoelectric coupler isolation, resistor voltage division, capacitor delay and NMOS tube control, accurate control of the circuit power-on sequence is achieved, avoiding circuit failure or damage caused by improper power-on sequence. By calculating the charging time difference and the threshold adjustment mechanism, the delay performance of the circuit can be monitored and adjusted in real time to ensure that the circuit can maintain a stable delay effect under different working conditions. The control method has strong flexibility and adaptability, and can adjust the delay threshold and negative voltage output parameters according to actual needs to meet the needs of different application scenarios. When negative voltage output is not required, the negative voltage output path is cut off in time by controlling the NMOS tube cutoff and capacitor discharge, thereby reducing the energy consumption and heat generation of the circuit. The control method and circuit structure are relatively simple, easy to implement and maintain, reducing the complexity and cost of circuit design, and improving design efficiency.

[0025] In one embodiment of the present invention, the S1 includes: When a positive voltage is input to the circuit startup circuit, the photocoupler U1 is controlled to be turned on, and the negative voltage is divided by resistors R3 and R4 respectively. The voltage of resistor R4 is greater than the negative voltage, and the theoretical calculated value is -9.2V; Because of the capacitor CI, when there is no voltage difference between the gate and source of the NMOS tube M1, the NMOS tube M1 is controlled not to be turned on, and there is no negative voltage output; The capacitor C1 is charged through the resistor R2, and the charging time is the negative voltage output delay time.

[0026] The working principle of the above technical solution is: when a positive voltage is input to the circuit startup circuit, this positive voltage signal is transmitted to the input end of the photocoupler U1, causing the output end of the photocoupler (usually the phototransistor side) to be turned on. This conduction state provides a path for the subsequent resistor voltage divider network. After the photocoupler U1 is turned on, its output end is connected to resistors R3 and R4 to form a voltage divider network. After the voltage is divided by R3 and R4, the voltage obtained on R4 is -9.2V. This is just an example, the initial state of the NMOS tube M1: due to the presence of capacitor C1, when the circuit is just powered on, the voltage on C1 is zero (or close to zero). Therefore, there is no voltage difference between the gate and source of the NMOS tube M1 (or the voltage difference is very small, not enough to turn on the NMOS tube). At this time, the NMOS tube M1 is in the cut-off state, and the negative voltage cannot be output through the NMOS tube. When the photocoupler U1 is turned on and the voltage divider network is stable, the capacitor C1 begins to be charged through the resistor R2. Due to the charging characteristics of the capacitor (i.e. the current gradually decreases over time and the voltage gradually increases), this process takes a certain amount of time. This charging time is the delay time of the negative voltage output. As the voltage on the capacitor C1 gradually increases, when the voltage reaches the threshold voltage of the NMOS tube M1, the NMOS tube begins to conduct and the negative voltage is output.

[0027] The technical effect of the above technical solution is: through the charging delay of capacitor C1, the output time of negative voltage can be accurately controlled, avoiding the simultaneous output with positive voltage or other signals, thereby reducing interference and potential problems in the circuit. The use of photoelectric coupler realizes electrical isolation between input and output, and enhances the anti-interference ability of the circuit. At the same time, through the combination of resistor voltage divider network and capacitor charging effect, the conduction state of NMOS tube can be stably controlled, and the reliability and stability of the circuit are improved. By adjusting the resistance value of resistors R2, R3, R4 and the capacity of capacitor C1, the delay time and the output characteristics of negative voltage can be flexibly adjusted to adapt to different application scenarios and requirements. During the cut-off period of NMOS tube M1, the negative voltage output path is cut off, reducing unnecessary power consumption and heat generation. The control method is relatively simple, requires fewer components, and is easy to implement and maintain, reducing the complexity and cost of circuit design.

[0028] In one embodiment of the present invention, S2 includes: The calculation formula of the theoretical charging time is: The unit of resistance is Ω , the unit of capacitance is F, V s is the input voltage at the resistor end, V c is the required rising voltage, Theoretical charging time; Obtaining a theoretical charging time and an actual charging time, and obtaining a charging difference according to the theoretical charging time and the actual charging time; Comparing the charging difference with a preset difference threshold to obtain a difference comparison result; A charging delay determination is performed according to the difference comparison result to obtain a delay determination result.

[0029] The working principle of the above technical solution is as follows: the parameters involved in the formula include resistance R (in Ω), capacitance C (in F), input voltage Vs (i.e., resistance terminal voltage) and required rise voltage Vc. By substituting these parameters into the formula, the theoretical charging time can be calculated. In the actual circuit, the time from the start of charging to the capacitor voltage reaching the required rise voltage Vc is measured in some way (such as using a timer, counter, or microcontroller's timestamp function), that is, the actual charging time. Compare the theoretical charging time with the actual charging time and calculate the difference between them. Compare the calculated charging difference with the preset difference threshold. If the difference is greater than the preset difference threshold, the charging delay is considered to be successful, and the delay judgment result is "successful". This means that the actual delay time is consistent with expectations and the circuit performance is stable. If the difference is less than or equal to the preset difference threshold, the charging delay is considered to have failed, and the delay judgment result is "failed".

[0030] The technical effect of the above technical solution is: by calculating the theoretical charging time and comparing it with the actual charging time, the charging delay performance of the circuit can be accurately evaluated to determine whether the circuit works as expected. By setting the difference threshold and making a delay judgment, potential problems in the circuit (such as component aging, voltage fluctuations, etc.) can be discovered in time, so that corresponding measures can be taken to repair or adjust and improve the reliability and stability of the circuit. According to the results of the charging delay judgment, the resistors, capacitors and other components in the circuit can be optimized or adjusted to improve the charging delay performance of the circuit to meet specific application requirements. When a circuit fails, by comparing the theoretical charging time with the actual charging time, the problem can be quickly located, providing strong support for troubleshooting and maintenance. In application scenarios where precise control of charging delay is required (such as power management, timing control, etc.), the performance and user experience of the entire system can be improved by ensuring the accuracy and stability of the charging delay.

[0031] In one embodiment of the present invention, S3 includes: When the capacitor C1 is successfully charged and delayed, the gate voltage of the NMOS tube M1 is controlled to rise and be greater than the source voltage, thereby controlling the voltage difference to be greater than 1V, controlling the NMOS tube M1 to be turned on, and the negative voltage is output through the NMOS tube M1; When there is no positive voltage input, the photocoupler U1 is controlled to be cut off, and the resistor R2 is short-circuited through the diode D1; The capacitor C1 is discharged through the resistor R3 and the diode D1, and the positive voltage of the gate of the NMOS tube M1 is converted into a negative voltage, so that there is no voltage difference between the gate and the source, and then the negative voltage is controlled to stop the data; This ultimately achieves positive electricity controlling negative electricity output, and negative electricity output is slower than positive electricity.

[0032] The working principle of the above technical solution is: when there is a positive voltage input, the capacitor C1 is charged. During the charging process, the voltage across the capacitor C1 gradually rises until it reaches a certain threshold. After the charging delay is successful, it means that the capacitor C1 is fully charged or reaches a preset voltage level, which triggers a signal or circuit state change. After the charging delay of the capacitor C1 is successful, its voltage is applied to the gate of the NMOS tube M1 in some way (such as a level converter, a voltage follower, etc.), so that the gate voltage is higher than the source voltage, and this voltage difference is greater than the threshold voltage of the NMOS tube (usually at least 1V to ensure reliable conduction). The NMOS tube M1 is turned on when the gate voltage is higher than the source voltage and the voltage difference is large enough, allowing a negative voltage (which may come from another power supply or circuit part) to be output through the NMOS tube M1. When there is no positive voltage input, the photocoupler U1 is cut off due to insufficient light (or electrical signal). This means that the output end of the photocoupler U1 will not affect the circuit. Resistor R2 is short-circuited through diode D1, which is usually to prevent resistor R2 from generating unnecessary current or voltage effects on the circuit when there is no positive voltage input. When the negative voltage output needs to be stopped, capacitor C1 is discharged through resistor R3 and diode D1. This process releases the charge on capacitor C1, causing the voltage of the gate of NMOS tube M1 to drop. When the gate voltage drops below the source voltage or is insufficient to maintain the conduction of the NMOS tube, NMOS tube M1 is turned off, thereby cutting off the output path of the negative voltage. Due to the charging delay mechanism of capacitor C1, the output of the negative voltage will lag behind the input of the positive voltage in time. This lag can be precisely controlled by adjusting the capacity of capacitor C1, the resistance value of the charging circuit, and the standard for delay determination.

[0033] The technical effect of the above technical solution is: through simple circuit design and logic control, the control of the negative voltage output by the positive voltage input is realized, and the flexibility and functionality of the circuit are increased. Through the charging delay mechanism of the capacitor, it is ensured that the output of the negative voltage lags behind the input of the positive voltage in time, which is very useful in certain application scenarios (such as timing control, anti-misoperation, etc.). Through the cut-off control of the optocoupler U1 and the discharge mechanism of the capacitor C1, the circuit can be effectively protected from unnecessary current or voltage shocks, and the stability and reliability of the circuit can be improved. The circuit structure is relatively simple, easy to integrate into a larger system, and can be flexibly adjusted and optimized according to specific needs. By accurately controlling the output timing and duration of the negative voltage, the energy consumption of the circuit can be reduced to a certain extent and the overall efficiency can be improved.

[0034] In one embodiment of the present invention, the S4 includes: Acquiring circuit control data, and calculating a threshold adjustment coefficient according to the circuit control data; The calculation formula of the threshold adjustment coefficient is:

[0035] Among them, YTX is the threshold adjustment coefficient, α is the basic adjustment factor, Δt s is the actual charging time, Δt l is the theoretical charging time, β is the time deviation index, r is the time standard deviation attenuation factor, is the standard deviation of charging time, Δt a is the average charging time, θ is the voltage gain factor, V g is the maximum voltage difference between the gate and source of the NMOS tube, V t is the threshold voltage of the NMOS tube, V s The supply voltage, i.e. the voltage supplied to the starting circuit; The value ranges of the above factors are set according to specific circuit design requirements and conventional selections.

[0036] Compare the preset adjustment coefficient with the preset coefficient threshold to obtain a threshold comparison result; The threshold is adjusted according to the threshold comparison result to obtain an adjustment result.

[0037] The working principle of the above technical solution is as follows: the system first collects and stores the delay data of the past period of time (such as a few days, hours or several operation cycles). These data may include the actual delay time of each operation or event, as well as various parameters related to it (such as input voltage, ambient temperature, load conditions, etc.). Using the collected historical delay data, a threshold adjustment coefficient is calculated according to a given calculation formula (although the specific formula is not given, it usually involves statistical analysis of historical data, such as mean, standard deviation, median, etc.). This coefficient reflects a certain statistical characteristic or change trend of the historical delay data, and is used to guide the adjustment of subsequent thresholds. The calculated threshold adjustment coefficient is compared with the preset adjustment coefficient threshold. The preset adjustment coefficient threshold is set according to system requirements, experience values ​​or experimental data, and is used to determine whether the currently calculated adjustment coefficient is within an acceptable range. If the threshold adjustment coefficient is within the preset threshold range, it may mean that the current system state is stable and there is no need to make a significant adjustment to the threshold. At this time, the threshold can be fine-tuned or kept unchanged as needed. If the threshold adjustment coefficient exceeds the preset threshold range, it indicates that the system delay characteristics have changed significantly, and the threshold needs to be adjusted accordingly to adapt to this change. The direction and magnitude of the adjustment depend on the specific value of the threshold adjustment coefficient and the preset adjustment strategy.

[0038] The technical effect of the above technical solution is: by dynamically adjusting the threshold, the system can better adapt to changes in the external environment or internal conditions and maintain stable performance and reliability. Threshold adjustment based on historical data can more accurately reflect the actual delay characteristics of the system, thereby optimizing the delay control strategy and reducing misjudgments and missed judgments. In application scenarios that require precise control of delays (such as real-time control systems, data transmission systems, etc.), dynamically adjusting the threshold can improve the response speed and accuracy of the system, thereby improving the user experience. By adjusting the threshold in a timely manner to respond to changes in system status, system crashes or instability caused by abnormal delays can be reduced. The dynamic threshold adjustment mechanism can reduce the need for manual intervention and reduce the complexity and cost of system maintenance. At the same time, through the automated adjustment process, potential problems can be discovered and resolved in a timely manner to avoid the expansion of problems. By , the deviation between the actual charging time and the theoretical charging time is taken into account, and the adjustment coefficient is adjusted according to the size of the deviation. The consideration of charging time stability is introduced, that is, the smaller the discreteness of the charging time, the larger the adjustment coefficient, which means the more stable the system. The influence of the gate voltage of the NMOS tube on the delay is considered. When the gate voltage is close to or exceeds the threshold voltage, the NMOS tube is more likely to turn on, so the adjustment coefficient will increase accordingly. This calculation formula takes into account multiple factors such as time deviation, time stability and voltage gain, which can more accurately reflect the changes in the system delay characteristics and adjust the threshold accordingly. By dynamically adjusting the threshold, the system can more flexibly respond to changes in various working conditions and external environments. When the system detects that the charging time or other related parameters deviate from the theoretical value, it can automatically adjust the threshold to adapt to these changes, thereby maintaining the stability and reliability of the system. Reasonable adjustment of the threshold can optimize the performance of the system. For example, in the case of a short charging time, appropriately lowering the threshold can reduce unnecessary delays and improve the response speed of the system. On the contrary, in the case of a long charging time or poor system stability, increasing the threshold can ensure that the system has enough time to work stably and avoid misjudgment or premature termination of the delay process. Different application scenarios and working environments may have different requirements for the system's delay. By adjusting the threshold, the system can adapt to different working requirements and ensure that it can work normally under various conditions. This adaptability is particularly important for systems that need to be widely deployed and applied. In actual applications, the system may be affected by various interferences and noises, resulting in deviations in the measured data. By dynamically adjusting the threshold, the system can be more tolerant of these deviations, reducing the possibility of misjudgment and misoperation, thereby improving the system's fault tolerance. When the system detects that the charging time or other related parameters continue to deviate from the theoretical value, it may mean that there is a fault or problem in the system. At this time, by adjusting the threshold and observing the system's response, engineers can quickly locate the problem and take appropriate measures to troubleshoot and repair it.

[0039] In one embodiment of the present invention, the circuit comprises: A control circuit construction module, used for inputting voltage to a startup circuit through an external power supply, and constructing a power-on sequence circuit through the external power supply and the startup circuit; An isolation module is used to isolate the circuit input and output using a photocoupler; A voltage division module, used for voltage division control of input voltage; The delay control module is used to control the delay of the circuit through capacitor C1 to obtain the delay control result, such as Figure 2 shown.

[0040] The working principle of the above technical solution is: receiving voltage input from an external power supply. The external power supply provides stable power and supplies voltage to the startup circuit in an orderly manner through the control circuit building module. This means that when the system starts, it can ensure that each part is powered on in a predetermined order to avoid circuit damage or malfunction caused by improper power-on sequence. By accurately controlling the input timing of the voltage, the module ensures the stable operation and efficient coordination of various parts of the system. Optocouplers are used to achieve electrical isolation between circuit input and output. Optocouplers transmit electrical signals through optical signals, effectively isolating the electrical connection between the input side and the output side, thereby avoiding interference, noise or fault propagation that may be introduced by direct electrical connection. This isolation mechanism improves the safety and reliability of the system, especially when dealing with high voltage, high current or sensitive signals. The function of the voltage divider module is to accurately control the input voltage to meet the different voltage level requirements of subsequent circuits. Through a reasonable resistor voltage divider network design, a higher input voltage can be reduced to a voltage range suitable for the operation of specific circuit components. The voltage divider module ensures that each component in the system can receive a stable voltage that meets its working requirements, thereby improving the overall performance and stability of the system. The delay control module uses the charging and discharging characteristics of capacitor C1 to achieve delay control of the circuit. When the circuit receives a start signal, capacitor C1 begins to charge, and its charging process takes a certain amount of time. During this period of time, by detecting the voltage change across capacitor C1, the output of the subsequent circuit can be controlled to achieve a delay effect. The delay control module plays an important role in timing adjustment in the system. It can adjust the startup time or action sequence of the circuit as needed, avoiding circuit failures caused by instantaneous current shocks or timing mismatches.

[0041] The technical effects of the above technical solution are: by precisely controlling the power-on sequence and voltage division, circuit failures caused by voltage fluctuations or improper timing are reduced, and the overall stability of the system is improved. The isolation effect of the photoelectric coupler effectively isolates the electrical connection between circuits, prevents fault propagation and electrical interference, and enhances the safety of the system. The delay control module provides the system with flexible timing adjustment capabilities, which can adjust the startup time and action sequence of the circuit according to specific needs, enhancing the adaptability and flexibility of the system. By precisely controlling the voltage and timing, it is ensured that each component in the system can work in the best state, thereby optimizing the overall performance of the system. By improving the stability and reliability of the system, the downtime and maintenance costs caused by failures are reduced, and the overall maintenance cost of the system is reduced.

[0042] In one embodiment of the present invention, the control circuit building module includes: Connecting the positive voltage output terminal of the external power supply to the positive voltage input terminal of the start-up circuit; A power-on sequence control circuit is constructed by an external power supply and a startup circuit, wherein the startup circuit includes a photocoupler U1, a capacitor C1, multiple resistors, a diode D1 and an NMOS tube M1; The plurality of resistors include a resistor R1 , a resistor R2 , a resistor R3 , and a resistor R4 .

[0043] The working principle of the above technical solution is: the external power supply provides a stable positive voltage, which is connected to the positive voltage input terminal of the startup circuit through a wire. This is the basis for the operation of the entire circuit. Capacitor C1 plays a delay role in the circuit. When the power supply is powered on, capacitor C1 starts to charge, and the voltage across it gradually rises during the charging process. This delay process can be controlled by adjusting the capacitance of the capacitor and the resistance value of the charging circuit. After the delay is over, the state change of capacitor C1 (such as the voltage reaching a certain threshold) will trigger the action of the subsequent circuit. Resistors R1, R2, R3, and R4 may play a role in voltage division and current limiting in the circuit. It can divide the input voltage into a range suitable for the operation of subsequent components (such as optocoupler U1, NMOS tube M1, etc.), and limit the current to prevent damage to the components. Diode D1 may be used to protect certain components in the circuit from reverse voltage damage. When a reverse voltage appears in the circuit, diode D1 will turn on, short-circuit the reverse voltage to the ground, thereby protecting the subsequent circuit. As a switching element, NMOS tube M1 is turned on or off under the action of a control signal. When the capacitor C1 is fully charged and certain conditions are met (such as the gate voltage is higher than the source voltage by a certain value), the NMOS tube M1 is turned on, allowing current to pass through its channel, thereby controlling the on and off of subsequent circuits.

[0044] The technical effect of the above technical solution is: through a carefully designed circuit, the power-on sequence of each component when the external power supply is supplied is controlled. This helps to avoid circuit damage or malfunction caused by improper power-on sequence. The use of optocoupler U1 for electrical isolation improves the safety of the circuit. At the same time, components such as diode D1 also play a role in protecting the circuit. By adjusting the parameters of components such as resistors and capacitors, the delay time and working state of the circuit can be flexibly controlled to meet the needs of different application scenarios. The use of common electronic components (such as resistors, capacitors, diodes, NMOS tubes, etc.) to construct a power-on sequence control circuit reduces the cost of the system. Through reasonable circuit design and component selection, the overall reliability and stability of the system are improved.

[0045] In one embodiment of the present invention, the isolation module comprises: The positive voltage input terminal and the negative voltage input terminal of R1 are the positive voltage input terminal and the negative voltage input terminal of the startup circuit; The positive voltage output terminal of R1 is connected to the anode of the photoelectric coupler, and the cathode and collector of the photoelectric coupler are grounded respectively; the emitter of the photoelectric coupler is connected to the positive voltage input terminal of the resistor R4.

[0046] The working principle of the above technical solution is: when the positive voltage of the external power supply is input through the positive voltage input terminal of R1, R1 acts as a voltage divider resistor (if there are other voltage divider resistors in the circuit, R1 may be only a part of them), and outputs the voltage after voltage division to the anode of the photocoupler. It is assumed here that the negative voltage input terminal of R1 (that is, the negative voltage input terminal of the circuit) is grounded to form a complete voltage loop. The anode of the photocoupler receives the voltage after voltage division from R1. When the voltage reaches the trigger threshold of the photocoupler, the internal light-emitting diode emits light, thereby driving the phototransistor to turn on. The cathode and collector of the photocoupler are grounded, which is a common connection method used to ensure that the phototransistor is in the cut-off state when there is no signal. The emitter of the photocoupler is connected to the positive voltage input terminal of resistor R4. When the phototransistor is turned on, the emitter outputs a lower voltage (relative to the anode voltage), and this voltage signal is transmitted to the subsequent circuit through R4. Resistor R4 may be used for further voltage division or current limiting to protect components in subsequent circuits. Subsequently, this voltage signal can be used to control other circuit elements (such as the gate voltage of the NMOS tube M1), thereby controlling the on and off of the circuit or realizing other logic functions.

[0047] The technical effect of the above technical solution is: the photoelectric coupler provides an electrical isolation function, effectively cuts off the electrical connection between the input circuit and the output circuit, and prevents the propagation of interference, noise or faults that may be introduced by direct electrical connection. The photoelectric coupler can reliably convert the input signal (voltage signal) into an optical signal, and then convert the optical signal into an electrical signal output, thereby realizing the isolated transmission of the signal. The voltage division and current limiting effect of resistors R1 and R4 protect the photoelectric coupler and other subsequent circuit components from damage caused by excessive voltage or current. The use of photoelectric couplers improves the overall reliability of the system, especially when dealing with high voltage, high current or sensitive signals, it can reduce system instability caused by electrical interference or faults. By using standard components such as photoelectric couplers to build circuits, the circuit design process is simplified, and the design difficulty and cost are reduced. By adjusting the resistance values ​​of resistors R1 and R4, the trigger voltage of the photoelectric coupler and the working state of the subsequent circuit can be flexibly controlled to meet the needs of different application scenarios.

[0048] In one embodiment of the present invention, the voltage dividing module comprises: The positive voltage output end of the resistor R4 is connected to the positive voltage input end of the resistor R3, the positive voltage output end of the resistor R3 is connected to the negative voltage input end, the resistor R3 is connected in series with the resistor R4, and the central node where the resistor R4 and the resistor R3 are connected is respectively connected to the positive voltage input end of the resistor R2 and the cathode of the diode D1.

[0049] The working principle of the above technical solution is as follows: resistors R4 and R3 are connected in series to jointly divide the voltage input to the positive voltage input terminal of R4. When a voltage source (which may be the voltage obtained by voltage division by R1) is connected to the positive voltage input terminal of R4, the voltage will be distributed on R4 and R3 according to the ratio of their resistance values. The voltage at the central node (i.e., the connection point between them) where R4 and R3 are connected is the result of the voltage division of these two resistors. This voltage value depends on the input voltage, the resistance values ​​of R4 and R3. The voltage at the central node is also provided to the positive voltage input terminal of resistor R2. This means that R2 will perform further processing or voltage division based on this voltage value (if there are other circuit elements behind R2). The cathode of diode D1 is connected to the central node, and the positive electrode is used to protect the circuit. When the voltage at the central node is higher than the forward conduction voltage of diode D1, D1 will be in a reverse cutoff state and will not conduct current. However, if the voltage at the center node unexpectedly becomes very low (close to or below the negative voltage terminal), D1 will turn on, clamping the center node voltage near the forward voltage of the diode, thereby protecting subsequent circuits from damage by negative voltage.

[0050] The technical effect of the above technical solution is: through the series voltage division of R4 and R3, the circuit can adjust the voltage value of the central node as needed, and provide a suitable voltage reference for the subsequent circuit. At the same time, the series connection of resistors also plays a role in current limiting, preventing excessive current from damaging circuit components. This circuit structure helps to stabilize the voltage of the central node so that it can still maintain a relatively stable value when it fluctuates within a certain range, thereby improving the working stability of the subsequent circuit. The addition of diode D1 provides reverse voltage protection for the circuit. In abnormal circumstances, such as when the voltage of the central node suddenly drops to a negative value, D1 can quickly turn on and clamp the voltage within a safe range to prevent damage to subsequent circuit components. By adjusting the resistance values ​​of R4, R3 and R2, the voltage value of the central node and the working state of the subsequent circuit can be flexibly controlled to meet the needs of different application scenarios. The circuit structure is constructed using common resistors and diode components, which reduces costs and improves the maintainability of the system.

[0051] In one embodiment of the present invention, the delay control module includes: The positive voltage output end of the resistor R2 is connected to the positive electrode of the diode D1 to form a first intersection; The first intersection is connected to the positive voltage input terminal of the capacitor C1 and the gate of the NMOS tube respectively; The negative voltage input terminal of the capacitor C1 is connected to the source of the NMOS tube to form a second intersection; The second intersection is connected to the negative voltage input terminal; The NMOS tube MI is connected to the negative voltage output terminal.

[0052] The working principle of the above technical solution is as follows: the resistor R2 receives the voltage from the previous circuit and passes it to the positive electrode of the diode D1 and the positive voltage input terminal of the capacitor C1. Here, R2 plays the role of voltage division and current limiting. The positive electrode of the diode D1 is connected to the positive voltage output terminal of R2, and the negative electrode is connected to the negative voltage input terminal of the circuit. When the voltage output by R2 is higher than the forward conduction voltage of the diode D1, D1 is in a reverse cutoff state and does not conduct current. If the voltage output by R2 suddenly drops to a negative value or approaches the negative voltage input terminal, D1 will turn on and clamp the voltage near the forward conduction voltage of the diode, thereby protecting the subsequent circuit from damage by negative voltage. However, in this particular configuration, since the negative electrode of D1 is directly grounded, it provides protection against excessive positive voltage, but its protective effect may be limited in this scenario, because we usually expect the diode to provide protection when the negative voltage is abnormal. The positive voltage input terminal of capacitor C1 receives the voltage from R2 and D1 (it may be attenuated after passing through D1, but in this configuration D1 mainly plays a protective role and has little effect on voltage attenuation). The negative voltage input terminal of capacitor C1 is connected to the source of NMOS tube M1. When the power is turned on, capacitor C1 begins to charge, and the voltage across it gradually rises. This charging process takes a certain amount of time, forming a circuit delay. The delay time depends on the capacity of capacitor C1 and the resistance of the charging circuit. The gate of NMOS tube M1 is connected to the positive voltage input terminal of capacitor C1, the source is connected to the negative voltage input terminal of capacitor C1, and the drain is connected to the negative voltage output terminal. When capacitor C1 is charged to a certain voltage, NMOS tube M1 is turned on, allowing current to flow from the drain to the source. In this way, NMOS tube M1 acts as a switch to control the on and off of the negative voltage output terminal.

[0053] The technical effect of the above technical solution is: through the delay effect of capacitor C1, the circuit realizes precise control of the conduction time of NMOS tube M1. This helps to avoid instantaneous current shock when the system starts and protects subsequent circuits from damage. Diode D1 provides protection against negative voltage anomalies to a certain extent, although its protective effect in this particular configuration may not be as significant as in the negative voltage protection scenario. By precisely controlling the conduction time of NMOS tube M1, the circuit can ensure the coordinated work of various parts during the system startup process, thereby improving the overall stability of the system. By adjusting the parameters of resistor R2, capacitor C1 and the model of NMOS tube M1, the delay time and working characteristics of the circuit can be flexibly adjusted to meet the needs of different application scenarios. The circuit is constructed using common electronic components, which reduces costs and improves the maintainability of the system.

[0054] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A power-on sequence control method, characterized in that: The method comprises: S1, after inputting positive voltage to the startup circuit, obtains negative voltage through the conduction of the photocoupler and the voltage division of resistors R3 and R4, and uses the charging of the capacitor for delay, thereby controlling the conduction of the NMOS tube; S2. Calculate the theoretical charging time and compare it with the actual charging time to obtain the charging difference. According to the comparison between the charging difference and the preset difference threshold, determine whether the delay is successful and obtain the delay determination result. S3, by controlling the gate voltage of the NMOS tube to rise, the NMOS tube is turned on, a negative voltage is output, the capacitor is discharged, the gate voltage of the NMOS tube is converted to a negative voltage, and the output of the negative voltage is stopped; S4. Calculate the threshold adjustment coefficient, compare the calculated adjustment coefficient with the preset coefficient threshold, adjust the threshold according to the comparison result, and obtain the adjustment result.

2. A power-on sequence control method according to claim 1, characterized in that: The S1 includes: When a positive voltage is input to the circuit startup circuit, the photocoupler is controlled to be turned on, and the negative voltage is divided by resistors R3 and R4 respectively, and the voltage of resistor R4 is greater than the negative voltage; When there is no voltage difference between the gate and source of the NMOS tube, the NMOS tube is controlled not to conduct, and there is no negative voltage output; The capacitor is charged through the resistor R2, and the charging time is the negative voltage output delay time.

3. A power-on sequence control method according to claim 1, characterized in that: The S2 includes: The calculation formula of the theoretical charging time is:

4. Among them, The unit of resistance is Ω, the unit of capacitance is F, V s is the input voltage at the resistor end, V c is the required rising voltage, Theoretical charging time; Obtaining a theoretical charging time and an actual charging time, and obtaining a charging difference according to the theoretical charging time and the actual charging time; Comparing the charging difference with a preset difference threshold to obtain a difference comparison result; A charging delay determination is performed according to the difference comparison result to obtain a delay determination result.

5. A power-on sequence control method according to claim 1, characterized in that: The S3 includes: When the capacitor charging delay is successful, the gate voltage of the NMOS tube is controlled to rise and is greater than the source voltage, thereby controlling the voltage difference to be greater than 1V, controlling the NMOS tube to be turned on, and the negative voltage is output through the NMOS tube; When there is no positive voltage input, the photocoupler is controlled to be cut off, and the resistor R2 is short-circuited through the diode; The capacitor is discharged through the resistor R3 and the diode, and the positive voltage of the gate of the NMOS tube is converted into a negative voltage, so that there is no voltage difference between the gate and the source, and the negative voltage is controlled to stop the data.

6. A power-on sequence control method according to claim 1, characterized in that: The S4 includes: Acquiring circuit control data, and calculating a threshold adjustment coefficient according to the circuit control data; The calculation formula of the threshold adjustment coefficient is: Among them, YTX is the threshold adjustment coefficient, α is the basic regulatory factor, Δt s is the actual charging time, Δt l is the theoretical charging time, β is the time deviation index, r is the time standard deviation attenuation factor, is the standard deviation of charging time, Δt a is the average charging time, θ is the voltage gain factor, V g is the maximum voltage difference between the gate and source of the NMOS tube, V t is the threshold voltage of the NMOS tube, V s The supply voltage, i.e. the voltage supplied to the starting circuit; Compare the preset adjustment coefficient with the preset coefficient threshold to obtain a threshold comparison result; The threshold is adjusted according to the threshold comparison result to obtain an adjustment result.

7. A power-on sequence control circuit, characterized in that: The circuit comprises: A control circuit construction module, used for inputting voltage to a startup circuit through an external power supply, and constructing a power-on sequence circuit through the external power supply and the startup circuit; An isolation module is used to isolate the circuit input and output using a photocoupler; A voltage division module, used for voltage division control of input voltage; The delay control module is used to perform delay control of the circuit through a capacitor to obtain a delay control result.

8. A power-on sequence control circuit according to claim 6, characterized in that: The control circuit building block includes: Connecting the positive voltage output terminal of the external power supply to the positive voltage input terminal of the start-up circuit; A power-on sequence control circuit is constructed by an external power supply and a startup circuit, wherein the startup circuit includes a photocoupler, a capacitor, multiple resistors, a diode and an NMOS tube; The plurality of resistors include a resistor R1 , a resistor R2 , a resistor R3 , and a resistor R4 .

9. A power-on sequence control circuit according to claim 7, characterized in that: The isolation module comprises: The positive voltage input terminal and the negative voltage input terminal of the resistor R1 are the positive voltage input terminal and the negative voltage input terminal of the startup circuit; The positive voltage output terminal of the resistor R1 is connected to the anode of the photoelectric coupler, and the cathode and collector of the photoelectric coupler are grounded respectively; the emitter of the photoelectric coupler is connected to the positive voltage input terminal of the resistor R4.

10. A power-on sequence control circuit according to claim 7, characterized in that: The voltage divider module comprises: The positive voltage output end of the resistor R4 is connected to the positive voltage input end of the resistor R3, the positive voltage output end of the resistor R3 is connected to the negative voltage input end, the resistor R3 is connected in series with the resistor R4, and the central node where the resistor R4 and the resistor R3 are connected is respectively connected to the positive voltage input end of the resistor R2 and the cathode of the diode.

11. A power-on sequence control circuit according to claim 7, characterized in that: The delay control module comprises: The positive voltage output end of the resistor R2 is connected to the positive electrode of the diode to form a first intersection; The first intersection is connected to the positive voltage input terminal of the capacitor and the gate of the NMOS tube respectively; The negative voltage input terminal of the capacitor is connected to the source of the NMOS tube to form a second intersection; The second intersection is connected to the negative voltage input terminal; The NMOS tube is connected to the negative voltage output terminal.

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