Phase self-feedback-based AD or DA synchronization method and system

Abstract

The invention belongs to the technical field of high-speed signal acquisition and output, particularly relates to an AD (Analog to Digital) chip or DA (Digital to Analog) chip synchronization method and system based on phase self-feedback, and aims to solve the problems that two chips in the existing system are difficult to keep synchronous and are easily influenced by environment temperature. The method comprises the following steps of: initializing two paths of SYNC signal delays; sYNC signal delay is carried out on the two paths; each time of SYNC signal delay corresponds to one delay value; each SYNC signal is delayed, the SYNC signals are sent for two paths for 32 times, and clock phase discrimination is carried out to obtain a training code; screening the SYNC signal delay of delay stable reset; for the stable reset SYNC signal delay, selecting the training code word with the highest occurrence frequency as the synchronous code word of the two paths; and selecting the median of the delay value of the continuous delay stable reset as the input of the two paths. According to the invention, automatic synchronization of two paths of AD or two paths of DA is realized, and the time of manual synchronization adjustment is greatly reduced.

Description

Background Art

[0002] In current radar jamming systems, IQ orthogonal channel sampling jammers are often used. On the one hand, the sampling rate can be reduced, and on the other hand, phase information can be retained, with a larger dynamic range and higher precision, which facilitates signal processing and data demodulation. However, the corresponding AD / DA system requires two AD chips for sampling, two DA chips for digital-to-analog conversion output, and strict synchronization between the chips. In addition, the synchronization of AD / DA is easily affected by the ambient temperature. Based on current technology, it is difficult for two AD chips to maintain synchronization and they are easily affected by the ambient temperature.

[0003] Therefore, it is difficult for the two AD chips in the existing AD / DA system to maintain synchronization and they are easily affected by the ambient temperature. Summary of the invention

[0004] In order to solve the above-mentioned problem in the prior art, that is, the problem that two AD chips in the existing AD / DA system are difficult to keep synchronized and are easily affected by the ambient temperature, the present invention provides a synchronization method of AD or DA based on phase self-feedback, the method comprising:

[0005] Initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter;

[0006] Delaying the SYNC signal of the two paths; each SYNC signal delay corresponds to a delay value; each time the SYNC signal is delayed, SYNC signals are sent 32 times to the two paths and clock phase detection is performed to obtain training codes, and the training codes obtained by each SYNC signal transmission are stored in the synchronization code word search function module RAM;

[0007] Screening the SYNC signal delay for stable reset; specifically, including: for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then determining that the SYNC signal delay is stable reset;

[0008] Under the SYNC signal delay corresponding to multiple continuous delay values, for the SYNC signal delay of stable reset, select the training codeword with the largest number of occurrences as the synchronization codeword of the two channels; select the median of the delay value of continuous delay stable reset as the input of the two channels.

[0009] In a preferred embodiment, the method for performing clock phase detection to obtain a training code includes:

[0010] For each SYNC signal delay, the input clock of the second converter is adjusted at the PS level through the FPGA Select IO core, and the input clock of the second converter is used as the reference signal; the input clock of the first converter is used as the sampling clock, and the sampling clock is used to sample the reference signal at the rising and falling edges. The training code is obtained by sampling the reference signal of the SYNC signal 0-31 times and input into the Select IO core. A 32-bit register is used to store the training code, and each bit represents the phase detection result of the bit position to obtain the training code.

[0011] In a preferred implementation, delaying the two SYNC signals includes:

[0012] For the transmission of two-way SYNC delay signals, in the initial stage, a SYNC pulse is generated through initialization reset pulse or through registering to ODELAY, and the delay from the OR gate to the two-way ODELAY input is kept equal through constraints; among them, the AD clock uses a quarter-frequency clock of the DA data clock, and the DA clock uses a quarter-frequency clock of the AD data clock.

[0013] In a preferred embodiment, the two paths further include:

[0014] The two-path programs use the same fixed routing constraints to ensure that the routing delay between SYNC signals does not change when the programs are modified.

[0015] In a preferred embodiment, the method for calculating the Hamming distance between the subsequent 31 training codes and the first training code includes:

[0016] By performing an XOR operation on two code words and calculating the number of inconsistent bits in the XOR result, the Hamming distance between the two code words is obtained.

[0017] In a second aspect of the present invention, a synchronization system of AD or DA based on phase self-feedback is proposed, the system comprising:

[0018] An initialization module is used to initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter;

[0019] A signal delay module is used to delay the SYNC signals of the two channels; each SYNC signal delay corresponds to a delay value; each time the SYNC signal is delayed, SYNC signals are sent 32 times to the two channels and clock phase detection is performed to obtain training codes, and the training codes obtained by each SYNC signal transmission are stored in the synchronization code word search function module RAM;

[0020] The delay screening module is used to screen the SYNC signal delay for delay stability reset; specifically, for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then it is determined that the SYNC signal delay is stable reset;

[0021] The delay value determination module is used to select the training codeword with the largest number of occurrences as the synchronization codeword of the two paths for the stable reset SYNC signal delay corresponding to multiple continuous delay values; and select the median of the delay value of the continuous delay stable reset as the input of the two paths.

[0022] The third aspect of the present invention proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned AD or DA synchronization method based on phase self-feedback.

[0023] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned AD or DA synchronization method based on phase self-feedback.

[0024] Beneficial effects of the present invention:

[0025] (1) The present invention realizes the automatic synchronization of two ADs or two DAs in FPGA, which greatly reduces the time of manual synchronization adjustment and reduces the cost;

[0026] (2) The present invention can be applied to environments with variable working temperatures, thus expanding the working scenarios;

[0027] (3) The present invention can be applied to scenarios with high requirements for sampling or output synchronization and temperature changes in the working environment to achieve adaptive synchronization between two AD chips and two DA chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0029] Figure 1 is a schematic diagram of a synchronization method of AD or DA based on phase self-feedback according to an embodiment of the present invention;

[0030] Figure 2 It is a schematic diagram of an implementation module of a synchronization method of AD or DA based on phase self-feedback according to an embodiment of the present invention;

[0031] Figure 3 It is a schematic diagram of performing clock phase detection on two paths to obtain a training code according to an embodiment of the present invention;

[0032] Figure 4 It is a structural diagram of a computer system of a server for implementing the method, system, and device embodiments of the present application. DETAILED DESCRIPTION

[0033] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] The present invention provides a synchronization method of AD or DA based on phase self-feedback, the method comprising:

[0036] Initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter;

[0037] Delaying the SYNC signal of the two paths; each SYNC signal delay corresponds to a delay value; for each SYNC signal delay, sending SYNC signals 32 times to the two paths and performing clock phase detection to obtain training codes, and storing the training codes obtained by each SYNC signal transmission into the synchronization code word search function module RAM;

[0038] Screening the SYNC signal delay for stable reset; specifically, including: for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then determining that the SYNC signal delay is stable reset;

[0039] Under multiple continuous delay values ​​of SYNC signal delay, for the stable reset SYNC signal delay, select the training codeword with the largest number of occurrences as the synchronization codeword of the two channels; select the median of the delay value of the continuous delay stable reset as the input of the two channels.

[0040] In order to more clearly explain the AD or DA synchronization method based on phase self-feedback of the present invention, the following is combined with Figure 1 Each step in the embodiment of the present invention is described in detail.

[0041] The steps of the AD or DA synchronization method based on phase self-feedback of the first embodiment of the present invention are described in detail as follows:

[0042] Initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter;

[0043] In this embodiment, initializing the delay of two SYNC signals includes: for the sending of two SYNC delay signals, in the initial stage, a SYNC pulse is generated by initializing a reset pulse or by registering to ODELAY, and the delay from the OR gate to the two ODELAY inputs is kept equal by constraints; wherein, the AD clock uses a quarter-frequency clock of the DA data clock, and the DA clock uses a quarter-frequency clock of the AD data clock.

[0044] Delaying the SYNC signal of the two channels; each SYNC signal delay corresponds to a delay value; for each SYNC signal delay, sending SYNC signals 32 times to the two channels and performing clock phase detection to obtain a training code for characterizing the phase difference between the two clocks, and storing the training code obtained by sending the SYNC signal each time into the synchronization code word search function module RAM;

[0045] In this embodiment, the method for performing clock phase detection to obtain a training code includes: for each SYNC signal delay, the input clock of the second converter is adjusted at the PS level through the FPGA Select IO core, and the input clock of the second converter is used as a reference signal; the input clock of the first converter is used as a sampling clock, and the reference signal is sampled at the rising and falling edges using the sampling clock, and the training code is obtained by sampling the reference signal of the SYNC signal 0-31 times and inputting it into the Select IO core, and a 32-bit register is used to store the training code, and each bit represents the phase detection result of the bit position to obtain the training code.

[0046] In this embodiment, the two paths also include: to ensure that the length between the SYNCs of the two ADs or two DAs is equal, the programs of the two paths use the same fixed routing constraints to ensure that the routing delay between the SYNC signals will not change when the program is modified.

[0047] Screening the SYNC signal delay of delayed stable reset; specifically including: for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then determine that the SYNC signal delay is stable reset; record the stable reset state under each SYNC signal, and summarize all situations into a register.

[0048] In this embodiment, the method for calculating the Hamming distance between the subsequent 31 training codes and the first training code includes: performing an XOR operation on two code words, calculating the number of inconsistent bits of the XOR result, and obtaining the Hamming distance between the two code words.

[0049] Under multiple continuous delay values ​​of SYNC signal delay, for the stable reset SYNC signal delay, select the training codeword with the largest number of occurrences as the synchronization codeword of the two channels; select the median of the delay value of the continuous delay stable reset as the input of the two channels.

[0050] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0051] A second embodiment of the present invention is a synchronous system of AD or DA based on phase self-feedback, the system comprising:

[0052] An initialization module is used to initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter;

[0053] A signal delay module is used to delay the SYNC signals of the two channels; each SYNC signal delay corresponds to a delay value; each time the SYNC signal is delayed, SYNC signals are sent 32 times to the two channels and clock phase detection is performed to obtain training codes, and the training codes obtained by each SYNC signal transmission are stored in the synchronization code word search function module RAM;

[0054] The delay screening module is used to screen the SYNC signal delay for delay stability reset; specifically, for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then it is determined that the SYNC signal delay is stable reset;

[0055] The delay value determination module is used to select the training codeword with the largest number of occurrences as the synchronization codeword of the two paths for the stable reset SYNC signal delay corresponding to multiple continuous delay values; and select the median of the delay value of the continuous delay stable reset as the input of the two paths.

[0056] In this embodiment, 32 SYNC signal delays are sent, corresponding to 32 delay values. The 32 delay values ​​are sent in order of size. The longest continuous delay value corresponding to the delay stable reset is selected as the delay value of the continuous delay stable reset. The median of this delay value is the input of the two converters.

[0057] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0058] It should be noted that the AD or DA synchronization system based on phase self-feedback provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0059] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned AD or DA synchronization method based on phase self-feedback.

[0060] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned AD or DA synchronization method based on phase self-feedback.

[0061] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and storage medium described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0062] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0063] Reference below Figure 4 , which shows a schematic diagram of the structure of a computer system of a server for implementing the method, system, and device embodiments of the present application. Figure 4 The server shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0064] like Figure 4 As shown, the computer system includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 to the random access memory (RAM) 603. Various programs and data required for system operation are also stored in the RAM 603. The CPU 601, ROM 602 and RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0065] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read therefrom is installed into the storage section 608 as needed.

[0066] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the above-mentioned functions defined in the method of the present application are executed. It should be noted that the above-mentioned computer-readable medium of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0067] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0068] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0069] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0070] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0071] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A synchronization method of AD or DA based on phase self-feedback, characterized in that: The method comprises: Initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter; Delaying the SYNC signal of the two paths; each SYNC signal delay corresponds to a delay value; for each SYNC signal delay, sending SYNC signals 32 times to the two paths and performing clock phase detection to obtain training codes, and storing the training codes obtained by each SYNC signal transmission into the synchronization code word search function module RAM; Screening the SYNC signal delay for stable reset; specifically, including: for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then determining that the SYNC signal delay is stable reset; Under the SYNC signal delay corresponding to multiple continuous delay values, for the SYNC signal delay of stable reset, the training codeword with the largest number of occurrences is selected as the synchronization codeword of the two channels; the median of the delay value of the continuous delay stable reset is selected as the input of the two channels.

2. The AD or DA synchronization method based on phase self-feedback according to claim 1, characterized in that: Methods for performing clock phase detection to obtain training codes include: For each SYNC signal delay, the input clock of the second converter is adjusted at the PS level through the FPGA Select IO core, and the input clock of the second converter is used as the reference signal; the input clock of the first converter is used as the sampling clock, and the sampling clock is used to sample the reference signal at the rising and falling edges. The training code is obtained by sampling the reference signal of the SYNC signal 0-31 times and input into the Select IO core. A 32-bit register is used to store the training code, and each bit represents the phase detection result of the bit position to obtain the training code.

3. The AD or DA synchronization method based on phase self-feedback according to claim 2, characterized in that: The SYNC signal delay for initializing the two converters on both sides includes: For the transmission of two-way SYNC delay signals, in the initialization stage, a SYNC pulse is generated through initialization reset pulse or through registering to ODELAY, and the delay from the OR gate to the two-way ODELAY input is kept equal through constraints; among them, the AD clock uses a quarter-frequency clock of the DA data clock, and the DA clock uses a quarter-frequency clock of the AD data clock.

4. The AD or DA synchronization method based on phase self-feedback according to claim 3, characterized in that: The two paths also include: The two-path programs use the same fixed routing constraints to ensure that the routing delay between SYNC signals does not change when the programs are modified.

5. The AD or DA synchronization method based on phase self-feedback according to claim 4, characterized in that: The method for calculating the Hamming distance between the following 31 training codes and the first training code includes: By performing an XOR operation on two code words and calculating the number of inconsistent bits in the XOR result, the Hamming distance between the two code words is obtained.

6. A synchronization system of AD or DA based on phase self-feedback, characterized in that: The system comprises: An initialization module is used to initialize the SYNC signal delay of two converters of two channels; the two converters are two ADs or two DAs; each channel corresponds to one converter; A signal delay module is used to delay the SYNC signals of the two channels; each SYNC signal delay corresponds to a delay value; each time the SYNC signal is delayed, SYNC signals are sent 32 times to the two channels and clock phase detection is performed to obtain training codes, and the training codes obtained by each SYNC signal transmission are stored in the synchronization code word search function module RAM; The delay screening module is used to screen the SYNC signal delay for delay stability reset; specifically, for each SYNC signal delay corresponding to 32 SYNC signals, if the Hamming distance between the subsequent 31 training codes and the first training code is less than 3, then it is determined that the SYNC signal delay is stable reset; The delay value determination module is used to select the training codeword with the largest number of occurrences as the synchronization codeword of the two paths for the stable reset SYNC signal delay corresponding to multiple continuous delay values; and select the median of the delay value of the continuous delay stable reset as the input of the two paths.

7. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to at least one of the processors; wherein, The memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the synchronization method of the AD chip and the DA chip based on phase self-feedback as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the synchronization method of an AD chip and a DA chip based on phase self-feedback as described in any one of claims 1-5.

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