Write energy consumption optimization method for STT-MRAM read disturbance
By dividing the line buffer of STT-MRAM into multiple data blocks and using a write update recorder and a comparison recorder, only the data blocks that need to be written back are written back, which solves the STT-MRAM storage unit during the read operation. Read disturbance problem reduces write energy consumption and improves storage efficiency.
Patent Information
- Application Number
- CN202411351967.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-02-11
AI Technical Summary
STT-MRAM memory cells are susceptible to read disturbances during read operations, resulting in data bit errors, thereby increasing write energy consumption. This problem becomes more prominent in deep submicron processes.
By dividing the line buffer of STT-MRAM into multiple data blocks and equipped with a write update recorder and a comparison recorder, the write update status and comparison status of each data block are tracked. When a write update or read disturbance is detected, only the data blocks that need to be written back are written back, not the entire memory line.
This method reduces unnecessary data block write back operations, reduces write energy consumption, improves storage efficiency, and alleviates the high energy consumption problems caused by read disturbances.
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Figure CN119415020A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for optimizing write energy consumption of STT-MRAM read disturbance. Background Art
[0002] Spin-transfer torque magnetoresistive memory (STT-MRAM) is an emerging and increasingly popular non-volatile storage technology. Due to its zero refresh power consumption and data non-volatility, STT-MRAM is widely believed to replace DRAM as a new generation of general storage solution.
[0003] An STT-MRAM memory cell, such as Figure 1 As shown, it includes an access transistor and a magnetic tunnel junction MTJ. STT-MRAM relies on the resistance of the MTJ to store data. The MTJ contains two ferromagnetic layers separated by an oxide barrier layer. The magnetization direction of the fixed layer Fixed Layer is fixed, but the magnetization direction of the free layer Free Layer can change, resulting in the magnetic field of the free layer and the fixed layer being in the same or opposite direction, and the same direction and the opposite direction correspond to different resistances. The difference in resistance can represent the 0 and 1 values of a bit. To write data to the MTJ, that is, to change the magnetization direction of the free layer, it is necessary to apply a voltage between the Sense Line (SL) and the Bit Line (BL), see Table 1 for details. Reading data is also achieved by applying a voltage between SL and BL, but the read current does not have the strict direction requirements when writing data.
[0004] Table 1. Relationship between read and write operations and operating voltage / current.
[0005] operate Voltage and Current Write 0 A positive voltage is applied between SL and BL to generate a write current in the direction of SL->BL Write 1 A negative voltage is applied between SL and BL to generate a write current in the direction of BL->SL Read Data Apply voltage to SL and BL, and read the data value by sensing the current size
[0006] With the development of process technology, the write current in the STT-MRAM memory cell decreases rapidly as the memory cell shrinks, while the read current remains basically constant under the limitation of the sense amplifier. Therefore, the magnitude of the read and write currents will become closer and closer, especially at 32 nanometer process and below. The read operation of the STT-MRAM memory cell may change the data stored therein because the read current is close to the write current. This phenomenon in which the STT-MRAM memory cell is disturbed by the read operation and the data bit error is caused with a certain probability is called read disturbance. The read disturbance problem is inevitable in future deep submicron STT-MRAM based memories.
[0007] Similar to the DRAM memory structure, a large number of STT-MRAM storage cells form a two-dimensional memory block Bank. The data line in the memory block is the basic read and write unit. Each memory block contains a row buffer Row Buffer. The source data row in the memory block is first read and loaded into the row buffer, and then serves the read and write requests from the outside world.
[0008] According to the computer storage hierarchy, the last level cache accesses the STT-MRAM memory in units of cache blocks. When a read or write request arrives, the memory controller locates the STT-MRAM memory block according to the read or write address, and then locates a specific row in the memory block, activates the row, reads the source data row, and loads it into the row buffer. The capacity of the memory row buffer is generally larger than the cache block, so the memory buffer contains not only the target cache block, but also other adjacent cache blocks. The memory controller then issues a column activation command to locate the target cache block data and complete the read or write. If the target data of the next read or write access is not in the current row buffer, that is, when a row buffer conflict occurs, the data row of the current row buffer needs to be written back to the memory block, and then the memory row containing the new data is activated to load the new data into the memory row buffer. When a row buffer conflict occurs in the STT-MRAM memory, due to the read disturbance problem, the data row in the row buffer must be written back to the memory block to overwrite the source data row and correct the erroneous storage unit that may be caused by the read disturbance. However, the write operation cost of STT-MRAM is high and consumes a lot of write energy, reaching 68% of the dynamic energy consumption of the memory. Therefore, alleviating the high energy consumption of write-back operations due to read disturbance is an urgent problem that needs to be solved. Summary of the invention
[0009] The purpose of the present invention is to overcome the deficiencies in the prior art and propose a write energy consumption optimization method for STT-MRAM read disturbance, aiming to alleviate the write energy consumption problem caused by the read disturbance of STT-MRAM memory.
[0010] The technical solution adopted by the present invention to solve the above problem is: a method for optimizing write energy consumption of STT-MRAM read disturbance, characterized in that it includes the following steps:
[0011] (1) dividing the row buffer of the STT-MRAM into a plurality of data blocks, each row buffer being equipped with a write update recorder and a comparison recorder; each write update recorder comprising a write update record bit, each write update record bit corresponding to the write update status of each data block in the row buffer in sequence; each comparison recorder comprising a comparison record bit, each comparison record bit corresponding to the comparison status of each data block in the row buffer in sequence;
[0012] (2) reading a source data row in the STT-MRAM memory block using a read current in a specific direction and loading it into a row buffer of the memory block;
[0013] (3) When loading the source data row into the row buffer of the memory block, the write update record bits of the row buffer are initialized to 0, and the comparison record bits of the row buffer are initialized to 1; the write update record bit value is 0, indicating that the corresponding data block in the row buffer has not been written and updated, otherwise, a write update has occurred; the comparison record bit value is 1, indicating that the corresponding data block in the row buffer needs to be compared with the source data block in the STT-MRAM memory block to find possible read disturbance errors; during data read and write access, once the column selector detects that a write update operation has occurred on a data block in the row buffer, the column selector sets the write update record bit corresponding to the data block to 1, and sets the comparison record bit of the data block to 0;
[0014] (4) When a row buffer conflict occurs, the comparator first reads the comparison recorder. If the bit value of each comparison record is 0, the current data blocks do not need data comparison; otherwise, the row buffer data block with the comparison record bit value of 1 must be compared with the source data in the STT-MRAM memory block; after completing the data comparison, the write update recorder is checked again. For the data block with the write update record bit value of 1, the corresponding data block in the row buffer needs to be written back to the STT-MRAM memory block; for the data block with the write back record bit value of 0, since there is no write update and the corresponding source data block is not free of read disturbance errors, it does not need to be written back.
[0015] In step (1) of the present invention, the row buffer of the STT-MRAM with a capacity of 512 Bytes is divided into 8 data blocks with a step size of 64 Bytes.
[0016] In step (1) of the present invention, each write update recorder contains 8 bits of write update record bits, and each comparison recorder contains 8 bits of comparison record bits.
[0017] In step (2) of the present invention, the specific direction is the write 0 direction.
[0018] The data reading of the write 0 direction current of the present invention only introduces a read disturbance error to the source data row in the STT-MRAM memory block, and with a certain probability, the bit disturbance with the original value of 1 is made 0, and the data row loaded into the memory block row buffer is not affected by the read disturbance.
[0019] The row buffer of each memory block of the present invention is equipped with a comparator, which connects the row buffer and the memory block, and can access the write update recorder and the comparison recorder. The comparator completes the data comparison operation between the row buffer data block with a record bit value of 1 in step (4) and the source data in the STT-MRAM memory block.
[0020] In the row buffer described in the present invention, the write update recorder and the comparison recorder are both connected to the comparator and the column selector, and the latter two can read and write the former two.
[0021] In step (4) of the present invention, when the row buffer data block with a record bit value of 1 is compared with the source data in the STT-MRAM memory block, a read current in the write 0 direction is used, and the comparator reads the data block A to be compared in the STT-MRAM memory block, and compares it with the data block a in the row buffer with a comparison record bit of 1 by bitwise XOR. Since the data in the row buffer is read and loaded by the current in the write 0 direction, it is only necessary to perform an XOR operation on the bit with a value of 1 in the data block a and the bit at the corresponding position in the data block A. All XOR results are subjected to an OR operation. As long as any XOR operation result value is 1, it indicates that there is a read disturbance error in the corresponding source data block in the STT-MRAM memory block where the current data block A is located. Therefore, the comparator sets the write update record bit corresponding to the data block a to 1 and the comparison record bit to 0 respectively.
[0022] Compared with the prior art, the present invention has the following advantages and effects: the present invention divides the data in the memory row buffer into blocks, and uses a write update recorder and a comparison recorder to track the status of each data block, and selectively writes back the data blocks according to the write update status of each data block and the triggering of read interference errors, instead of writing back the data in the entire memory row buffer as originally written, thereby reducing a large number of unnecessary data block write-back operations, optimizing write energy consumption, achieving the purpose of reducing write energy consumption, and improving storage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 A schematic diagram of an STT-MRAM memory cell.
[0024] Figure 2 4 is a structural diagram of a memory row buffer according to an embodiment of the present invention.
[0025] Figure 3 It is a schematic diagram of data comparison between a data block in a row buffer and source data in a memory block according to an embodiment of the present invention. DETAILED DESCRIPTION
[0026] The present invention will be further described in detail below with reference to the accompanying drawings and by way of examples. The following examples are intended to explain the present invention but the present invention is not limited to the following examples.
[0027] In this embodiment, a method for optimizing write energy consumption of STT-MRAM read disturbance includes the following steps:
[0028] (1) The 512-byte row buffer of the STT-MRAM is divided into 8 data blocks in steps of 64 bytes. Each row buffer is equipped with a write update recorder and a comparison recorder. Each write update recorder contains an 8-bit write update record bit, and each write update record bit corresponds to the write update status of each data block in the row buffer in sequence. Each comparison recorder contains an 8-bit comparison record bit, and each comparison record bit corresponds to the comparison status of each data block in the row buffer in sequence.
[0029] (2) The source data row in the STT-MRAM memory block is read using a read current in the write-0 direction and loaded into the row buffer of the memory block. The data reading using the write-0 direction current only introduces a read disturbance error to the source data row in the STT-MRAM memory block, and with a certain probability, the bit disturbance with the original value of 1 is changed to 0. The data row that has been loaded into the row buffer of the memory block is not affected by the read disturbance.
[0030] Reference Figure 2 , a structural diagram of a memory row buffer according to an embodiment of the present invention. The write update recorder WriteRecorder and the compare recorder Compare Recorder are both connected to the comparator Comparator and the column selector ColumnDecoder, the latter two can read and write the former two, the write update recorder contains an 8-bit write update record bit, and the compare recorder contains an 8-bit compare record bit.
[0031] (3) When loading the source data row into the row buffer of the memory block, the 8-bit write update record bits of the row buffer are initialized to 0, and the 8-bit comparison record bits of the row buffer are initialized to 1; the write update record bit value is 0, indicating that the corresponding data block in the row buffer has not been written and updated, otherwise, a write update has occurred; the comparison record bit value is 1, indicating that the corresponding data block in the row buffer needs to be compared with the source data block in the STT-MRAM memory block to find possible read disturbance errors. When accessing data read and write, once the column selector detects that a write update operation has occurred on a data block in the row buffer, the column selector sets the write update record bit corresponding to the data block to 1, and sets the comparison record bit of the data block to 0.
[0032] (4) When a row buffer conflict occurs, the comparator first reads the 8-bit comparison recorder. If the bit value of each comparison record is 0, the current data blocks do not need data comparison; otherwise, the row buffer data block with the comparison record bit value of 1 must be compared with the source data in the STT-MRAM memory block; after completing the data comparison, the 8-bit write update recorder is checked again. For the data block with the write update record bit value of 1, the corresponding data block in the row buffer needs to be written back to the STT-MRAM memory block; for the data block with the write update record bit value of 0, since there is no write update and the corresponding source data block is not free of read disturbance errors, it does not need to be written back.
[0033] Reference Figure 2 , a memory row buffer structure diagram of an embodiment of the present invention. The row buffer RowBuffer of each memory block is equipped with a comparator Comparator, which connects the row buffer and the memory Bank, and can access the write update recorder Write Recorder and the compare recorder Compare Recorder; the comparator completes the data comparison operation between the row buffer data block with the record bit value of 1 and the source data in the STT-MRAM memory block.
[0034] Reference Figure 3 , a data comparison diagram of a data block in a row buffer and a source data of a memory block according to an embodiment of the present invention, wherein the XOR circuit and the OR circuit are included, and the enable signal of the XOR circuit is controlled by the data bit of the row buffer of the memory block. When the enable signal value is 1, the XOR circuit works, and when the value is 0, the XOR circuit does not work, and the default output is 0. Therefore, the XOR circuit works only when the bit value in the data block of the row buffer is 1.
[0035] When comparing the row buffer data block with a record bit value of 1 with the source data in the STT-MRAM memory block, a read current in the write 0 direction is used, and the comparator reads the data block A to be compared in the STT-MRAM memory block, and compares it bit by bit with the data block a in the row buffer with a comparison record bit of 1; since the data in the row buffer is read and loaded by a current in the write 0 direction, it is only necessary to perform an XOR operation on the bit with a value of 1 in the data block a and the bit at the corresponding position in the data block A; all the XOR results are ORed, and as long as any XOR operation result value is 1, it means that there is a read disturbance error in the corresponding source data block in the STT-MRAM memory block where the current data block A is located, and therefore, the comparator sets the write update record bit corresponding to the data block a to 1 and the comparison record bit to 0 respectively.
[0036] In addition, it should be noted that the shapes and names of the parts and components of the specific embodiments described in this specification may be different, and the above content described in this specification is only an example of the structure of the present invention. All equivalent changes or simple changes made based on the structure, features and principles described in the patent concept of the present invention are included in the protection scope of the patent of the present invention. Technicians in the technical field of the present invention can make various modifications or supplements to the specific embodiments described or replace them in a similar manner, as long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.
Claims
1. A method for optimizing write energy consumption of STT-MRAM read disturbance, characterized in that: The steps include: (1) The row buffer of the STT-MRAM is divided into a plurality of data blocks, each row buffer is equipped with a write update recorder and a comparison recorder; each write update recorder includes a write update record bit, each write update record bit corresponds to the write update status of each data block in the row buffer in sequence; each comparison recorder includes a comparison record bit, each comparison record bit corresponds to the comparison status of each data block in the row buffer in sequence; (2) Using a read current in a specific direction to read the source data row in the STT-MRAM memory block and load it into the row buffer of the memory block; (3) When loading the source data row into the row buffer of the memory block, the write update record bits of the row buffer are initialized to 0, and the comparison record bits of the row buffer are initialized to 1; the write update record bit value is 0, indicating that the corresponding data block in the row buffer has not been written and updated, otherwise, a write update has occurred; the comparison record bit value is 1, indicating that the corresponding data block in the row buffer needs to be compared with the source data block in the STT-MRAM memory block to find possible read disturbance errors; during data read and write access, once the column selector detects that a write update operation has occurred on a data block in the row buffer, the column selector sets the write update record bit corresponding to the data block to 1, and sets the comparison record bit of the data block to 0; (4) When the row buffer conflicts, the comparator first reads the comparison recorder. If the value of each comparison record bit is 0, no data comparison is required for the current data blocks; Otherwise, the row buffer data block with the comparison record bit value of 1 must be compared with the source data in the STT-MRAM memory block; after completing the data comparison, check the write update recorder again. For the data block with the write update record bit value of 1, it is necessary to write the corresponding data block in the row buffer back to the STT-MRAM memory block; for the data block with the write update record bit value of 0, since there is no write update and the corresponding source data block is not free of read disturbance errors, it does not need to be written back.
2. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 1, characterized in that: In step (1), the row buffer of the STT-MRAM with a capacity of 512 bytes is divided into 8 data blocks with a step size of 64 bytes.
3. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 1, characterized in that: In step (1), each write update recorder contains 8 bits of write update record bits, and each comparison recorder contains 8 bits of comparison record bits.
4. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 1, characterized in that: In step (2), the specific direction is the write 0 direction.
5. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 4, characterized in that: The data reading with write 0 direction current only introduces read disturbance error to the source data row in the STT-MRAM memory block, and with a certain probability, the bit with the original value of 1 is disturbed to 0. The data row that has been loaded into the memory block row buffer is not affected by the read disturbance.
6. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 1, characterized in that: The row buffer of each memory block is equipped with a comparator, which connects the row buffer and the memory block. The comparator can access the write update recorder and the comparison recorder. The comparator completes the data comparison operation between the row buffer data block with the record bit value of 1 in step (4) and the source data in the STT-MRAM memory block.
7. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 6, characterized in that: In the row buffer, the write update recorder and the comparison recorder are both connected to the comparator and the column selector, and the latter two can read and write the former two.
8. The method for optimizing write energy consumption of STT-MRAM read disturbance according to claim 1, characterized in that: In step (4), when the row buffer data block with a record bit value of 1 is compared with the source data in the STT-MRAM memory block, a read current in the write 0 direction is used, and the comparator reads the data block A to be compared in the STT-MRAM memory block, and compares it with the data block a in the row buffer with a comparison record bit of 1 by bitwise XOR. Since the data in the row buffer is read and loaded by the current in the write 0 direction, it is only necessary to perform an XOR operation on the bit with a value of 1 in the data block a and the bit at the corresponding position in the data block A. All the XOR results are ORed, and as long as any XOR result value is 1, it means that there is a read disturbance error in the corresponding source data block in the STT-MRAM memory block where the current data block A is located. Therefore, the comparator sets the write update record bit corresponding to the data block a to 1 and the comparison record bit to 0 respectively.