Data writing method and system and related equipment

Abstract

The invention discloses a data writing method, a data writing system and related equipment. The data writing method comprises the following steps: receiving target test data from Ethernet; processing the target test data to obtain processed target test data; sending a data writing instruction to a direct memory access controller, so that the direct memory access controller writes the processed target test data into a memory according to the data writing instruction; and receiving an interrupt instruction sent by the direct memory access controller, and closing a data writing operation of the direct memory access controller according to the interrupt instruction. According to the technical scheme, the data writing efficiency and the reasonability of system resource utilization can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a data writing method, system and related equipment. Background Art

[0002] FPGA (Field-Programmable Gate Array) technology brings new ways to CPU (Central Processing Unit) design due to its programmable characteristics. Developers can use hardware description language to describe the CPU functional structure, such as instruction decoding, arithmetic logic unit, etc., and then use FPGA development tools to map it to chip logic resources to build a CPU prototype.

[0003] However, the existing technology has certain shortcomings. The speed of downloading data to FPGA through JTAG downloader is slow, which will slow down the development process in scenarios such as data distribution in big data processing centers and high-speed network communication protocol processing. When writing to the memory, the CPU needs to be called multiple times, which will occupy CPU computing resources. Due to its own bandwidth speed limitation, the writing efficiency is low. In scenarios such as real-time data processing of industrial automation control, high-frequency signal acquisition and processing systems, it is easy to cause data processing delays, system response lags and even instability, which limits the application and development of this technology in the field of high-performance electronic systems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a data writing method, comprising: Receive target test data from Ethernet; Processing the target test data to obtain processed target test data; Sending a data write instruction to a direct memory access controller, so that the direct memory access controller writes the processed target test data into a memory according to the data write instruction; An interrupt instruction sent by the direct memory access controller is received, and a data writing operation of the direct memory access controller is disabled according to the interrupt instruction.

[0006] In a feasible implementation, the method further includes: receiving a data transmission command sent by a universal asynchronous receiver and transmitter; starting the direct memory access controller according to the data transmission command, so that the direct memory access controller obtains the processed target test data from the memory, and transfers the obtained processed target test data to a temporary buffer; sending the processed target test data in the temporary buffer to an external device through the universal asynchronous receiver and transmitter, so as to check through the external device whether the processed target test data obtained from the memory is consistent with the target test data received from the Ethernet.

[0007] In a feasible implementation manner, before receiving the target test data from the Ethernet, the method further includes: performing initialization configuration and enabling operations on the hardware platform and network related operations; after completing the initialization configuration and the enabling operations, starting the application.

[0008] In a feasible implementation, the initialization configuration and enabling operations on the hardware platform and network related operations include: initializing the hardware platform; after completing the initialization operation, configuring the network interface; after completing the configuration of the network interface, initializing the protocol stack, and adding the configured network interface to the network interface list of the protocol stack, enabling interrupts and enabling the network interface.

[0009] In a feasible implementation manner, configuring the network interface after completing the initialization operation includes: setting a media access control address for the network interface after completing the initialization operation, and configuring an Internet Protocol address, a subnet mask, and a gateway.

[0010] In a feasible implementation, the method further includes: sending a network configuration parameter acquisition request to a dynamic host configuration protocol server; if the Internet Protocol address, subnet mask and gateway sent by the dynamic host configuration protocol server in response to the network configuration parameter acquisition request are received within a preset time, configuring the network interface according to the received Internet Protocol address, subnet mask and gateway; if no response from the dynamic host configuration protocol server is received within the preset time, configuring the network interface according to the static Internet Protocol address, static subnet mask and static gateway.

[0011] In a second aspect, the present application proposes a data writing system, comprising: The Ethernet module is used to receive target test data sent by the client and send the target test data to the processor; The processor is used to process the received target test data to obtain processed target test data, and the processor is also used to send a data write instruction to a direct memory access controller; The direct memory access controller is used to write the processed target test data into the memory according to the data write instruction sent by the processor. The direct memory access controller is also used to generate and send an interrupt instruction to the processor so that the processor closes the data write operation of the direct memory access controller according to the interrupt instruction.

[0012] In a third aspect, the present application proposes a data writing device, comprising: A receiving unit configured to receive target test data from Ethernet; a processing unit, configured to process the target test data to obtain processed target test data; a sending unit configured to send a data write instruction to a direct memory access controller, so that the direct memory access controller writes the processed target test data into a memory according to the data write instruction; The closing unit is configured to receive an interrupt instruction sent by the direct memory access controller and close the data writing operation of the direct memory access controller according to the interrupt instruction.

[0013] In a fourth aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of any one of the data writing methods of the first aspect when executing the computer program stored in the memory.

[0014] In a fifth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the data writing method of any one of the first aspects is implemented.

[0015] In summary, the data writing method proposed in the present application can quickly and effectively obtain external source data by receiving target test data from Ethernet, and can make it meet the subsequent storage and analysis requirements after processing; by sending write instructions to the direct memory access controller and using its efficient transmission capability to write the processed data to the memory, the processor burden is greatly reduced and the accurate storage of data is ensured; and receiving interrupt instructions and closing write operations accurately controls the data transmission process, avoids errors and waste of resources, and overall improves the efficiency and reliability of data acquisition, processing and storage, and optimizes system resource utilization and task coordination. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of an exemplary system used in an embodiment of the present application.

[0017] Figure 2 A flowchart of a data writing method provided in an embodiment of the present application.

[0018] Figure 3 An interactive schematic diagram of a data writing method provided in an embodiment of the present application.

[0019] Figure 4 A flowchart of a data writing method provided in an embodiment of the present application.

[0020] Figure 5 A schematic diagram of the structure of a data writing device provided in an embodiment of the present application.

[0021] Figure 6 A schematic diagram of the structure of an electronic device for writing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0023] Figure 1 A data writing system suitable for the embodiment of the present application is shown. Figure 1 As shown, the data writing system 100 may be a system based on FPGA, and may specifically include an Ethernet module 101 , a processor 102 , and a direct memory access controller 103 .

[0024] Among them, the Ethernet module 101 is the basic component for realizing Ethernet communication. This component adopts the AXI Ethernet mode and follows the AXI (Advanced extensible Interface) protocol during internal data transmission. In terms of external communication, it follows the Ethernet protocol and can convert data in the AXI protocol format into the Ethernet frame format and send it to the external Ethernet, or convert the received Ethernet data into the AXI protocol format for processing by the internal processor 102, thereby realizing data interaction between the internal system and the external Ethernet network.

[0025] The processor 102 may be a MicroBlaze, which is a soft-core processor. The soft-core means that it is not a physical chip, but a processor that can be implemented by programming in an FPGA. The processor 102 is used for system control and data processing; communication with peripherals and networks; data collection, transmission and distribution; processing real-time tasks, monitoring systems, etc.

[0026] The direct memory access controller 103 may be an AXI DMA (AXI Direct Memory Access), which is a direct memory access controller based on the AXI protocol. Based on this protocol, AXI DMA can communicate with other devices that also follow the AXI protocol (such as the processor 102, Figure 1 When the direct memory access controller 103 works with the processor 102, it is responsible for the handling and transmission of data. It can transfer data from one storage area to another, or transfer data from an external device to the memory, so that the processor 102 can focus more on data processing and calculation, improving the performance of the entire system. The processor 102 can communicate with the Ethernet module 101 and the direct memory access controller 103 respectively. In some embodiments, the processor 102 can communicate with the Ethernet module 101 and the direct memory access controller 103 respectively through the interconnect module 104. Among them, the interconnect module 104 can be an AXI Interconnect, which is an on-chip interconnect structure for connecting multiple AXI devices. For example, the processor 102 and the Ethernet module 101 (AXI Ethernet), the processor 102 and the direct memory access controller 103 (AXI DMA) are connected through the AXI Interconnect.

[0027] In some embodiments of the present application, the Ethernet module 101 can receive target test data from an external Ethernet network, and then send the received target test data to the processor 102 for processing. After the processor 102 processes the target test data, it obtains the processed target test data. Further, the processor 102 sends a data write instruction to the direct memory access controller 103, and the direct memory access controller 103 writes the processed target test data into the memory according to the data write instruction sent by the processor 102. The direct memory access controller 103 can also generate and send an interrupt instruction to the processor 102, and the processor 102 can shut down the data write operation of the direct memory access controller 103 according to the interrupt instruction.

[0028] It should be further explained that the memory in this solution can be the fourth generation double data rate synchronous dynamic random access memory (Double-Data-Rate Fourth-Generation Synchronous Dynamic Random-Access Memory, DDR4). DDR4 is a computer memory technology used to store programs and data running on a computer, enabling the processor to quickly read and write information, thereby supporting the normal operation of the computer system. Compared with previous generations of memory technology, DDR4 has improved in speed, capacity, and energy efficiency.

[0029] The data writing system 100 in the embodiment of the present application greatly improves data transmission efficiency and significantly increases transmission throughput by using a direct memory access controller 103 and without the need for frequent intervention of the processor 102; the processor 102 focuses on setting, starting and monitoring data transmission rather than moving data, effectively reducing the load on the processor 102 so that it can better process data and control logic; a modular design is adopted, and each component such as the Ethernet module 101, the processor 102, and the direct memory access controller 103 are independent of each other and connected by means of an interconnection module 104, and can be replaced or upgraded as needed, greatly enhancing the flexibility and scalability of the system; Ethernet data is quickly stored in the memory, and with its high-speed reading and writing characteristics, it fully supports big data processing and real-time applications, and meets the requirements of diverse application scenarios for data volume and real-time performance.

[0030] In some embodiments of the present application, the data writing system 100 may further include a memory interface generator 105 (Memory Interface Generator, MIG). The memory interface generator 105 is a tool mainly used to automatically generate an interface between a memory (such as DDR4, etc.) and other system components (such as the processor 102 and the direct memory access controller 103).

[0031] In some embodiments of the present application, the data writing system 100 may further include a universal asynchronous receiver-transmitter 106 (Universal Asynchronous Receiver-Transmitter, UART) and a temporary buffer 107. The universal asynchronous receiver-transmitter 106 may be an AXI UART, which is a module that combines UART functions with the AXI protocol. Due to the use of the AXI protocol, the AXI UART can follow the AXI protocol to communicate with other AXI-compatible devices in the system (such as the processor 102, etc.). The temporary buffer 107 may be an AXI4 Stream Data FIFO, which is a FIFO that combines the AXI4 Stream protocol. It is mainly used for data buffering between modules that follow the AXI4 Stream protocol.

[0032] In some embodiments, the universal asynchronous receiver and transmitter 106 may send a data transmission command to the processor 102, and then the processor 102 starts the direct memory access controller 103 according to the data transmission command, and the direct memory access controller 103 may obtain the processed target test data from the memory, and transmit the obtained processed target test data to the temporary buffer 107; finally, the universal asynchronous receiver and transmitter 106 sends the processed target test data in the temporary buffer to the external device, and the external device may check whether the processed target test data obtained from the memory is consistent with the target test data received from the Ethernet. If they are consistent, it means that the data writing of the direct memory access controller 103 is correct; otherwise, it means that the data writing is incorrect. Only when the data writing is correct can a series of tests be performed on the target test data.

[0033] This embodiment can intuitively verify the correctness of data writing by sending the target test data obtained from the memory and processed through a series of transmissions to the external device, and comparing it with the target test data initially received from the Ethernet. This direct comparison method is simple and effective, and can quickly locate errors that may occur during the data writing process. At the same time, the temporary buffer 107 is used to optimize data transmission. Since the data transmission rates between different components may be different, for example, the rate at which the direct memory access controller 103 obtains data from the memory and the rate at which the universal asynchronous receiver and transmitter 106 sends data to the external device may be inconsistent. The temporary buffer 107 can store a certain amount of data, so that the data transmission can be smoother, avoid data loss or transmission interruption, reduce the waiting time for data transmission, and improve the overall system performance.

[0034] In some embodiments, the direct memory access controller 103 may transfer the acquired processed target test data to the temporary buffer 107 by using a data transmission method of stream to memory mapping, and this process includes the conversion of data from a flow state to orderly storage in the temporary buffer 107. And the acquisition of data from the temporary buffer 107 may adopt a data transmission method of memory mapping to stream, and this method includes the conversion of data from orderly storage in the temporary buffer 107 to a flow state.

[0035] Figure 2 A flowchart of a data writing method according to an embodiment of the present application is shown. The data writing method can be executed by a processor, which can be Figure 1 The processor 102 shown in FIG. Figure 2 As shown, the data writing method includes: Step S210, receiving target test data from Ethernet; Step S220: Process the target test data to obtain processed target test data; Step S230, sending a data write instruction to the direct memory access controller, so that the direct memory access controller writes the processed target test data into the memory according to the data write instruction; Step S240: receiving an interruption instruction sent by the direct memory access controller, and shutting down the data writing operation of the direct memory access controller according to the interruption instruction.

[0036] These steps are described in detail below.

[0037] In step S210 , target test data is received from Ethernet.

[0038] Ethernet is a common and widely used computer local area network technology, which builds a network environment for data transmission. In this environment, multiple devices can be connected to each other and communicate. In this embodiment, the processor 102 can be connected to each other and communicate with the Ethernet module 101, so as to receive the target test data from the Ethernet through the Ethernet module 101. The processor 102 is the receiving end of the data.

[0039] The target test data is data sent by the sending end specifically for the purpose of testing. These data are encapsulated and transmitted according to the Ethernet protocol at the sending end, and flow in the network in the form of data packets. The processor 102 as the receiving end detects these data packets through its Ethernet interface, and performs unpacking operations according to the protocol to extract the target test data therein.

[0040] In some embodiments, the target test data may be an operating system startup file, which plays an extremely critical leading and driving role in the startup process of the computer system. It covers a series of indispensable instructions and data information such as initializing hardware facilities, loading the core kernel, and starting system basic services.

[0041] In step S220, the target test data is processed to obtain processed target test data.

[0042] Specifically, after the processor receives the target test data, it will further process the target test data to obtain the processed target test data. More specifically, the processor can perform group processing on the target test data, and group processing refers to dividing the received target test data into different groups according to certain rules. These rules can be based on a variety of factors, such as the type, source, purpose or size of the data. For example, grouping can be performed according to functional modules, such as grouping data related to hardware initialization into one group, data related to kernel loading into one group, and data related to system service startup into another group; or grouping can be performed according to the order of the files in the startup process, with one group executed first and one group executed later.

[0043] In other embodiments, in addition to packet processing, the target test data may also involve multiple processing methods. Data verification is an important part. By calculating the checksum or using a hash algorithm, it is verified whether the data is complete and has not been tampered with during transmission to ensure the accuracy and reliability of the data. Format conversion is also often performed, for example, converting data in a specific format transmitted over the network into a format that is common within the system or easier to operate subsequently, so as to work better with other components.

[0044] In step S230, a data write instruction is sent to the direct memory access controller, so that the direct memory access controller writes the processed target test data into the memory according to the data write instruction.

[0045] After receiving and processing the target test data in the previous steps, the system needs to store the processed data properly. At this time, the processor can send a data write instruction to the direct memory access controller to tell it to start working. The direct memory access controller here can be Figure 1 The direct memory access controller 103 in.

[0046] A direct memory access controller is a hardware device that can efficiently transfer data to memory without excessive processor intervention. This instruction is like a task order to the direct memory access controller, which will move the processed target test data to the specified memory location based on the parameters in the instruction, such as the starting address and length of the data.

[0047] This step utilizes the efficient data transmission capability of the direct memory access controller, reducing the burden on the processor during data transmission, freeing the processor to handle other tasks. At the same time, through precise instruction control, it can ensure that data is accurately stored in the appropriate location in the memory, providing a basic guarantee for subsequent data reading or other operations.

[0048] In step S240, an interruption instruction sent by the direct memory access controller is received, and the data writing operation of the direct memory access controller is disabled according to the interruption instruction.

[0049] The processor receives the interrupt instruction sent by the direct memory access controller and responds to it, which is the last step of the whole data writing process. After the direct memory access controller completes the task of writing the processed target test data into the memory, it will actively send an interrupt instruction to the processor.

[0050] The purpose of this interrupt instruction is to notify the processor that the data write operation has been successfully completed. After receiving the interrupt instruction, the processor closes the data write operation of the direct memory access controller according to the instruction content, which helps to accurately control the data transmission process and avoid unnecessary repeated data writing or data errors or confusion caused by failure to close the write channel in time. At the same time, through this interrupt mechanism, the processor can release resources from the data writing task in time so that they can be allocated to other tasks that need to be processed, such as subsequent reading and analysis of stored data or preparation for new data reception, thereby ensuring the efficient and orderly operation of the entire system.

[0051] The technical solution of the embodiment of the present application can quickly and effectively obtain external source data by receiving target test data from Ethernet, and make it meet the subsequent storage and analysis requirements after processing; by sending write instructions to the direct memory access controller and using its efficient transmission capability to write the processed data into the memory, the processor burden is greatly reduced and the accurate storage of data is ensured; and receiving interrupt instructions and closing write operations accurately controls the data transmission process, avoids errors and waste of resources, and overall improves the efficiency and reliability of data acquisition, processing and storage, and optimizes system resource utilization and task coordination.

[0052] See also Figure 3 , Figure 3 The figure shows an interactive schematic diagram of a data writing method provided in an embodiment of the present application. The data writing method may specifically include steps S1-S4, which are described in detail as follows: Step S1: The processor sets a direct memory access controller to write data.

[0053] Specifically, the processor sends a data write instruction to the direct memory access controller, and the direct memory access controller writes the data, while the processor can be released to perform other operations.

[0054] Step S2: Direct memory access controller writes data.

[0055] After receiving the data write instruction from the processor, the direct memory access controller writes the data into the memory.

[0056] Step S3: After completing data writing, the direct memory access controller sends an interrupt instruction to the processor.

[0057] Step S4: After receiving the interrupt instruction, the processor ends the data writing operation of the direct memory access controller.

[0058] In some embodiments of the present application, a data write instruction optimization engine can be constructed. Before sending a data write instruction to a direct memory access controller, the engine will pre-process the target test data for in-depth analysis, for example, by identifying hidden patterns, associations, and potential important information distribution in the data through a data mining algorithm. According to these analysis results, the data is divided into different logical blocks, and a customized write instruction sequence is generated for each logical block. Taking the target test data as an operating system startup file as an example to illustrate this embodiment, first, the operating system startup file data features, such as code segments, data segment distribution features, etc., can be extracted; then the internal associations are mined, such as the order association of the key module calls of the system; then logical blocks are formed according to the features and associations, such as the core startup logic block and the driver loading logic block; then each logic block is defined and marked, and the function is indicated; finally, in combination with the storage structure, a write instruction sequence is generated for each logic block, giving priority to the core startup logic block being written to the high-speed storage area and setting a high priority to ensure that the system can start efficiently and quickly.

[0059] In some embodiments of the present application, in order to achieve the best write effect and avoid possible performance bottlenecks or errors in advance, a write performance prediction model based on machine learning is introduced. The model will continue to learn data write performance (such as write speed, success rate, memory utilization, etc.) under different types of data, different instruction sequences, and different system environments. Before sending a write instruction each time, this model is used to predict the performance of the upcoming write operation, and the instruction is fine-tuned or the transmission strategy is adjusted according to the prediction results. If the predicted write speed is low, it may be necessary to optimize the instruction sequence, such as merging some instructions that can be executed in parallel to reduce redundant operations of the instruction. If the predicted success rate is low, it may be necessary to increase the data verification instruction or adjust the number of retries for data writing. If the predicted memory utilization is high and may affect other system operations, it may be necessary to adjust the memory allocation strategy for data writing, such as using segmented writing or caching part of the data to an external storage device before gradually writing it to the memory.

[0060] In some embodiments of the present application, at the direct memory access controller end, when a data write instruction arrives, it can be pre-parsed first, key information can be extracted and cached. Then, according to the current working state of the controller (such as the number of ongoing write tasks, the busyness of the memory area, etc.), the instructions in the cache are intelligently scheduled. If there is an idle memory write channel and there is no dependency between data blocks, multiple data write instructions can be processed in parallel to improve data writing efficiency; if the memory resources are tight or the data is logically associated and needs to be written sequentially, the instructions are processed in sequence according to priority and order.

[0061] In some embodiments of the present application, for the transmission path of the data write instruction, a single fixed channel may no longer be used, but a redundant and intelligently switched instruction transmission network may be established. This network includes multiple physical links and virtual channels. During the transmission process, key indicators such as the load, delay, and error rate of each channel are monitored in real time. Based on these indicators, a dynamic routing algorithm is used to dynamically select the optimal transmission path combination for the data write instruction to ensure that the instruction can reach the direct memory access controller quickly, stably, and accurately.

[0062] In some embodiments of the present application, Figure 4 As shown, in order to accurately test the target test data, it is further necessary to determine whether the data written into the direct memory access controller is correct. In this embodiment, it can specifically include steps S410 to S430, which are described in detail as follows: Step S410: receiving a data transmission command sent by a universal asynchronous receiver / transmitter.

[0063] In this embodiment, in order to determine whether the data written by the direct memory access controller is correct or not, it is necessary to first obtain the data in the memory. Based on this need to obtain data, the universal asynchronous receiver and transmitter will first generate and send a data transmission command to the processor. The processor receives the data transmission command sent by the universal asynchronous receiver and transmitter, thereby starting the subsequent data operation process.

[0064] Step S420: according to the data transfer command, start the direct memory access controller, so that the direct memory access controller obtains the processed target test data from the memory, and transfers the obtained processed target test data to the temporary buffer.

[0065] After receiving the data transfer command, the processor will start the direct memory access controller according to the command. The direct memory access controller plays an important role. It can bypass the processor and interact directly with the memory, and efficiently find the previously processed target test data from the memory. After finding the data, it will move the acquired processed target test data to a temporary buffer for temporary storage according to the set mechanism. Simply put, the direct memory access controller is like a precise "porter" who knows clearly which "warehouse" of the memory to go to to pick up the goods (target test data), and then accurately transport them to the temporary "transfer station" (temporary buffer).

[0066] Using a direct memory access controller can reduce the burden on the processor and make the data transmission process more efficient and faster. Placing data in a temporary buffer first is to speed up the direct memory access controller to read data from the memory, so as to prepare for the subsequent convenient sending of data to external devices, so that data can flow in an orderly manner between different links, avoiding the rate mismatch and data loss that may occur when directly transmitting from the memory to the external device, and ensuring the stability and continuity of data transmission.

[0067] Step S430: Send the processed target test data in the temporary buffer to the external device through the universal asynchronous receiver and transmitter, so as to check through the external device whether the processed target test data obtained from the memory is consistent with the target test data received from the Ethernet.

[0068] The universal asynchronous receiver and transmitter comes into play again. It uses the temporary buffer as the data source, takes out the processed target test data from it, and sends this data to the external device. After the external device receives this data, it can compare it with the target test data previously received from Ethernet. For example, the external device may be a computer or test terminal dedicated to data verification. It uses specific software or algorithms to compare the key parameters and contents of the two copies of data to determine whether there is any deviation in the entire data processing and storage process.

[0069] By comparing the processed data obtained from the memory with the data originally received from the Ethernet, it is possible to promptly discover whether there are errors or losses in the data transmission, processing and storage links, thereby ensuring that the data processing flow of the entire system is reliable and effective, providing an accurate data basis for subsequent testing work based on these data, and ensuring the normal realization of system functions.

[0070] In some embodiments of the present application, before the processor receives target test data from Ethernet, it is also necessary to perform initialization configuration and enablement operations on the hardware platform and network related operations; after completing the initialization configuration and the enablement operations, the application is started.

[0071] In this embodiment, initializing the configuration and enabling the hardware platform is an extremely critical basic step. First, the hardware platform and network related operations must be initialized and enabled, the hardware parameters must be set, the network parameters of the network equipment must be configured, and the network functions must be enabled, so as to build a basic framework for the system operation. Without this step, subsequent applications will be difficult to run normally. Then, after completing the above operations, the application can be started, its executable file can be loaded into the memory, and the processor will execute according to the instructions, using the configured hardware and network conditions to realize functions and serve users.

[0072] In some embodiments, the initialization configuration of the hardware may include configuring the physical layer, for example, by operating through ProgramSi5324 and ProgramSfpPhy functions. In addition, the initialization of the platform may be completed by executing the init_platform function.

[0073] In some embodiments, after completing the initialization operation on the hardware platform, the network interface is further configured; then, the protocol stack is initialized, and the configured network interface is added to the network interface list of the protocol stack, and interrupts are enabled and the network interface is enabled.

[0074] Among them, the initialization of the protocol stack is the initialization of the Light Weight Internet Protocol (lwIP). lwIP is a small open source TCP / IP protocol stack, mainly used in embedded systems and resource-constrained environments. Compared with the complete TCP / IP protocol stack, lwIP occupies less memory space and has lower hardware resource requirements, but it can still provide basic network communication functions. lwIP initialization is an important starting step for the entire network-related configuration. By calling the lwip_init function, its purpose is to put the lwIP stack into a working state. The lwIP stack plays a key role in network communication, similar to a "steward" who manages network data transmission and reception and other operations. Initializing it is like arranging work responsibilities for this "steward" and preparing various tools so that it can coordinate network interfaces in an orderly manner and prepare for the subsequent reception and transmission of network data, laying the foundation for the realization of network communication functions.

[0075] After completing the initialization of the lwIP stack, the next step is to add a network interface. Use the xemac_add function to add the network interface to the lwIP network interface list. Adding a network interface to the lwIP network interface list can achieve centralized management of multiple network interfaces. When network data needs to be sent or received, lwIP can select the appropriate network interface to process the data based on the information in the network interface list. At the same time, the addition of network interfaces also helps to achieve layered processing of network protocols and supports network function expansion and flexible configuration.

[0076] Next, after adding the network interface, you can enable interrupts and enable the network interface. Enabling interrupts is conditional. If you are not in SDT (Software Debug Tool) mode, you must turn on the interrupt function. The interrupt mechanism allows the system to respond to various network-related events in a timely manner, such as data arrival, transmission completion, etc., to ensure the timeliness and smoothness of network communication. Marking the network interface as "started" clearly informs the system that the network interface is ready and can participate in the interaction of network data normally. At this point, the configuration and preparation work related to the entire network interface are completed, and the system can use it for stable network communication activities.

[0077] In some embodiments, after the initialization operation is completed, the network interface is configured, which may include setting the media access control address, and configuring the Internet Protocol address, subnet mask, and gateway.

[0078] The media access control address (MAC address) is a unique identifier for network devices. It is mainly used to identify devices, facilitate network management and security monitoring, and ensure the accuracy of data transmission. The Internet Protocol address (IP address) is a digital label assigned to a network device, which is used to identify and locate the device in a network environment such as the Internet or a local area network. The subnet mask is a 32-bit number that is used to divide the network part and the host part of the IP address. It is used in conjunction with the IP address to help the device determine the network it is in and the boundaries with other networks. The gateway is a device or node that connects different networks. It is like a "gate" between different networks. When a device in a local network needs to communicate with a device in another network (such as the Internet or another local area network), the data is first sent to the gateway. The gateway knows how to forward data to other networks. It selects the appropriate path to send the data based on the destination IP address and the routing information it stores.

[0079] In some embodiments, a specific method for configuring an Internet Protocol address, a subnet mask, and a gateway may be sending a network configuration parameter acquisition request to a dynamic host configuration protocol server; if the Internet Protocol address, subnet mask, and gateway sent by the dynamic host configuration protocol server in response to the network configuration parameter acquisition request are received within a preset time, the network interface is configured according to the received Internet Protocol address, subnet mask, and gateway; if no response is received from the dynamic host configuration protocol server within the preset time, the network interface is configured according to the static Internet Protocol address, static subnet mask, and static gateway.

[0080] In this embodiment, first, the Dynamic Host Configuration Protocol (DHCP) server plays an important role in the network environment. It can automatically allocate network configuration parameters to devices in the network. When the device is started and connected to the network, it will send a request to the DHCP server to obtain network configuration parameters. This request is like a "help signal" sent by the device to the server, informing the server that it needs the corresponding network configuration information, such as key parameters such as the Internet Protocol address, subnet mask, and gateway, so that it can communicate and interact smoothly in the network.

[0081] If the IP address, subnet mask, gateway and other parameters sent by the DHCP server in response to its request are successfully received within the preset time, then the network interface will be configured based on the received information. The network interface is like a "channel port" connecting the device to the external network. By accurately configuring this "channel port" according to the received parameters, the device can clearly identify its "identity" in the network (IP address), the scope of the network (subnet mask), and how to communicate with other networks (gateway). In this way, the device can participate in network activities with the correct network configuration, such as sending and receiving data, accessing other network resources, etc., to ensure the normal operation of network communication functions.

[0082] However, sometimes there may be some situations that result in no response from the DHCP server within the preset time, such as server failure or unstable network connection. At this time, the network interface will be configured according to the pre-set static Internet Protocol address, static subnet mask and static gateway. These static parameters are backup solutions that are manually configured in advance and stored in the device. Although they are not as convenient as dynamically obtaining them through the DHCP server, they can ensure that the device's network interface has the corresponding configuration available when encountering the above special circumstances, so that it will not be unable to connect to the Internet due to the inability to obtain dynamic configuration, so that the device can still try to communicate in the network based on these static configurations and maintain certain network functions.

[0083] In some embodiments of the present application, after the above series of operations, i.e., initializing the hardware platform, configuring the network interface, initializing the protocol stack, adding the configured network interface to the network interface list of the protocol stack, enabling interrupts, and enabling the network interface, the main loop is entered, in which the processor checks and processes the fast timer (tcp_fasttmr) and the slow timer (tcp_slowtmr). The processor can also call the xemacif_input function to process the received network data packets. Call the transfer_data function for data transmission (the specific implementation depends on the application).

[0084] tcp_fasttmr is used for fast response related tasks, such as the associated fast retransmission mechanism; tcp_slowtmr is responsible for relatively slow tasks, such as the keep-alive mechanism. When checking, you need to check the timer status and the associated data and events to determine whether the triggering conditions are met. In terms of processing, if tcp_fasttmr is triggered, fast response operations such as retransmitting segments are performed; if tcp_slowtmr is triggered, corresponding processing is performed according to the corresponding tasks such as keep-alive detection, so as to ensure the smooth operation of TCP connections.

[0085] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0086] In a second aspect, the present application also proposes a data writing device, such as Figure 5 As shown, the data writing device includes: a receiving unit 501, a processing unit 502, a sending unit 503 and a closing unit 504.

[0087] Among them, the receiving unit 501 is configured to receive target test data from Ethernet; the processing unit 502 is configured to process the target test data to obtain processed target test data; the sending unit 503 is configured to send a data write instruction to the direct memory access controller, so that the direct memory access controller writes the processed target test data into the memory according to the data write instruction; the closing unit 504 is configured to receive an interrupt instruction sent by the direct memory access controller, and close the data write operation of the direct memory access controller according to the interrupt instruction.

[0088] In some embodiments of the present application, the receiving unit 501 is also configured to receive a data transmission command sent by a universal asynchronous receiver and transmitter; according to the data transmission command, start the direct memory access controller so that the direct memory access controller obtains the processed target test data from the memory and transfers the obtained processed target test data to a temporary buffer; send the processed target test data in the temporary buffer to an external device through the universal asynchronous receiver and transmitter, so as to check through the external device whether the processed target test data obtained from the memory is consistent with the target test data received from the Ethernet.

[0089] In some embodiments of the present application, before the receiving unit 501 receives the target test data from the Ethernet, the device also includes: an initialization unit configured to perform initialization configuration and enabling operations on the hardware platform and network related operations; a startup unit configured to start the application after completing the initialization configuration and the enabling operations.

[0090] In some embodiments of the present application, the initialization unit is also configured to perform initialization operations on the hardware platform; after completing the initialization operation, configure the network interface; after completing the configuration of the network interface, initialize the protocol stack, and add the configured network interface to the network interface list of the protocol stack, enable interrupts, and enable the network interface.

[0091] In some embodiments of the present application, the initialization unit is further configured to set a media access control address for the network interface, and configure an Internet Protocol address, a subnet mask, and a gateway after completing the initialization operation.

[0092] In some embodiments of the present application, the initialization unit is further configured to send a network configuration parameter acquisition request to a dynamic host configuration protocol server; if the Internet Protocol address, subnet mask and gateway sent by the dynamic host configuration protocol server in response to the network configuration parameter acquisition request are received within a preset time, the network interface is configured according to the received Internet Protocol address, the subnet mask and the gateway; if no response from the dynamic host configuration protocol server is received within the preset time, the network interface is configured according to the static Internet Protocol address, the static subnet mask and the static gateway.

[0093] like Figure 6 As shown, an embodiment of the present application also provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor, and when the processor 620 executes the computer program 611, the steps of any of the above-mentioned data writing methods are implemented.

[0094] Since the electronic device introduced in this embodiment is a device used to implement a data writing device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation method of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0095] During the specific implementation process, when the computer program 611 is executed by the processor 620, any implementation method in the corresponding embodiment can be implemented.

[0096] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0098] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0099] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0101] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the data writing process in the corresponding embodiment.

[0102] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0103] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0104] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0105] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0107] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0108] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that: include: Receive target test data from Ethernet; Processing the target test data to obtain processed target test data; Sending a data write instruction to a direct memory access controller, so that the direct memory access controller writes the processed target test data into a memory according to the data write instruction; An interrupt instruction sent by the direct memory access controller is received, and a data writing operation of the direct memory access controller is disabled according to the interrupt instruction.

2. The method according to claim 1, characterized in that The method further comprises: receiving a data transmission command sent by a universal asynchronous receiver / transmitter; According to the data transmission command, starting the direct memory access controller so that the direct memory access controller obtains the processed target test data from the memory and transmits the obtained processed target test data to a temporary buffer; The processed target test data in the temporary buffer is sent to an external device through the universal asynchronous receiver and transmitter, so as to check through the external device whether the processed target test data obtained from the memory is consistent with the target test data received from the Ethernet.

3. The method according to claim 1, characterized in that Before receiving the target test data from the Ethernet, the method further includes: Initialize configuration and enable operations on hardware platforms and network related; After completing the initialization configuration and the enabling operation, start the application.

4. The method according to claim 3, characterized in that The initialization configuration and activation operations for the hardware platform and network related operations include: Performing initialization operation on the hardware platform; After completing the initialization operation, configuring the network interface; After completing the configuration of the network interface, the protocol stack is initialized, and the configured network interface is added to the network interface list of the protocol stack, and interrupts are enabled and the network interface is enabled.

5. The method according to claim 4, characterized in that After completing the initialization operation, configuring the network interface includes: After completing the initialization operation, the media access control address is set for the network interface, and the Internet Protocol address, subnet mask and gateway are configured.

6. The method according to claim 5, characterized in that The method further comprises: Send a network configuration parameter acquisition request to a dynamic host configuration protocol server; If the Internet Protocol address, subnet mask and gateway sent by the dynamic host configuration protocol server in response to the network configuration parameter acquisition request are received within a preset time, the network interface is configured according to the received Internet Protocol address, the subnet mask and the gateway; If no response is received from the dynamic host configuration protocol server within the preset time, the network interface is configured according to the static Internet Protocol address, the static subnet mask and the static gateway.

7. A data writing system, characterized in that: include: The Ethernet module is used to receive target test data sent by the client and send the target test data to the processor; The processor is used to process the received target test data to obtain processed target test data, and the processor is also used to send a data write instruction to a direct memory access controller; The direct memory access controller is used to write the processed target test data into the memory according to the data write instruction sent by the processor. The direct memory access controller is also used to generate and send an interrupt instruction to the processor so that the processor closes the data write operation of the direct memory access controller according to the interrupt instruction.

8. A data writing device, characterized in that: include: A receiving unit configured to receive target test data from Ethernet; a processing unit, configured to process the target test data to obtain processed target test data; a sending unit configured to send a data write instruction to a direct memory access controller, so that the direct memory access controller writes the processed target test data into a memory according to the data write instruction; The closing unit is configured to receive an interrupt instruction sent by the direct memory access controller and close the data writing operation of the direct memory access controller according to the interrupt instruction.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the data writing method according to any one of claims 1 to 6 when executing a computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data writing method according to any one of claims 1 to 6 are implemented.

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