Data storage method, processor, computing device, storage medium and program product

Abstract

The invention discloses a data storage method, a processor, computing equipment, a storage medium and a program product. The method is applied to a processor, and comprises the following steps: in response to a received data persistence request, storing to-be-persisted data corresponding to the data persistence request into a cache, and storing a base address of the to-be-persisted data into a source register; based on the information of the source register, a data persistence instruction is constructed, and the data persistence instruction is a predefined extension instruction; and sending a data persistence instruction to the persistent memory, the data persistence instruction being used for storing the to-be-persistent data to the persistent memory. The technical problem that the reliability of data storage of the processor of the RISC architecture is reduced is solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to a data storage method, a processor, a computing device, a storage medium, and a program product. Background Art

[0002] The Reduced Instruction Set Computer (RISC) architecture is an open source instruction set structure with the advantages of being completely open source, free of charge, and customizable. Therefore, it is very popular in modern computer architecture.

[0003] In the related art, a RISC architecture processor usually refreshes data to the last level cache (LLC) or the main memory of the computer. However, the above memory is volatile memory, which causes the data stored in the above memory to be lost when the power is cut off. The RISC architecture processor cannot use the lost data, resulting in reduced reliability of data storage in the RISC architecture processor.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] Embodiments of the present application provide a data storage method, a processor, a computing device, a storage medium, and a program product to at least solve the technical problem of reduced reliability of data storage in a RISC architecture processor.

[0006] According to one aspect of an embodiment of the present application, a data storage method is provided, which is applied to a processor, and the method may include: in response to receiving a data persistence request, storing the data to be persisted corresponding to the data persistence request in a cache, and storing the base address of the data to be persisted in a source register; based on information of the source register, constructing a data persistence instruction, wherein the data persistence instruction is a predefined extended instruction; sending the data persistence instruction to a persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory.

[0007] According to another aspect of an embodiment of the present application, a processor is further provided, which is used to run a program, and the program executes the above-mentioned data storage method when it is run.

[0008] According to another aspect of an embodiment of the present application, a computing device is also provided, which may include: a persistent memory; a processor, connected to the persistent memory, and used to store the data to be persisted corresponding to the data persistence request in a cache in response to receiving a data persistence request, and store the base address of the data to be persisted in a source register; based on information in the source register, construct a data persistence instruction, wherein the data persistence instruction is a predefined extended instruction; the persistent memory is also used to store the data to be persisted based on the persistence instruction.

[0009] According to another aspect of an embodiment of the present application, a computer-readable storage medium is further provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is running, the device where the storage medium is located is controlled to execute the methods in each embodiment of the present application.

[0010] According to another aspect of the embodiments of the present application, a computer program product is also provided, including computer program instructions, and the computer program instructions implement the methods in various embodiments of the present application when executed by a processor.

[0011] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0012] According to another aspect of the embodiments of the present application, a computer program instruction is also provided, and when the computer program instruction is executed by a processor, the method in each embodiment of the present application is implemented.

[0013] In an embodiment of the present application, in response to receiving a data persistence request, the data to be persisted corresponding to the data persistence request is stored in a cache, and the base address of the data to be persisted is stored in a source register; based on the information of the source register, a data persistence instruction is constructed, wherein the data persistence instruction is a predefined extended instruction; and the data persistence instruction is sent to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory. That is to say, in an embodiment of the present application, by constructing a new data persistence instruction, the data to be persisted in the cache is refreshed to the persistent memory, avoiding the problem of data loss in the event of a power outage, thereby providing a guarantee for data persistence, achieving the technical effect of improving the reliability of data storage in a RISC architecture processor, and solving the technical problem of low reliability of data storage in a RISC architecture processor.

[0014] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A hardware structure block diagram of a RISC-V system for implementing a data storage method is shown;

[0017] Figure 2 Shown using the above Figure 1 A schematic diagram of a system-on-chip of the RISC-V architecture is shown;

[0018] Figure 3 is a flow chart of a data storage method according to the above embodiment of the present application;

[0019] Figure 4 is a schematic diagram of a CXL controller located in an ADR domain according to an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of a CXL controller not located in an ADR domain according to an embodiment of the present application;

[0021] Figure 6 is a schematic diagram of a data stream transmission situation in which a CXL controller is not in an ADR domain according to an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of another data stream transmission situation in which the CXL controller is not in the ADR domain according to an embodiment of the present application;

[0023] Figure 8 is a schematic diagram of data stream transmission of a CXL controller in an ADR domain according to an embodiment of the present application;

[0024] Fig. 9 is a schematic diagram of data stream transmission of another CXL controller in an ADR domain according to an embodiment of the present application;

[0025] Fig.10 is a schematic diagram of a data storage device according to an embodiment of the present application;

[0026] Fig.11 It is a schematic diagram of a system on a chip of a RISC-V architecture shown in the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0030] The open source instruction set structure may be an open source instruction set structure based on a reduced instruction set principle, and may be used to provide a flexible, scalable and customizable processor architecture to meet various application requirements.

[0031] Persistent Memory (PMem) is a new storage technology that has high-speed access capabilities and persistent data storage.

[0032] Asynchronous DRAM Refresh domain (ADR Domain for short) may refer to an asynchronous DRAM refresh mechanism, which may be used to ensure that data entering the ADR Domain can be successfully written into the non-volatile memory even when power is off.

[0033] According to an embodiment of the present application, a data storage method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0034] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 FIG. 1 shows a hardware structure block diagram of a RISC-V system for implementing a data storage method. Figure 1 As shown, the RISC-V system 100 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0035] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0036] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0037] The operating system layer 104 is located above the hardware and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0038] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0039] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0040] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0041] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0042] In an optional embodiment, Figure 2 Shown using the above Figure 1 The schematic diagram of the RISC-V architecture system on chip is shown in FIG. Figure 2 As shown, the system on chip (System On Chip, SOC for short) includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, Universal Asynchronous Receiver / Transmitter (UART for short) 212, General Purpose Input / Output (GPIO for short) 214, Serial Peripheral Interface Bus (SPI for short) 216, etc.

[0043] Under the above operating environment, this application provides Figure 3 The data storage method shown. Figure 3 is a flow chart of a data storage method according to the above embodiment of the present application. Figure 3 As shown, the method may include the following steps:

[0044] Step S302 , in response to receiving a data persistence request, storing the data to be persisted corresponding to the data persistence request in a cache, and storing the base address of the data to be persisted in a source register.

[0045] In the technical solution provided in the above step S302 of the present application, the above persistence request can be used to indicate that the persistent data is persistently stored in the persistent memory. The above source register can be a register (Register, referred to as rs1) register. The above base address can be a virtual address specified by the source register, can be the target location where the data to be persisted is stored, can be the location of the data to be persisted in the persistent memory, for example, can be the starting address of the persistent data in the persistent memory. It should be noted that this is only an example, and there is no specific restriction on the representation content of the base address. The above persistent data can be data that needs to be stored for a long time or stored in a persistent storage medium, for example, it can be data stored in a hard disk, a database, etc., and can include user information, order information, log records, configuration information, etc. It should be noted that this is only an example, and there is no specific restriction on the type of persistent data.

[0046] Optionally, in order to prevent data from being lost due to power outages or other failures, the data in the memory needs to be permanently saved to non-volatile storage (e.g., persistent memory). In this case, a data persistence request is generated. In response to the data persistence request, since writing data directly to non-volatile storage may be slow, in order to implement the persistence process, the data to be persisted can be first stored in the cache, and then, through the persistence instruction, the data to be persisted can be refreshed to the persistent memory, thereby achieving the purpose of fast storage of the data to be persisted.

[0047] Step S304: construct a data persistence instruction based on the information of the source register.

[0048] In the technical solution provided in the above step S304 of the present application, the above source register information may include address information of the source register, memory size information, etc. It should be noted that this is only an example, and the type of source register information is not specifically limited. The above data persistence instruction may be a predefined extended instruction (for example, cbo.cleanp instruction), which may be used to store the data to be persisted in the persistent memory. The instruction may be applicable to situations where data needs to be refreshed to the persistent memory.

[0049] Optionally, when executing the cbo.cleanp instruction, it is necessary to specify the target location of the data to be persisted, that is, the location in the persistent memory, which usually involves a base address, that is, the starting address of the data to be persisted in the persistent memory. Therefore, in order to ensure that the cbo.cleanp instruction can correctly identify and operate the data location, the base address can be stored in the source register (rs1), and further based on the information of the source register, the purpose of the data persistence instruction can be constructed.

[0050] For example, a data persistence instruction can be constructed based on the source register information, such as the source register mnemonic (Base), so as to ensure that the data to be persisted is correctly and safely refreshed from the cache to the persistent memory. It should be noted that this is only an example, and there is no specific limitation on the method of constructing the data persistence instruction.

[0051] Step S306: Send a data persistence instruction to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory.

[0052] In the technical solution provided in the above step S306 of the present application, the above persistent memory can be a new storage technology between the memory and the traditional storage (such as SSD, HDD).

[0053] Optionally, in response to receiving a data persistence request from an application, an operating system, or an external event (e.g., a power-off warning) and the like, which requires persisting the data to be persisted to PMem, the data to be persisted may be stored in a cache. Furthermore, in order to identify the storage location of the data to be persisted in PMem, the base address of the data to be persisted may be stored in a source register (e.g., rs1). Based on the stored base address information, a data persistence instruction may be constructed, which may be a predefined extended instruction, such as a cbo.cleanp instruction, the structure and behavior of which have been defined, and may ensure that the data to be persisted is correctly refreshed to PMem. After the data persistence instruction is constructed, the data persistence instruction may be sent to the PMem controller to perform the persistence operation of the data to be persisted, that is, the data to be persisted in the specified base address may be refreshed to PMem.

[0054] For example, suppose there is an application that needs to store the user's personal information persistently. When the user clicks the Save button, a data persistence request can be triggered. In response to the data persistence request, the user's personal information can be stored in the cache, and the base address can be stored in the source register. According to the information in the source register, a data persistence instruction can be constructed, and the data persistence instruction can be sent to the persistent memory. Based on the data persistence data, the user's personal information can be stored in the persistent memory.

[0055] Through the above steps S302 to S308 of the present application, in response to receiving a data persistence request, the data to be persisted corresponding to the data persistence request is stored in the cache, and the base address of the data to be persisted is stored in the source register; based on the information of the source register, a data persistence instruction is constructed, wherein the data persistence instruction is a predefined extended instruction; and the data persistence instruction is sent to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory. In other words, based on the information of the source register, a data persistence instruction is constructed, and by defining a new data persistence instruction, a method of refreshing the persistent data in the cache to the persistent memory is clarified, thereby providing a guarantee for data persistence, and then achieving the technical effect of avoiding data loss in the case of power failure, and solving the technical problem that data will be lost in the case of power failure.

[0056] The above method of this embodiment is further introduced below.

[0057] As an optional implementation, in step S306, the processor is connected to the persistent memory through a high-speed interconnect technology bus, wherein sending a data persistence instruction to the persistent memory includes: sending a data persistence instruction to a high-speed interconnect technology controller corresponding to the high-speed interconnect technology bus, wherein the data persistence instruction is used to control the high-speed interconnect technology controller to send a first write request to the persistent memory controller, and the first write request is used to control the persistent memory controller to write the data to be persisted into the persistent memory; receiving a persistence response sent by the high-speed interconnect technology controller, wherein the timing of sending the persistence response is determined based on whether the high-speed interconnect technology controller is in an asynchronous refresh mechanism domain.

[0058] In this embodiment, sending the data persistence instruction to the persistent memory may include the following steps: the data persistence instruction may be sent to the high-speed interconnect technology (Compute Express Link, referred to as CXL) controller corresponding to the high-speed interconnect technology bus through a router. When the CXL controller receives the data persistence instruction, it may send a first write request to the persistent memory controller (ie, PMem controller), and the first write request may be used to control the persistent memory controller to write the persistent data to the persistent memory. After writing the persistent data to the persistent memory, the CXL controller may issue a persistence response to the persistent memory controller (ie, PMem controller).

[0059] Optionally, the timing of sending the persistence response can be determined according to the location of the CXL controller. The location of the CXL controller can include the following two situations: the CXL controller is in the asynchronous refresh mechanism domain, that is, the ADR domain includes the CXL controller, the PMem controller and the PMem; the CXL controller is not in the asynchronous refresh mechanism domain, that is, the ADR domain only includes the PMem controller and the PMem. It should be noted that the above two situations are only examples and are not specifically limited here.

[0060] For example, the processor and the persistent memory are connected through a high-speed interconnect technology bus. The CXL bus can be used to complete high-speed data transmission. The processor can interact with the high-speed interconnect technology controller (e.g., CXL controller) through the bus to send data persistence instructions. When the processor needs to permanently save data to the persistent memory, it can send a data persistence instruction (e.g., cbo.cleanp instruction) to the high-speed interconnect technology controller. The instruction can be used to trigger the high-speed interconnect technology controller to send a write request (i.e., the first write request mentioned above) to the persistent memory controller. The write request can contain information about the data to be persisted. The persistent memory controller can write the persistent data to the persistent memory according to the write request to ensure that the persistent data can still be restored after power failure, thereby ensuring the persistence and consistency of the data. After completing the write operation, the persistent memory controller can send a persistence response to the processor through the high-speed interconnect technology controller, indicating that the persistent data has been successfully persisted.

[0061] As an optional implementation, when the high-speed interconnect technology controller is in an asynchronous refresh mechanism domain, the persistence response is sent by the high-speed interconnect technology controller at the same time as sending the first write request; when the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, the persistence response is sent by the high-speed interconnect technology controller after receiving the first response sent by the persistent memory controller.

[0062] In this embodiment, whether the CXL controller belongs to the ADR domain determines whether the CXL controller has the ability to continue to send the first write request (i.e., write request) to the PMem controller after power failure. That is, if the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain, the persistence response is sent by the high-speed interconnect technology controller at the same time as the first write request is sent. If the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, after power failure, the persistence response is sent by the high-speed interconnect technology controller after receiving the first response (i.e., ack response) sent by the persistent memory controller. The above-mentioned first response can be a response issued by the persistent memory controller in response to the first write request.

[0063] Optionally, the timing at which the CXL controller returns a persistence response is different depending on whether the CXL controller is in the ADR domain. The core side can use the persistence response (persist_resp) to determine whether the data persistence instruction has been executed. If the CXL controller is not in the ADR domain, the CXL controller can send a persistence response to the core after the PMem controller returns an acknowledgment (ack) response. If the CXL controller is in the ADR domain, it does not need to wait for the ack response from the PMem controller. After receiving the persistence request from the coherent network on chip (CNOC), it can immediately send a persistence response (persist_resp) to the core. This method can shorten the persistence request time on the core side. Among them, the above-mentioned coherent network on chip can be used to complete the transmission of instructions and / or data between the core and the CXL controller. For example, CNOC can be used to transmit the cbo.cleanp instruction issued by the core to the CXL controller.

[0064] For example, if the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain, the core sends a cbo.cleanp instruction to the CNOC. After receiving the cbo.cleanp instruction, the CNOC will give a response to the core, and then the CNOC sends a data persistence instruction (persist_req) to the CXL controller. The CXL controller responds to the data persistence instruction to send a first write request to the PMem controller. After receiving the first write request, the PMem controller returns a first response (which can be an ACK response) to the CXL controller. Since the PMem controller has the ability to continue writing to the PMem after power failure, the CXL controller can return a persistence response (which can be persist_resp) to the core, that is, the high-speed interconnect technology controller sends it after receiving the first response sent by the persistent memory controller to indicate that the current persistence request is completed. Among them, the above-mentioned first response can be issued by the PMem controller, and can be a response instruction used to characterize the completion of persistence.

[0065] For another example, if the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, the core can send a cbo.cleanp instruction to CNOC. After receiving the request, CNOC will give the core a response, and then CNOC sends a persistence request to the CXL controller. The CXL controller sends the first write request to the PMem controller. Since the CXL controller is in the ADR domain and has the ability to continue sending requests to the PMem controller after power failure, the CXL controller can immediately give the core a persistence response. That is, the CXL controller sends a persistence response while sending the first write request to the PMem controller. After receiving the request, the PMem controller can return an ACK response to the CXL controller.

[0066] As an optional implementation, sending a data persistence instruction to a high-speed interconnect technology controller corresponding to the high-speed interconnect technology bus includes: determining the current state of the data to be persisted in the cache; and sending a data persistence instruction to the high-speed interconnect technology controller when the current state is clean data.

[0067] In this embodiment, the timing of sending the data persistence instruction can be determined based on the current state of the data to be persisted in the cache. The current state may include clean data and dirty data. The clean data may be data in the cache that is consistent with the data in the main memory, and may be unmodified data. The dirty data may be modified data in the cache.

[0068] Optionally, when the data in the cache is modified, it changes from a clean state to a dirty state. In the process of sending a data persistence instruction to the high-speed interconnect technology controller corresponding to the high-speed interconnect technology bus, the current state of the data to be persisted in the cache can be determined. If the data to be persisted has not been modified, it can be determined that the current state of the data to be persisted is a clean state, that is, it can be determined that the data to be persisted is clean data, and then the data persistence instruction can be sent to the high-speed interconnect technology controller.

[0069] As an optional implementation, when the current state is dirty data, the method also includes: sending a data persistence instruction and a second write request to the high-speed interconnect technology controller; upon receiving a second response returned by the high-speed interconnect technology controller based on the second write request, sending the data to be persisted to the high-speed interconnect technology controller, wherein the second write request is sent by the high-speed interconnect technology controller to the persistent memory controller after receiving the data to be persisted.

[0070] In this embodiment, if the current state is used to characterize that the data to be persisted is dirty data, a data persistence instruction and a write request (i.e., the second write request mentioned above) can be sent to the high-speed interconnect technology controller; upon receiving a second response returned by the high-speed interconnect technology controller based on the write request, the data to be persisted is sent to the high-speed interconnect technology controller, wherein the second write request mentioned above is sent by the high-speed interconnect technology controller to the persistent memory controller after receiving the data to be persisted, so as to write the data to be persisted into the persistent memory.

[0071] For example, if the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, the core sends a cbo.cleanp instruction to the CNOC. After receiving the cbo.cleanp instruction, the CNOC will give a response to the core, and then the core sends a write instruction (e.g., write data) to the CNOC. In response to the instruction, the CNOC sends a data persistence instruction (e.g., write&persist_req) to the CXL controller. The CXL controller returns a response to the data persistence instruction. The CNOC sends a second write request (e.g., write data) to the CXL controller. Using the second write request, the CXL controller sends the data to be persisted to the PMem controller. At the same time, the CXL controller returns a response to the core. The PMem controller returns a response (ack) to the CXL controller. In response to the response, the CXL controller sends a second response (persist_resp) to the core. When the core receives the second response returned by the high-speed interconnect technology controller based on the second write request, the data to be persisted can be sent to the high-speed interconnect technology controller.

[0072] For another example, if the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain, the core sends a cbo.cleanp instruction to the CNOC. After receiving the cbo.cleanp instruction, the CNOC will give the core a response, and then the core sends a write instruction (e.g., write data) to the CNOC. In response to the instruction, the CNOC sends a data persistence instruction (e.g., write&persist_req) to the CXL controller. The CXL controller returns a response to the CNOC in response to the data persistence instruction. The CNOC sends a second write request (e.g., write data) to the CXL controller, and using the second write request, the CXL controller sends the data to be persisted to the PMem controller. At the same time, the CXL controller returns a response (resp_cbo) to the CNOC and sends a second response (persist_resp) to the core. The PMem controller returns a response (ack) to the CXL controller. When the core receives the second response returned by the high-speed interconnect technology controller based on the second write request, the data to be persisted can be sent to the high-speed interconnect technology controller.

[0073] As an optional implementation, the length of the persistence instruction is a first preset length, and the persistence instruction includes a source register field, a function field, and an operation category field, wherein the field value of the source register field is used to represent the information of the source register, the field value of the function field is used to represent the change management instruction and the persistence function, and the field value of the operation category field is used to represent the operation corresponding to the memory.

[0074] In this embodiment, the first preset length may be a preset length, for example, 32 bits or 64 bits. It should be noted that, in the embodiment of the present application, the first preset length is 32 bits as an example for explanation. The above-mentioned persistence instruction may include a source register field, a function field, and an operation category field. The above-mentioned source register field may be a field corresponding to a mnemonic, and the field value of the source register field may be used to characterize the information of the source register, for example, it may be used to determine the corresponding register rs1, or it may be the base address corresponding to rs1. The above-mentioned function field may include a field corresponding to a cache block operation (CBO for short), and a field corresponding to an instruction extension (cbo.cleanp), which may be used to determine the additional information provided by the persistence instruction, and the field value of the function field may be used to characterize the change management instruction and the persistence function, for example, the field corresponding to the above-mentioned persistence function may be fields 31-20 in the persistence instruction. The field value of the above-mentioned operation category (for example, MISC-MEM) field may be used to characterize the operation corresponding to the memory. It should be noted that the size and position of the above-mentioned fields are only for example, and may be selected according to the actual situation, and no specific restrictions are made here.

[0075] Optionally, by defining new persistence instructions to explicitly refresh the data in the kernel cache to the persistent memory, data persistence is guaranteed, thereby achieving the technical effect of avoiding data loss in the event of a power outage, and solving the technical problem of data loss in the event of a power outage.

[0076] For example, a persistence instruction may be an instruction with a length of 32 fields, wherein fields 31 to 20 of the persistence instruction may be function fields, and the corresponding binary code may be 100000000001; fields 19 to 15 may be source register fields, and the corresponding binary code may be rs1; fields 14 to 12 may be another function field, and the corresponding binary code may be empty; fields 16 to 7 may be fields corresponding to the extension code, and fields 6 to 0 may be operation category fields, and the corresponding binary code may be 0001111. It should be noted that this is only an example, and the format and content of the persistence instruction are not specifically limited.

[0077] In this embodiment, a new instruction (eg, cbo.cleanp instruction) is defined to clarify the location of data refresh. Compared with the original cache management instruction (Cache Management Operatin, CMO for short), this method can clarify the location of data refresh to ensure the durability of required data.

[0078] As an optional implementation, the method may also include at least one of the following: after sending a persistence instruction to the persistent memory, sending a first masking instruction to the persistent memory, wherein the first masking instruction is used to control the persistent memory to execute a read request or a write request after the first masking instruction after the read request or the write request before the first masking instruction is completed; after sending the persistence instruction to the persistent memory, sending a second masking instruction to the persistent memory, and sending a new persistence instruction to the persistent memory again, wherein the second masking instruction is used to control the persistent memory to execute the new persistence instruction after the persistence instruction is completed.

[0079] In this embodiment, the first shielding instruction may be a memory sorting instruction (FENCE R*, *W instruction) which may be used to control the persistent memory to execute the read request or write request after the first shielding instruction after the read request or write request before the first shielding instruction is completed. The second shielding instruction (which may be a FENCE W, W instruction) may be used to control the persistent memory to execute a new persistent instruction after the persistent instruction is completed.

[0080] Optionally, this embodiment controls and ensures the order and consistency of data operations in the persistent memory by utilizing the first mask instruction and the second mask instruction.

[0081] Optionally, after sending the persistence instruction to the persistent memory, a first shielding instruction FENCER*,*W can be sent. The first shielding instruction can ensure that in the persistent memory, only after any read request or write request before the first shielding instruction has been executed, the persistent memory will continue to process the read request or write request after the first shielding instruction, thereby maintaining the order of data operations and preventing the data from being affected by the operations of subsequent instructions during the refresh process, thereby achieving the purpose of maintaining data persistence and consistency.

[0082] Optionally, after the cbo.cleanp instruction is executed, a second shielding instruction (e.g., FENCE W,W) can be sent, and a new persistence instruction can be prepared to be sent again. By using the FENCE W,W instruction, the persistent memory can be controlled to execute subsequent write instructions only after the cbo.cleanp instruction is completed, thereby ensuring that the completion status of the data refresh operation will not be disturbed by the new write operation until the new persistence instruction is sent and processed. The use of the FENCE W,W instruction can ensure the order of data refresh operations to the persistent memory, thereby avoiding data confusion and inconsistency in a multi-threaded environment.

[0083] Optionally, in a multi-threaded or concurrent environment, the order and persistence of data operations become extremely important. For example, when a thread performs data modifications and wants these modifications to be immediately persisted in non-volatile memory, while other threads may be performing read or write operations, by using the cbo.cleanp instruction and the corresponding FENCE instruction, the sequential update and persistent storage of data can be ensured to prevent data competition or loss.

[0084] For example, by sending a FENCE instruction (e.g., FENCER*,*W) after executing the cbo.cleanp instruction, the execution of the FENCE instruction is applicable to both read and write operations. To ensure the update of persistent memory, cbo.cleanp can be sorted with fencew,w, so that the order of data operations in persistent memory can be effectively controlled to ensure data persistence and consistency.

[0085] In this embodiment, the cbo.cleanp instruction is applicable to situations where data needs to be refreshed to persistent memory, that is, the cbo.cleanp instruction can be used to refresh data to the persistent memory at the corresponding location. However, in order to ensure the persistence order of the memory, the data can also be refreshed to the persistent memory and the order of such refresh can be guaranteed by using the cbo.cleanp and fence instructions.

[0086] As an optional implementation, the method may also include: determining the current privileged mode of the processor and obtaining the value stored in the status register corresponding to the persistence instruction; based on the current privileged mode and the value stored in the status register, determining whether there is an exception in the persistence instruction; wherein the persistence instruction is sent when there is no exception in the persistence instruction.

[0087] In this embodiment, during the execution of the cbo.cleanp instruction, the processor may be abnormal due to the status register, and the current privilege mode of the processor can be used to determine whether the cbo.cleanp instruction will cause an illegal instruction exception or a virtual instruction exception. Therefore, the current privilege mode of the processor can be determined, and the value stored in the status register corresponding to the persistence instruction can be obtained. Based on the current privilege mode and the value stored in the status register, it can be determined whether the persistence instruction is abnormal. Among them, the above-mentioned current characteristic mode can be the current privilege level (priv_mode), which can be used to characterize the privilege level of the processor, for example, it can include level m, level s and level h, which can be used to distinguish the operating status and permission requirements of different processors. The value stored in the status register corresponding to the above-mentioned persistence instruction can be an enable signal of the status register, which can be used to determine the state of the status register.

[0088] In this embodiment, three status registers may be included, and these three status registers may be respectively for processors of each privilege level in the RISCV architecture, and each privilege level corresponds to a status register (Control and Status Register, referred to as CSR) to control whether the cbo.cleanp instruction can be executed in a lower privilege mode. Among them, the status register may be a register defined in the RISCV architecture (e.g., menvcfg, senvcfg, henncfg), wherein m, s, and h represent the current privilege mode respectively. m may represent machine mode. s may represent supervisor mode. h may represent user mode, which may also be referred to as a hypervisor. Further, this embodiment may determine whether the cbo.cleanp instruction can be executed based on the current privilege level of the processor and the enable signal in the status register (e.g., menvcfg.CBCPE, senvcfg.CBCPE, henncfg.CBCPE).

[0089] As an optional implementation, the current privileged mode includes one of the following: a machine mode, a supervisor mode, and a user mode in descending order, and the status register includes: a high-level register, a mid-level register, and a low-level register, wherein, based on the current privileged mode and the values ​​stored in the status register, determining whether there is an exception in the persistent instruction includes: when the values ​​stored in the current privileged mode and the status register meet the first condition, determining that there is an illegal instruction exception in the persistent instruction; when the values ​​stored in the current privileged mode and the status register meet the second condition, determining that there is a virtual instruction exception in the persistent instruction; when the values ​​stored in the current privileged mode and the status register do not meet the second condition, determining that there is a virtual instruction exception in the persistent instruction; When the first condition is met and the current privileged mode and the value stored in the status register do not meet the second condition, it is determined that there is no exception in the persistence instruction; wherein the first condition includes one of the following: the current privileged mode is not machine mode, and the value stored in the high-level register is not a preset value; the current privileged mode is user mode, and the value stored in the mid-level register is not a preset value; the second condition includes one of the following: the current privileged mode is supervisor mode, and the value stored in the low-level register is not a preset value; the current privileged mode is user mode, and the value stored in the low-level register is not a preset value; the current privileged mode is user mode, and the value stored in the mid-level register is not a preset value.

[0090] In this embodiment, the current privileged mode may include: machine mode, supervisor mode and user mode in descending order, and the status register corresponds to the current privileged mode one by one, and may include: high-level registers, medium-level registers and low-level registers. The above preset value may be 1 or 0. It should be noted that this is only for example, and the size of the preset value is not specifically limited.

[0091] Optionally, the following pseudo code can be used to determine whether a persistence instruction is abnormal:

[0092] / / Illegal instruction exception

[0093] if((priv_mode!=M&&!menvcfg.CBCPE)||(priv_mode==U&&!senvcfg.CBCPE)){

[0094] Raises an illegal instruction exception

[0095] }

[0096] / / Virtual instruction exception

[0097] elseif((priv_mode==Vs&&!henvcfg.CBCPE)||

[0098] (priv_mode==Vu&&!(henvcfg.CBCPE&&senvcfg.CBCPE))){

[0099] Throws a virtual instruction exception

[0100] }

[0101] / / Execute instructions

[0102] else{

[0103] Execute cbo.cleanp

[0104] }

[0105] Optionally, the above pseudocode is further explained: First, check the current privilege mode and configuration register status: determine whether the current privilege mode (priv_mode) is the supervisor mode (M), and whether the CBCPE bit of the status register (menvcfg) is 1 (that is, the preset value); if the current privilege mode is not the machine mode, and menvcfg.CBCPE is 0, or if the current mode is the user mode (U), and the CBCPE bit of the status register (senvcfg) is 0, it can be determined that the persistence instruction has an illegal instruction exception. Further, the configuration status in the virtualization mode can be checked. If it is currently in the virtual supervisor mode (Vs), check whether the CBCPE bit of the status register (henvcfg) is 0. Or, if it is currently in the virtual user mode (Vu), check whether henncfg.CBCPE and senvcfg.CBCPE are both 0. If so, it can be determined that the persistence instruction has a virtual instruction exception.

[0106] Further, if neither of the above two situations is true, that is, the CBCPE bit in the current mode is set to allow execution of the cbo.cleanp instruction, then the cbo.cleanp instruction can be executed normally, which means that if the corresponding bit in the status register is set, the cbo.cleanp instruction will be executed, otherwise, it can be determined that there is an exception with the persistence instruction.

[0107] For example, before executing the cbo.cleanp instruction, the persistence instruction can be judged to determine whether there is an abnormality in the persistence instruction. If the current operating mode is not the highest privilege management mode, and the CBCPE bit configured in the management environment is not turned on, or if it is running in user mode and the CBCPE bit configured in the security environment is not turned on, it can be determined that there is an abnormality in the persistence instruction. Secondly, when the system is running in virtual security or virtual user mode, if the henncfg.CBCPE bit is not set, or the henncfg.CBCPE and senvcfg.CBCPE bits are not set at the same time in virtual user mode, it can be determined that there is an abnormality in the persistence instruction. Only when these checks are passed, that is, the CBCPE bit is correctly set in the current mode, the cbo.cleanp instruction will be executed normally and the data persistence refresh operation will be completed.

[0108] Optionally, the first condition and the second condition may be set in advance. The first condition may include: the current privileged mode is not a machine mode, and the value stored in the high-level register is not a preset value, or the current privileged mode is a user mode, and the value stored in the mid-level register is not a preset value. The second condition may include: the current privileged mode is a supervisor mode, and the value stored in the low-level register is not a preset value; or the current privileged mode is a user mode, and the value stored in the low-level register is not a preset value; the current privileged mode is a user mode, and the value stored in the mid-level register is not a preset value. Further, the current privileged mode and the value stored in the status register are judged based on the first condition and / or the second condition to determine the abnormal situation of the above-mentioned persistence instruction.

[0109] As an optional implementation, the persistent instruction converts the base address stored in the source register into a physical address by the persistent memory based on the current privileged mode and conversion mechanism of the processor, wherein, when the attribute corresponding to the physical address is that access is not allowed, it is determined that a page fault exception exists in the persistent instruction; when conversion of the base address is not allowed, it is determined that an access error exception exists in the persistent instruction.

[0110] In this embodiment, the persistence instruction is similar to the storage instruction, and the cbo.cleanp instruction is an explicit memory access instruction, which requires the calculation of an effective address. The effective address may be a physical address, which may be converted according to the current privilege mode and conversion mechanism. For example, if virtualization extension is implemented, the above physical address may be obtained through two-level conversion; if virtualization extension is not implemented, the above physical address may be obtained through one-level conversion.

[0111] Optionally, in this embodiment, the following constraints can be imposed on the persistence instruction: (1) the effective address is a cacheable attribute; (2) if access to the cache block is not allowed, that is, if the attribute corresponding to the physical address is not allowed to be accessed, it is determined that the persistence instruction has a page fault (e.g., pagefault or guest-pagefault) exception; (3) if conversion of the base address is not allowed, it can be determined that the persistence instruction has an access fault exception.

[0112] For example, the address in the cbo.cleanp instruction is a virtual address (that is, a base address), which needs to be converted into a physical address. During the conversion process, the address attributes are also checked. If the address attributes do not match, an exception will be reported.

[0113] In this embodiment, even if the given base address is non-aligned, it can be treated as aligned, so no address non-alignment exception will be generated.

[0114] As can be seen from the above, in this embodiment, executing the cbo.cleanp instruction may cause a processor exception due to the status register, address translation and protection mechanism.

[0115] As an optional implementation, step S302, in response to a data persistence request received during the processor executing a preset loop, the preset loop includes one of the following: a load-reservation loop, a storage conditional loop; the method also includes: after generating a persistence instruction, continuing to execute the preset loop.

[0116] In this embodiment, if a data persistence request is received during the execution of a preset loop by the processor, the preset loop can be continued to be executed after the persistence instruction is generated. That is, the cbo.cleanp instruction will neither change the properties of the load-reserved / store-conditional loop (LR / SC loop for short), nor interrupt the LR / SC loop, nor modify the event guarantee provided by the LR / SC loop.

[0117] As an optional implementation, the method may also include: when the data type of the persistence instruction is a preset type and the selection attribute of the base address is a first value, determining a first logical function corresponding to the execution data matching trigger; when the storage attribute of the base address is a second value, determining a second logical function corresponding to the execution address matching trigger.

[0118] In this embodiment, the trigger may be a trigger module, which may include at least one of the following: a data match trigger and an address match trigger. The trigger may be a tool for monitoring memory access and data flow during debugging.

[0119] Optionally, unless otherwise defined by the debug architecture specification, the behavior of the trigger with respect to the persist instruction is unspecified. If cbo.cleanp is implemented, the following additional trigger behaviors similar to cbo.cleanp may also be implemented: (1) Implementing an address match trigger should be optional; (2) Type 6 data match triggers should not be supported, so that when the data type of the persist instruction is a preset type and the select attribute of the base address is a first value (i.e., tdata1.type=6 and mcontrol6.select=1), it is determined that the first logical function corresponding to the data match trigger is executed. Memory accesses may be considered as storage, so that only when the storage attribute of the base address is a second value (i.e., mcontrol6.store=1), it is determined that the second logical function corresponding to the address match trigger is executed, and the second logical function may be a match address trigger.

[0120] Optionally, when executing a persistence instruction, if the data type of the persistence instruction is consistent with a preset type, and the selection attribute of the base address is set to a first value, the processor can execute the first logical function corresponding to the data match trigger. Among them, the preset type can be the data type of the instruction operand or the data type that the instruction is expected to process, and the first value can be a configuration value that allows the data match trigger to monitor, for example, it can be 1. The first logical function can be to monitor the read and write operations of the specified data when the data match trigger is activated, and / or possible breakpoint settings, which can be used to understand how the instruction affects specific data during debugging. It should be noted that the above is only for example, and there is no specific limitation on the size of the first value and the type of the first logical function.

[0121] Optionally, if the storage attribute of the base address is set to a second value, the processor may execute a second logical function corresponding to the address matching trigger. The above storage attribute may be used to determine the cacheability or protection level of the base address. The above second value may be used to determine a specific storage attribute that the address matching trigger is allowed to monitor, for example, it may be 0 or 1. The second logical function may be to monitor all read and write operations accessing a specific address range when the address matching trigger is activated, which may be used to determine the memory layout or detect access anomalies to a specific address. It should be noted that the above is for illustrative purposes only, and there is no specific limitation on the size of the second value or the type of the second logical function.

[0122] Optionally, in debug mode, triggers should be optional, meaning that developers can choose whether to enable the corresponding triggers as needed. For example, when tdata1.type=6 and mcontrol6.select=1, it indicates that this part of the data match trigger is not supported, probably because it is incompatible with the characteristics or purpose of the cbo.cleanp instruction. For the address match trigger, the address match trigger will only match the cbo.cleanp instruction when mcontrol6.store=1.

[0123] In this embodiment, in response to receiving a data persistence request, the data to be persisted corresponding to the data persistence request is stored in a cache, and the base address of the data to be persisted is stored in a source register; based on the information of the source register, a data persistence instruction is constructed, wherein the data persistence instruction is a predefined extended instruction; the data persistence instruction is sent to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory, thereby achieving a technical effect of avoiding data loss in the event of a power outage, and solving the technical problem of data loss in the event of a power outage.

[0124] Currently, hard disks and flash memory are at the bottom of the storage hierarchy. They can provide high storage density at a low cost, and because hard disks and flash memory are non-volatile, they can retain data when the power is off. However, hard disks or flash memory are addressed by sectors or blocks, and the access latency is very high. Static Random Access Memory (SRAM) and dynamic random access memory, because they need to be addressed by bytes, have lower read and write latency and higher throughput, are usually used to build the processor's cache hierarchy and main memory, but they are volatile devices, and all data will be lost after a power outage or system crash.

[0125] In recent years, the surge in high-performance big data applications requires storage systems to have high capacity, low access latency, and scalability. The emergence of persistent memory has introduced a new layer between DRAM and hard disks, eliminating the performance gap between the two. Because it is memory, data can be directly run or updated in real time without reloading. And because persistent memory is non-volatile, data can be directly persisted without the overhead of writing back from the storage medium to DRAM. Since PMem can achieve byte addressing, it greatly improves read and write efficiency.

[0126] In the related technologies, the main areas of persistent memory application include in-memory databases, currently popular in-memory databases (for example, Redis in-memory databases) and related variants. The cost and volatility of traditional DRAM make it impossible to store data in the cache in persistent memory in scenarios where large amounts of data need to be processed and data persistence is strict.

[0127] Alternatively, as an open source instruction set structure, RISCV has gradually entered the high-performance field with its development in recent years. However, in terms of persistent memory, RISCV has not yet been supported by standards or instruction extensions.

[0128] Since there is no solution for supporting persistent memory under the RISCv architecture, there is a technical problem that the reliability of data storage in the RISC architecture processor is reduced. Therefore, in this embodiment, a method for extending new instructions to support persistent memory function under the RISCv architecture is proposed. The method may include a structure that supports a persistent solution under the RISCv architecture, an implementation process based on the PMem function, and a solution for RISCv to support the persistent memory function in combination with the functional requirements of the database.

[0129] Optionally, from the perspective of refreshing data to the last level cache or the main memory of the computer, RISCV already has a CMO instruction extension to refresh the data in the kernel cache to the LLC or memory, but the above method does not provide clear instructions for persistent memory. In scenarios where data persistence is required, if only the original CMO instruction is used, the data to be persisted will be stored in volatile memory. In the event of a power outage, the data to be persisted will be completely lost, resulting in a technical problem of reduced reliability of data storage in RISC architecture processors. Therefore, in this embodiment, a new instruction is defined to clarify the process of refreshing the cache data in the kernel to the persistent memory, thereby providing a guarantee for data persistence.

[0130] In this embodiment, a new instruction (cbo.cleanp) is defined to clarify the location of the data to be persisted refresh. Compared with the original CMO instruction, the location of the data to be persisted refresh can be clarified to ensure the persistence of the data to be persisted, thereby making up for the shortcomings of the RISCV system in the memory database scenario that requires non-volatile memory, achieving the technical effect of avoiding data loss in the event of a power outage, and solving the technical problem of data loss in the event of a power outage.

[0131] The above method of this embodiment is further introduced below.

[0132] In this embodiment, two feasible implementation solutions are provided according to whether the CXL controller has the ability to continue writing to the PMem controller after power failure.

[0133] Figure 4 is a schematic diagram of a CXL controller located in an ADR domain according to an embodiment of the present application, according to Figure 4 It can be seen that the CXL controller does not have the ability to write to the PMem controller after power failure, that is, the ADR domain 41 only includes the PMem controller 405 and PMem406. In this case, after power failure, the PMem controller can continue to write the content in the WPQ (WritePending Queue) in the controller to the PMem. The PMem controller will retain the data after power failure to achieve data persistence. It should be clear that in this process, the CXL controller does not control this ADR domain. The CXL controller will send the data to the PMem controller, and then the PMem controller will write it to the PMem.

[0134] like Figure 4As shown, the core 401 can send a cbo.cleanp instruction to the router 402. In response to the cbo.cleanp instruction, the router 402 sends persist_resp to the LLC 403. The LLC 403 feeds back resp to the core 401 through the router 402, and sends the cbo.cleanp instruction to the CXL controller 404. The CXL controller 404 and the PMem controller 405 exchange information to achieve the purpose of controlling the PMem 406 through the PMem controller 405.

[0135] Optionally, the PMem controller can cache the data sent from the CXL controller into the WPQ, and write the data into the PMem memory particles under certain conditions. The PMem controller can be used to receive data sent from the upstream, convert the received data into a downstream communication protocol and send it to the downstream.

[0136] Figure 5 is a schematic diagram of a CXL controller not located in an ADR domain according to an embodiment of the present application, according to Figure 5 It can be seen that the CXL controller can continue to write to the PMem controller after power failure, that is, the ADR domain 51 may include the CXL controller 504 , the PMem controller 505 , and the PMem 506 .

[0137] like Figure 5 As shown, the core 501 can send a cbo.cleanp instruction to the router 502. In response to the cbo.cleanp instruction, the router 502 sends persist_resp to the LLC 503. The LLC 503 feeds back resp to the core 501 through the router 502, and sends the cbo.cleanp instruction to the CXL controller 504. The CXL controller 504 first feeds back persist to the router, and then exchanges information with the PMem controller 505, so as to achieve the purpose of controlling the PMem 506 through the PMem controller 505.

[0138] Figure 6 FIG. 1 is a schematic diagram of a data flow transmission situation in which a CXL controller is not in an ADR domain according to an embodiment of the present application. Figure 6As shown, if the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, and the data to be persisted is clean data, core 601 can send a cbo.cleanp instruction to CNOC 602. After receiving the request, CNOC 602 will give core 601 a response (resp for short), and then CNOC 602 sends a persistence request to CXL controller 603, and CXL controller 603 sends a write request to PMem controller 604. Since CXL controller 603 is in the ADR domain and has the ability to continue to send requests to PMem controller 604 after power failure, CXL controller 603 can immediately return a persistence response (persist_resp) to core 601, that is, CXL controller sends a persistence response while sending the first write request to PMem controller, and PMem controller 604 can return an ACK response to CXL controller 604 after receiving the request.

[0139] Figure 7 FIG. 4 is a schematic diagram of another data stream transmission situation in which the CXL controller is not in the ADR domain according to an embodiment of the present application. Figure 7 As shown, if the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, and the data to be persisted is dirty data, core 701 sends a write&cbo.cleanp instruction to CNOC 702. After receiving the write&cbo.cleanp instruction, CNOC 702 feeds back a response to core 701, and then core 701 sends a write instruction (e.g., write data) to CNOC 702. In response to the instruction, CNOC 702 sends a data persistence instruction (e.g., write&persist_req) to CXL controller 703. CXL controller 703 responds to the data persistence instruction and returns a resp response to CNOC 702. CNOC 702 sends a second write request (e.g., write data) to CXL controller 703. Using the second write request, CXL controller 703 sends the data to be persisted to PMem controller 704. At the same time, CXL controller 703 returns a response resp_cbo to core 701. PMem controller 704 returns a response (ack) to CXL controller 703. In response to the response, CXL controller 703 sends a second response (persist_resp) to core 701. When core 701 receives the second response returned by the high-speed interconnect technology controller based on the second write request, it can send the data to be persisted to the high-speed interconnect technology controller.

[0140] Figure 8is a schematic diagram of data flow transmission of a CXL controller in an ADR domain according to an embodiment of the present application, such as Figure 8 As shown, if the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain and the data to be persisted is clean data, core 801 sends a cbo.cleanp instruction to CNOC 802. After receiving the cbo.cleanp instruction, CNOC 802 will give a response to core 801, and then CNOC 802 sends a data persistence instruction (persist_req) to CXL controller 803. CXL controller 803 responds to the data persistence instruction to send a write request to PMem controller 804. After receiving the write request, PMem controller 804 returns a first response (which can be an ACK response) to CXL controller 803. Since PMem controller 804 has the ability to continue writing to PMem after power failure, CXL controller can return a persistence response (which can be persist_resp) to core, that is, the high-speed interconnect technology controller sends it after receiving the first response sent by the persistent memory controller to indicate that the current persistence request is completed.

[0141] Fig. 9 FIG. 1 is a schematic diagram of data flow transmission of another CXL controller in the ADR domain according to an embodiment of the present application. Fig. 9As shown, if the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain, and the data to be persisted is dirty data, core 901 sends a write&cbo.cleanp instruction to CNOC 902. After receiving the write&cbo.cleanp instruction, CNOC 902 will give a response to core 901, and then core 901 sends a write instruction (e.g., write data) to CNOC 902. CNOC 902 responds to the write instruction and sends a data persistence instruction (e.g., write&persist_req) to CXL controller 903. CXL controller 903 responds to the data persistence instruction and returns a response resp to CNOC 902. CNOC902 sends a second write request (e.g., write data) to CXL controller 903. Using the second write request, CXL controller 903 sends the data to be persisted to PMem controller 904. At the same time, CXL controller 903 returns a response (resp_cbo) to CNOC 902 and sends a second response (persist_resp) to core 901. PMem controller 904 returns a response (ack) to CXL controller 903. When core 901 receives the second response returned by the high-speed interconnect technology controller based on the second write request, it can send the data to be persisted to the high-speed interconnect technology controller.

[0142] In this embodiment, the timing at which the CXL controller returns a persistence response is different depending on whether the CXL controller is in the ADR domain or not. The Core side can determine whether the data persistence instruction has been executed through the persistence response (persist_resp). If the CXL controller is not in the ADR domain, the CXL controller can send a persistence response to the core after the PMem controller returns an acknowledgment (ack) response. If the CXL controller is in the ADR domain, it does not need to wait for the ack response from the PMem controller. After receiving the persistence request from the Coherent Network On Chip (CNOC), it can immediately send a persistence response (persist_resp) to the core. This method can shorten the persistence request time on the core side.

[0143] In this embodiment, there are three control and status registers (Control and Status Register, referred to as CSR) registers, namely: menvcfg, sendvcfg and henncfg, and the above registers can be used to control the execution of the cbo.cleanp instruction.

[0144] Optionally, menvcfg, senvcfg, and henncfg are registers defined in three RISCV architectures, where m, s, and h can represent current privilege levels. The environment configuration register (envcfg for short) can be used to control the configuration information of the execution environment in a mode with lower privileges than the own.

[0145] It should be noted that the above three registers are for each current privileged mode of the RISCV architecture. Each current privileged mode has a CSR register to control the lower privilege mode and execute the cbo.cleanp instruction. It should be noted that there is no specific limit on the number of registers here.

[0146] In this embodiment, all supervisor modes (including VS mode) use the Secure Environment Configuration Register (senvcfg). A hypervisor is responsible for saving and restoring senvcfg when a virtual context is switched. The Heterogeneous Environment Configuration (henvcfg) register will only appear after the H extension is implemented and enabled. The H extension may refer to the virtualization extension in RISCV.

[0147] Table 1 is a general format table of registers. As shown in Table 1, each xenvcfg register (x represents m, s or h) has the following general format:

[0148] Table 1 General format of registers

[0149]

[0150] Optionally, the cbo.cleanp instruction is applicable to situations where data needs to be refreshed to persistent memory. That is, the cbo.cleanp instruction can be used to refresh data to the persistent memory at the corresponding location. However, in order to ensure the persistence order of the memory, the cbo.cleanp and fence instructions can also be used to refresh data to the persistent memory and ensure the order of such refreshes.

[0151] In this embodiment, a persistence instruction can be constructed in advance, and the persistence instruction may include: a field corresponding to the instruction extension (cbo.cleanp), a field corresponding to Base, a field corresponding to CBO, and a field corresponding to MISC-MEM. Among them, the persistence instruction can be used to determine that the action to be executed is a data clearing operation indicated by the cbo.cleanp instruction, and refresh the data to the persistent memory. The effective address of the data clearing operation is the base address specified by the rs1 register (Register), and the offset operand can be omitted and expressed as 0. Table 2 is an instruction code table, and the instruction code can be as shown in Table 2. The field corresponding to cbo.cleanp can be used to characterize the function field. The field corresponding to CBO can also be used to characterize the function field, and can be used to provide additional information for the instruction. The field corresponding to MISC-MEM can be used to characterize the operation type, for example, it can represent memory-related operations.

[0152] Table 2 Instruction code table

[0153]

[0154] In this embodiment, after executing cbo.cleanp (extended instruction), the execution of FENCE R*,*W is applicable to reading and writing. Fence is a memory sorting instruction in RISCV, which can be used to sort memory accesses. For example, fencew,w means that the storage instruction before the FENCE instruction must be executed before all the storage instructions after the FENCE instruction.

[0155] Optionally, for updates to persistent memory, cbo.cleanp can be sorted using fence w,w.

[0156] In this embodiment, during the execution of the cbo.cleanp instruction, a processor exception may be caused due to the status register, address translation, and protection mechanism.

[0157] Optionally, the cbo.cleanp instruction may raise an illegal instruction exception or a virtual instruction exception, depending on the current privilege mode and the state of the CBCPE control register.

[0158] In this embodiment, the cbo.cleanp instruction is similar to a storage instruction, and is an explicit memory access instruction that requires calculation of an effective address, which may be a physical address, and may be converted according to the current privilege mode and conversion mechanism.

[0159] Optionally, the cbo.cleanp instruction can have the following constraints: (1) the effective address is cacheable; (2) if access to the cache block is not allowed, the cbo.cleanp instruction will cause a pagefault or guest-pagefault exception; (3) if address translation is not allowed, any access will cause an accessfault exception.

[0160] In this embodiment, even if the given base address is non-aligned, it can be treated as aligned, so no address non-alignment exception will be generated.

[0161] In this embodiment, with respect to the impact on restricted LR / SC loops, the cbo.cleanp instruction neither changes the properties of LR / SC loops nor modifies the event guarantees they provide.

[0162] Alternatively, the LR / SC loop is a technique for implementing atomic operations in concurrent programming. In the LR / SC loop, data can be loaded into registers and retained by using the LR instruction, and then written back to the memory by using the SC instruction, and the data is written back successfully only if no other thread or process modifies the data. The LR / SC loop can be used to implement atomic operations to avoid race condition problems in concurrent programming.

[0163] In this embodiment, for breakpoint exceptions and debug mode, the behavior of the trigger module with respect to the cbo.cleanp instruction is unspecified unless otherwise defined by the debug architecture specification. If cbo.cleanp is implemented, the following additional trigger module (i.e., trigger) behaviors similar to cbo.clean can be further implemented: (1) Implementing address match triggers should be optional; (2) Type 6 data match triggers, i.e., tdata1.type=6 and mcontrol6.select=1, should not be supported; (3) Memory accesses are treated as stores, i.e., address triggers will match only when mcontrol6.store=1.

[0164] In this embodiment, a new instruction for the RISCV system to support persistent memory is innovatively proposed, and a new instruction (cbo.cleanp) is defined to clarify the process of refreshing data to persistent memory. Two data transmission schemes are designed according to whether the CXL controller belongs to the ADR domain, thereby achieving the technical effect of avoiding data loss in the event of a power outage and solving the technical problem of data loss in the event of a power outage.

[0165] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0166] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0167] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0168] According to an embodiment of the present application, there is also provided a method for implementing the above Figure 3 The data storage method is shown in the data storage device.

[0169] Fig.10 is a schematic diagram of a data storage device according to an embodiment of the present application, such as Fig.10 As shown, the data storage device 1000 may include: a storage unit 1002 , a construction unit 1004 and a sending unit 1006 .

[0170] The storage unit 1002 is used for storing the data to be persisted corresponding to the data persistence request in the cache in response to receiving the data persistence request, and storing the base address of the data to be persisted in the source register.

[0171] The construction unit 1004 is used to construct a data persistence instruction based on the information of the source register, wherein the data persistence instruction is a predefined extended instruction.

[0172] The sending unit 1006 is used to send a data persistence instruction to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory.

[0173] Here, the storage unit 1002, the construction unit 1004 and the sending unit 1006 correspond to steps S302 to S306 in the above embodiment, and the three units and the corresponding steps implement the same examples and application scenarios, but are not limited to the contents disclosed in the above embodiment. It should be noted that the above units can be hardware components or software components stored in a memory and processed by one or more processors, and the above units can also be run in a computer terminal as part of the device.

[0174] In the data storage device, data persistence instructions are constructed based on the information of the source register. By defining new data persistence instructions, the method of refreshing the persistent data in the cache to the persistent memory is clarified, thereby providing a guarantee for data persistence and further achieving the technical effect of avoiding data loss in the event of a power outage, solving the technical problem of data loss in the event of a power outage.

[0175] In an optional embodiment, Fig.11 Schematic diagram of a RISC-V architecture system on chip according to the present application. Fig.11 As shown, the system on chip (System On Chip, referred to as SOC) includes at least one RISC-V core 1102 (only one is shown in the figure), and the RISC-V core 1102 is connected to peripheral devices through a bus 1104, including but not limited to ROM 1106, RAM 1108, timer 1110, UART (Universal Asynchronous Receiver / Transmitter) 1112, GPIO (General Purpose Input / Output) 1114, SPI (Serial Peripheral Interface Bus) 1116, etc.

[0176] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0177] According to another aspect of an embodiment of the present application, a processor is further provided, which is used to run a program, and the program executes the above-mentioned data storage method when it is run.

[0178] Optionally, the processor may adopt a reduced instruction set architecture.

[0179] According to another aspect of an embodiment of the present application, a computing device is also provided, which may include: a persistent memory; a processor, connected to the persistent memory, and used to store the data to be persisted corresponding to the data persistence request in a cache in response to receiving a data persistence request, and store the base address of the data to be persisted in a source register; based on information in the source register, construct a data persistence instruction, wherein the data persistence instruction is a predefined extended instruction; the persistent memory is also used to store the data to be persisted based on the persistence instruction.

[0180] Optionally, the processor is connected to the persistent memory via a high-speed interconnect technology bus, and the computing device further includes: a high-speed interconnect technology controller, used to receive a data persistence instruction, generate a first write request, and send a persistence response to the processor, wherein the processor is used to receive the persistence response, wherein the timing of sending the persistence response is determined based on whether the high-speed interconnect technology controller is in an asynchronous refresh mechanism domain; a persistent memory controller, connected to the high-speed interconnect technology controller and the persistent memory, used to receive the first write request, and write the data to be persisted into the persistent memory.

[0181] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method in each embodiment provided in the first embodiment.

[0182] Optionally, in this embodiment, the computer-readable storage medium may be located in any one of the computer terminals in a computer terminal group in a computer network, or in any one of the mobile terminals in a mobile terminal group.

[0183] In an embodiment of the present application, a data persistence instruction is constructed based on the information of the source register. By defining a new data persistence instruction, a method for refreshing the persistent data in the cache to the persistent memory is clarified, thereby providing a guarantee for data persistence, and further achieving the technical effect of avoiding data loss in the event of a power outage, and solving the technical problem of data loss in the event of a power outage.

[0184] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include computer program instructions, and the computer program instructions implement the method provided by the embodiment when executed by a processor.

[0185] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store computer program instructions, and the computer program instructions implement the method provided in the embodiments when executed by a processor.

[0186] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0187] According to an embodiment of the present application, a data storage method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0188] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor that may be a dedicated or general purpose programmable processor that may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0189] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0190] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0191] To provide interaction with a user, the systems and techniques described herein may be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or an LCD (liquid crystal display, monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a path ball) through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0192] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0193] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0194] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0195] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0196] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0197] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0198] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0199] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), mobile hard disk, disk or optical disk and other media that can store program codes.

[0200] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data storage method, characterized in that: Applied to a processor, the method comprises: In response to receiving a data persistence request, storing the data to be persisted corresponding to the data persistence request in a cache, and storing a base address of the data to be persisted in a source register; Based on the information of the source register, construct a data persistence instruction, wherein the data persistence instruction is a predefined extended instruction; The data persistence instruction is sent to the persistent memory, wherein the data persistence instruction is used to store the data to be persisted in the persistent memory.

2. The method according to claim 1, characterized in that The processor is connected to the persistent memory via a high-speed interconnect technology bus, wherein sending the data persistence instruction to the persistent memory includes: Sending the data persistence instruction to a high-speed interconnect technology controller corresponding to the high-speed interconnect technology bus, wherein the data persistence instruction is used to control the high-speed interconnect technology controller to send a first write request to a persistent memory controller, and the first write request is used to control the persistent memory controller to write the data to be persisted into the persistent memory; A persistence response sent by the high-speed interconnect technology controller is received, wherein a sending timing of the persistence response is determined based on whether the high-speed interconnect technology controller is in an asynchronous refresh mechanism domain.

3. The method according to claim 2, characterized in that When the high-speed interconnect technology controller is in the asynchronous refresh mechanism domain, the persistence response is sent by the high-speed interconnect technology controller while sending the first write request; when the high-speed interconnect technology controller is not in the asynchronous refresh mechanism domain, the persistence response is sent by the high-speed interconnect technology controller after receiving the first response sent by the persistent memory controller.

4. The method according to claim 2, characterized in that: The sending of the data persistence instruction to the high-speed interconnect technology controller corresponding to the high-speed interconnect technology bus includes: Determine the current state of the data to be persisted in the cache; When the current state is clean data, the data persistence instruction is sent to the high-speed interconnect technology controller.

5. The method according to claim 4, characterized in that When the current state is dirty data, the method further includes: Sending the data persistence instruction and the second write request to the high-speed interconnect technology controller; Upon receiving a second response returned by the high-speed interconnect technology controller based on the second write request, the data to be persisted is sent to the high-speed interconnect technology controller, wherein the second write request is sent by the high-speed interconnect technology controller to the persistent memory controller after receiving the data to be persisted.

6. The method according to any one of claims 1 to 5, characterized in that The length of the persistence instruction is a first preset length, and the persistence instruction includes a source register field, a function field, and an operation category field, wherein the field value of the source register field is used to represent the information of the source register, the field value of the function field is used to represent the change management instruction and the persistence function, and the field value of the operation category field is used to represent the operation corresponding to the memory.

7. The method according to any one of claims 1 to 5, characterized in that The method further comprises at least one of the following: After sending the persistence instruction to the persistent memory, sending a first masking instruction to the persistent memory, wherein the first masking instruction is used to control the persistent memory to execute a read request or a write request after the first masking instruction after completing the read request or the write request before the first masking instruction; After sending the persistence instruction to the persistent memory, sending a second masking instruction to the persistent memory, and sending a new persistence instruction to the persistent memory again, wherein the second masking instruction is used to control the persistent memory to execute the new persistence instruction after completing the execution of the persistence instruction.

8. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Determine the current privileged mode of the processor, and obtain the value stored in the status register corresponding to the persistence instruction; Determining whether the persistence instruction is abnormal based on the current privileged mode and the value stored in the status register; The persistence instruction is sent when there is no abnormality in the persistence instruction.

9. The method according to claim 8, characterized in that The current privileged mode includes one of the following: a machine mode, a supervisor mode, and a user mode in descending order, the status register includes: a high-level register, a mid-level register, and a low-level register, wherein the determining whether the persistent instruction is abnormal based on the current privileged mode and the value stored in the status register includes: In a case where the current privileged mode and the value stored in the status register satisfy a first condition, determining that an illegal instruction exception exists in the persistent instruction; In a case where the current privileged mode and the value stored in the status register satisfy a second condition, determining that a virtual instruction exception exists in the persistence instruction; When the current privileged mode and the value stored in the status register do not satisfy the first condition, and the current privileged mode and the value stored in the status register do not satisfy the second condition, determining that there is no abnormality in the persistence instruction; The first condition includes one of the following: the current privileged mode is not the machine mode, and the value stored in the high-level register is not a preset value; the current privileged mode is the user mode, and the value stored in the mid-level register is not the preset value; The second condition includes one of the following: the current privileged mode is the supervisor mode, and the value stored in the low-level register is not a preset value; the current privileged mode is the user mode, and the value stored in the low-level register is not the preset value; the current privileged mode is the user mode, and the value stored in the mid-level register is not the preset value.

10. The method according to any one of claims 1 to 5, characterized in that The persistent instruction is converted by the persistent memory into a physical address based on the current privileged mode and conversion mechanism of the processor, wherein, when the attribute corresponding to the physical address is that access is not allowed, it is determined that a page fault exception exists in the persistent instruction; when conversion of the base address is not allowed, it is determined that an access fault exception exists in the persistent instruction.

11. The method according to any one of claims 1 to 5, characterized in that In response to the data persistence request being received during the execution of a preset cycle by the processor, the preset cycle comprising one of the following: a load-reserve cycle and a store-conditional cycle; the method further comprises: After the persistence instruction is generated, the preset loop is continued to be executed.

12. The method according to any one of claims 1 to 5, characterized in that The method further comprises: When the data type of the persistence instruction is a preset type and the selection attribute of the base address is a first value, determining to execute a first logic function corresponding to a data matching trigger; When the storage attribute of the base address is a second value, it is determined to execute a second logic function corresponding to the address matching trigger.

13. A processor, characterized in that: Used to run the program, wherein the method according to any one of claims 1 to 12 is executed when the program is run.

14. The processor according to claim 13, characterized in that The processor adopts a reduced instruction set architecture.

15. A computing device, characterized in that: include: Persistent memory; A processor connected to the persistent memory, configured to, in response to receiving a data persistence request, store the data to be persisted corresponding to the data persistence request in a cache, and store the base address of the data to be persisted in a source register; and construct a data persistence instruction based on information of the source register, wherein the data persistence instruction is a predefined extended instruction; The persistent memory is further used to store the data to be persisted based on the persistence instruction.

16. The computing device according to claim 15, characterized in that The processor is connected to the persistent memory via a high-speed interconnect technology bus, and the computing device further includes: A high-speed interconnect technology controller, configured to receive the data persistence instruction, generate a first write request, and send a persistence response to the processor, wherein the processor is configured to receive the persistence response, and a timing of sending the persistence response is determined based on whether the high-speed interconnect technology controller is in an asynchronous refresh mechanism domain; A persistent memory controller is connected to the high-speed interconnect technology controller and the persistent memory, and is used to receive the first write request and write the data to be persisted into the persistent memory.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed, the device where the storage medium is located is controlled to execute the method according to any one of claims 1 to 12.

18. A computer program product, characterized in that The method comprises computer program instructions which, when executed by a processor, implement the method according to any one of claims 1 to 12.

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