Instruction processing method and device, storage medium and computer equipment

Abstract

The embodiment of the invention discloses an instruction processing method and device, a storage medium and computer equipment. The instruction processing method comprises the steps of obtaining a type ratio of an instruction sequence; wherein each type ratio represents the proportion of the instruction corresponding to one type in the instruction sequence; based on the type ratio, determining a transmitting path adopted by each type of instruction; and transmitting the to-be-transmitted instruction in the instruction sequence to the corresponding pipeline execution unit through the corresponding transmission path.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of integrated circuits, and in particular to an instruction processing method, apparatus, storage medium, and computer equipment. Background Art

[0002] A thread is the smallest unit that an operating system can schedule operations on. A thread is contained in a process and is the actual operating unit in the process. A thread refers to a single sequential control flow in a process. A process can have multiple threads running concurrently, and each thread executes different tasks in parallel.

[0003] A warp includes multiple threads. Instructions are sent from the warp to the execution unit for execution. In the related art, the instruction sending path is relatively single, and all instructions are sent to the execution unit through the same sending path, resulting in low instruction sending performance. Summary of the invention

[0004] In view of this, embodiments of the present application provide an instruction processing method, apparatus, device and storage medium, which can improve the efficiency of instruction transmission.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] An embodiment of the present application provides an instruction processing method, which includes: obtaining a type ratio value of an instruction sequence; wherein each type ratio value represents the proportion of instructions of a corresponding type in the instruction sequence; based on the type ratio value, determining the emission path adopted by each type of the instruction; and emitting the to-be-emitted instruction in the instruction sequence to the corresponding pipeline execution unit via the corresponding emission path.

[0007] In the above scheme, based on the type ratio value, determining the emission path used by each type of the instruction includes: determining at least two types of instructions whose type ratio values ​​meet the merging condition to use the same emission path.

[0008] In the above scheme, at least two types of instructions whose type proportions meet the merging conditions are determined to use the same emission path, including: if the type proportion of the first instruction is lower than a threshold value, the first instruction and other types of instructions are determined to use the same emission path; and / or, if the type proportions of the second instruction and the third instruction are both higher than a threshold value, and the second instruction and the third instruction are not the highest instructions, the second instruction and the third instruction are determined to use the same emission path; wherein the type proportion of the highest instruction is the highest.

[0009] In the above scheme, obtaining the type proportion value of the instruction sequence includes: after the compilation of the instruction sequence is completed, counting the number of occurrences of each type of instruction in the instruction sequence; and calculating the type proportion value based on the number of occurrences of each type of instruction.

[0010] In the above scheme, obtaining the type ratio value of the instruction sequence also includes: determining the type ratio value of the instruction sequence based on historical data.

[0011] In the above scheme, the instruction to be issued is issued to the corresponding pipeline execution unit, including: obtaining pre-decoding information of the instruction to be issued; the pre-decoding information includes: waiting cycle; the waiting cycle represents the number of cycles that the instruction to be issued needs to wait before issuing; when the instruction to be issued reaches the corresponding waiting cycle, the instruction to be issued is issued

[0012] In the above scheme, the waiting period of the instruction to be issued is set based on the data dependency of the instruction to be issued; the instruction to be issued is not set with preparation information, wherein the preparation information indicates whether the data dependency is released.

[0013] An embodiment of the present application also provides an instruction processing device, which includes: a thread controller, multiple emission paths and multiple pipeline execution units; wherein the first ends of the multiple emission paths are electrically connected to the thread controller; each of the pipeline execution units is electrically connected to the second end of the corresponding at least one emission path; the thread controller is electrically connected to the thread bundle; the thread controller includes: a first control module; the first control module is configured to obtain a type ratio value of an instruction sequence; and, based on the type ratio value, determine the emission path used by each type of instruction; and, emit the to-be-emitted instructions in the instruction sequence from the thread bundle via the corresponding emission path to the corresponding pipeline execution unit; wherein each type ratio value represents the proportion of instructions of a corresponding type in the instruction sequence.

[0014] In the above solution, the thread controller further includes: a second control module; the second control module is configured to retrieve the instruction from the instruction cache to the thread warp; and decode the retrieved instruction.

[0015] In the above scheme, a configuration register is set on each of the transmission paths; the first control module is also configured to configure type information for the instruction to be transmitted based on the type ratio value; and, the type information is compared with the information of the configuration register of each of the transmission paths, and if the comparison result is a match, the instruction to be transmitted is stored in the corresponding configuration register.

[0016] In the above solution, the first control module is further configured to determine that at least two types of instructions whose type proportions meet the merging condition adopt the same transmission path.

[0017] In the above scheme, the first control module is also configured to, if the type ratio value of the first instruction is lower than a threshold value, determine the first instruction and other types of instructions to use the same transmission path; and / or, if the type ratio values ​​of the second instruction and the third instruction are both higher than a threshold value, and the second instruction and the third instruction are not the highest instructions, determine the second instruction and the third instruction to use the same transmission path; wherein the type ratio value of the highest instruction is the highest.

[0018] In the above scheme, the first control module is further configured to obtain pre-decoding information of the instruction to be transmitted; the pre-decoding information includes: a waiting period; and when the instruction to be transmitted reaches the corresponding waiting period, the instruction to be transmitted is transmitted.

[0019] In the above solution, the first control module is further configured to receive and respond to a warp emission enable signal to continuously emit the to-be-emitted instructions in the warp, or to suspend the emission of the to-be-emitted instructions in the warp.

[0020] An embodiment of the present application also provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the steps in the above method.

[0021] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method are implemented.

[0022] An embodiment of the present application also provides a computer device, including the instruction processing device described in the above solution.

[0023] It can be seen that in the embodiment of the present application, a corresponding launch path is configured for each type of instruction based on the type ratio value, so that different types of instructions can be launched in parallel, and the number of instructions carried on different launch paths can be balanced. Thus, the utilization efficiency of the launch path is improved, and at the same time, the launch congestion of a single path will not block the instructions of other paths, that is, the efficiency of instruction launch is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the implementation process of the instruction processing method provided in the embodiment of the present application Figure 1 ;

[0025] Figure 2 Schematic diagram of the implementation process of the instruction processing method provided in the embodiment of the present application Figure 2 ;

[0026] Figure 3 Schematic diagram of the implementation process of the instruction processing method provided in the embodiment of the present application Figure 3 ;

[0027] Figure 4 Schematic diagram of the implementation process of the instruction processing method provided in the embodiment of the present application Figure 4 ;

[0028] Figure 5 Schematic diagram of the implementation process of the instruction processing method provided in the embodiment of the present application Figure 5 ;

[0029] Figure 6 Schematic diagram of the structure of the instruction processing device provided in the embodiment of the present application Figure 1 ;

[0030] Figure 7 A schematic diagram of the structure of a thread controller provided in an embodiment of the present application;

[0031] Figure 8 Schematic diagram of the structure of the instruction processing device provided in the embodiment of the present application Figure 2 ;

[0032] Fig. 9 Schematic diagram of the structure of the instruction processing device provided in the embodiment of the present application Figure 3 ;

[0033] Fig.10 A schematic diagram of the hardware entity of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0035] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing this application and are not intended to limit this application.

[0037] The embodiment of the present application provides an instruction processing method, which can be executed by a processor of a computer device. The computer device may refer to a server, a laptop, a tablet computer, a desktop computer, a smart TV, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable gaming device), or other device with data processing capabilities.

[0038] Figure 1 A schematic diagram of an implementation flow of an instruction processing method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes steps S101 to S103.

[0039] S101, obtaining a type ratio value of an instruction sequence.

[0040] In the embodiment of the present application, each type ratio value represents the proportion of the corresponding type of instructions in the instruction sequence.

[0041] The following Table 1 illustrates the type ratios of several test sets (ie, instruction sequences used for testing), which will be explained in conjunction with Table 1.

[0042] Test Set FP32 INT32 BIT other 3DMark11_GT1 46.67％ 1.79％ 1.45％ 50.09％ 51_Meet_Lumen 49.33％ 9.41％ 6.65％ 34.61％ PUBG_DaTing 61.78％ 5.37％ 3.36％ 29.49％ 51_WDP 29.64％ 21.93％ 7.74％ 40.71％

[0043] Table 1

[0044] Table 1 above lists the types of floating-point instructions FP32, integer instructions INT32, and bit operation type instructions BIT. For example, in the test set 3DMark11_GT1, floating-point instructions FP32 account for 46.67%, integer instructions INT32 account for 1.79%, and bit operation type instructions BIT account for 1.45%. It should be noted that floating-point instructions FP32, integer instructions INT32, and bit operation type instructions BIT all belong to ALU (Arithmetic and Logic Unit) instructions.

[0045] In the embodiment of the present application, after compiling the instruction sequence, the compiler can count the proportion of different types of instructions in the instruction sequence, that is, count the type ratio of the instruction sequence. Accordingly, before the instructions in the instruction sequence are emitted, the type ratio of the instruction sequence can be obtained from the compiler.

[0046] S102: Determine the emission path used by each type of instruction based on the type ratio value.

[0047] S103 , issuing the to-be-issued instructions in the instruction sequence to the corresponding pipeline execution unit via the corresponding issue path.

[0048] It should be noted that the instruction issuance path is the key path for instructions to enter the execution stage from the compilation stage. Therefore, whether the issuance path is smooth directly affects the efficiency of instruction issuance.

[0049] In the related art, the instruction emission path is not effectively controlled and planned; this may cause a certain emission path to carry too many instructions and cause emission congestion, while other emission paths may carry fewer instructions and be idle; thus, each emission path is not fully utilized, resulting in a waste of resources and reducing the efficiency of instruction emission.

[0050] In the embodiment of the present application, a corresponding launch path can be configured for each type of instruction based on the type ratio. Furthermore, for each instruction to be launched in the instruction sequence, the instruction to be launched can be launched to the corresponding pipeline execution unit via the launch path corresponding to the type of the instruction to be launched for execution.

[0051] In the embodiment of the present application, if a certain type of instruction accounts for a large proportion, a separate emission path can be allocated for the instruction of this type; at the same time, multiple types of instructions with a smaller proportion can be combined to use another emission path. In addition, if a certain type of instruction accounts for a large proportion, the instruction of this type can also be emitted by multiple optional emission paths.

[0052] It can be understood that, based on the type ratio value, a corresponding launch path is configured for each type of instruction, so that different types of instructions can be launched in parallel, and the number of instructions carried on different launch paths can be balanced. Thus, the utilization efficiency of the launch path is improved, and at the same time, the launch congestion of a single path will not block the instructions of other paths, that is, the efficiency of instruction launch is improved.

[0053] In some embodiments of the present application, Figure 2 Step S201 is shown to achieve Figure 1 The step S102 shown will be explained in conjunction with each step.

[0054] S201. Determine at least two types of instructions whose type ratios satisfy a merging condition to use the same issuance path.

[0055] In the embodiment of the present application, in the process of determining the emission path used by each type of instruction, the type ratio value can be determined according to the merging condition. Furthermore, if the type ratio values ​​of at least two types of instructions meet the merging condition, these types of instructions can be merged to use the same emission path. Correspondingly, for instructions that do not meet the merging condition, a separate emission path is used according to the type of the instruction.

[0056] It is understandable that instructions that meet the merging conditions are merged to use the same emission path; in this way, while ensuring the instruction emission efficiency, the number of occupied emission paths can be reduced; thereby, resource occupation can be saved and power consumption can be reduced.

[0057] In some embodiments of the present application, Figure 3 Steps S202 and / or S203 are shown to achieve Figure 2 The step S201 shown will be explained in conjunction with each step.

[0058] S202: If the type ratio of the first instruction is lower than a threshold, the first instruction and other types of instructions are determined to use the same issuance path.

[0059] In the embodiment of the present application, the first instruction is any type of instruction. The other types of instructions are any type of instructions in the instruction sequence except the first instruction.

[0060] It should be noted that the threshold of the type ratio can be set according to demand, and the embodiment of the present application takes the threshold of 5% as an example for explanation.

[0061] Referring to Table 1 above, for example, in the test set 3DMark11_GT1, the proportion of integer instructions INT32 is 1.79%, and the proportion of bit operation type instructions BIT is 1.45%, both of which are lower than the threshold value of 5%; therefore, the two types of instructions (integer instructions INT32 and bit operation type instructions BIT) can be determined to use the same emission path; or, the three types of instructions (integer instructions INT32, bit operation type instructions BIT and floating point type instructions FP32) can be determined to use the same emission path.

[0062] Continuing to refer to Table 1, for example, in the test set PUBG_DaTing, the proportion of bit operation type instructions BIT is 3.36%, which is lower than the threshold value of 5%; therefore, the two types of instructions (bit operation type instructions BIT and floating point type instructions FP32) can be determined to use the same emission path; or, the two types of instructions (integer instructions INT32 and bit operation type instructions BIT) can be determined to use the same emission path.

[0063] It can be understood that if the type ratio value of the first instruction is lower than the threshold, it means that the proportion of the first instruction in the test sequence is very small. Therefore, combining the first instruction with other types of instructions and using the same transmission path will neither significantly increase the number of instructions transmitted in the adopted transmission path, nor reduce the number of occupied transmission paths, thereby saving resource usage and reducing power consumption.

[0064] S203: If the type proportions of the second instruction and the third instruction are both higher than the threshold, and the second instruction and the third instruction are not the highest instructions, the second instruction and the third instruction are determined to use the same issuance path.

[0065] In the embodiment of the present application, the highest instruction type has the highest proportion value; referring to Table 1 above, in the four test sets listed in Table 1, the floating point type instruction FP32 has the highest proportion value, that is, the floating point type instruction FP32 is the highest instruction. The second instruction and the third instruction are both instructions of any type.

[0066] Referring to Table 1 above, for example, in the test set 51_Meet_Lumen, the proportion of integer instructions INT32 is 9.41%, and the proportion of bit operation type instructions BIT is 6.65%, both of which are higher than the threshold of 5%, but at the same time neither of them is the highest instruction; therefore, the two types of instructions (integer instructions INT32 and bit operation type instructions BIT) can be determined to use the same emission path.

[0067] It is understandable that the type ratios of the second and third instructions are both higher than the threshold. If the second or third instruction is merged into the emission path of the highest instruction, the number of instructions transmitted in the emission path of the highest instruction will be significantly increased, and the number of instructions configured in each emission path will be unbalanced, thereby affecting the efficiency of instruction emission. Therefore, merging the second instruction and the third instruction into the same emission path will not affect the efficiency of instruction emission, but can also reduce the number of emission paths occupied, thereby saving resource occupancy and reducing power consumption.

[0068] In some embodiments of the present application, Figure 4 Steps S301 to S302 are shown to achieve Figure 1 The step S101 shown will be explained in conjunction with each step.

[0069] S301: After the instruction sequence is compiled, count the number of occurrences of each type of instruction in the instruction sequence.

[0070] S302: Calculate the type ratio based on the number of occurrences of each type of instruction.

[0071] In the embodiment of the present application, after the instructions in the instruction sequence are compiled, the number of occurrences of each type of instruction in the instruction sequence can be counted; for example, the number of occurrences of floating-point type instruction FP32, integer type instruction INT32, and bit operation type instruction BIT can be counted respectively. Furthermore, the number of occurrences of each type of instruction can be divided by the total number of instructions in the instruction sequence, so that the type proportion value corresponding to each type of instruction can be obtained.

[0072] It is understandable that the number of occurrences of each type of instruction in the instruction sequence is counted and the type proportion value is calculated. In this way, a more accurate type proportion value can be obtained to reflect the actual proportion of each type of instruction in the instruction sequence, so that the emission path can be allocated more accurately for each type of instruction.

[0073] In some embodiments of the present application, Figure 4 Step S303 is shown to achieve Figure 1 The step S101 shown will be explained in conjunction with each step.

[0074] S303: Determine the type ratio of the instruction sequence based on historical data.

[0075] In the embodiment of the present application, the compiler software can count the historical frequency of each type of instruction in the process of writing the operator, that is, it can obtain the historical data of the type ratio. Therefore, the historical data of the type ratio can be directly used as the type ratio of the current instruction sequence to allocate an emission path for each type of instruction.

[0076] It is understandable that by using the historical data of the type ratio value as the type ratio value of the current instruction sequence, it is possible to avoid the real-time calculation of the type ratio value of the instruction sequence, thus saving time and improving the efficiency of instruction emission.

[0077] In some embodiments of the present application, Figure 5 Steps S401 to S402 are shown to achieve Figure 1 S103 shown will be described in conjunction with each step.

[0078] S401, obtaining pre-decoding information of a to-be-transmitted instruction; the pre-decoding information includes: a waiting period.

[0079] It should be noted that the following Table 2 illustrates the pre-decoding information of each instruction.

[0080] vld rdy resv op wcys Instr words info

[0081] Table 2

[0082] In Table 2 above, vld (Verify Load) is mainly used for verification during data loading to check whether the loaded data is as expected or valid.

[0083] rdy (Ready) is used to indicate that a device, data, or status is ready for the next operation, ensuring that the correct operation is performed at the right time. rdy can indicate whether the instruction releases data dependency.

[0084] resv (Reserve, reservation information) is used to reserve resources for specific operations or data, indicating whether the instruction is reserved. resv is used to retrieve the subsequent instructions of the jump when retrieving the jump instruction; the subsequent instructions need to wait until it is determined whether to jump before executing, otherwise they will be discarded.

[0085] op (Operation, operation information), used to indicate the operation type of the operation.

[0086] wcys (wait cycles) indicates the number of cycles the instruction needs to wait.

[0087] instr words info indicates other relevant information of the instruction and has no effect on the transmission.

[0088] S402: When the instruction to be issued reaches the corresponding waiting period, the instruction to be issued is issued.

[0089] In an embodiment of the present application, the compiler can set corresponding data dependencies and waiting cycles on each instruction while compiling an instruction sequence. Among them, the data dependency of an instruction means that the execution of the instruction depends on the results of other instructions. The waiting cycle of an instruction represents the number of cycles that the instruction needs to wait before it is emitted, that is, the instruction needs to wait for a number of cycles before it is emitted.

[0090] It should be noted that when the thread warp enters the ready state, the instruction processing device can retrieve the instruction on which the instruction to be issued depends from the instruction buffer. If the result of the instruction on which the instruction to be issued depends can be retrieved, the instruction to be issued can release the data dependency. However, since the process of retrieving instructions takes time, if the instruction to be issued is issued after waiting for the data dependency to be released, it is not conducive to improving the emission efficiency.

[0091] In some embodiments of the present application, the waiting period of the instruction to be issued is set based on the data dependency of the instruction to be issued. The instruction to be issued does not set the preparation information (rdy), wherein the preparation information indicates whether the data dependency is released.

[0092] That is to say, in the embodiment of the present application, the number of cycles to wait can be set based on the data dependency of each instruction; at the same time, the rdy of the instruction to be issued can be not set. In this way, when the instruction to be issued reaches the corresponding number of cycles to wait, the instruction to be issued is issued in advance, thereby improving the issuance efficiency and the utilization rate of the instruction pipeline.

[0093] In the embodiment of the present application, it is possible to determine whether the instruction to be issued can be issued based on the pre-decoding information of the instruction to be issued. If the rdy of the instruction to be issued is characterized as releasing the data dependency, and the number of cycles waiting for the instruction to be issued reaches wcys, then the instruction to be issued can be issued. On the other hand, the rdy of the instruction to be issued can be not set, so that if the number of cycles waiting for the instruction to be issued reaches wcys, the instruction to be issued can still be issued.

[0094] For example, for the following instructions a, b, c, and d:

[0095] FADD.wcys0 R0,R1,R2 / / instruction a;

[0096] FADD.wcys0 R3,R4,R5 / / instruction b;

[0097] FMA.wcys5 R6,R7,R8,R9 / / instruction c;

[0098] FADD.wcys0 R1,R9,R6 / / instruction d.

[0099] Among them, instruction a represents writing R1+R2 into R0; instruction b represents writing R4+R5 into R3; instruction c represents writing R7+R8*R9 into R6; instruction d represents writing R9+R6 into R1.

[0100] Since the data of instruction d depends on the execution result R6 of instruction c, at this time, if the fence dependency mechanism is fully used for detection, it is necessary to wait for R6 to be written into the general data register, and then release the data dependency of instruction d, and then select instruction d to be issued. In this way, it is necessary to wait for about 8 cycles to issue instruction d.

[0101] However, after the introduction of the wcys mechanism, instruction c sets the wcys5 signal during the compilation phase. When there are no other dependencies or emission issues, instruction d that depends on instruction c can be emitted by satisfying the wcys5 signal (that is, only waiting for 5 cycles). This reduces 3 waiting cycles and improves the utilization rate of the instruction pipeline.

[0102] Figure 6 The following is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application. Figure 6 As shown, the instruction processing device 800 includes: a thread controller 810, a plurality of emission paths 820 and a plurality of pipeline execution units 830. The first ends of the plurality of emission paths 820 are electrically connected to the thread controller 810; each pipeline execution unit 830 is electrically connected to the second end of at least one corresponding emission path 820; and the thread controller 810 is electrically connected to the thread bundle.

[0103] In some embodiments of the present application, reference Figure 7 The thread controller 810 includes: a first control module 811. The first control module 811 is configured to obtain a type ratio value of an instruction sequence; and, based on the type ratio value, determine an issue path 820 used by each type of instruction; and, issue the to-be-issued instruction in the instruction sequence from the thread bundle to the corresponding pipeline execution unit 830 via the corresponding issue path 820. Each type ratio value represents the proportion of a corresponding type of instruction in the instruction sequence.

[0104] In an embodiment of the present application, the first control module 811 can configure a corresponding transmission path 820 for each type of instruction based on the type ratio value; in this way, different types of instructions can be transmitted in parallel; thus, transmission congestion of a single path will not block instructions of other paths, thereby improving the efficiency of instruction transmission.

[0105] In some embodiments of the present application, continue to refer to Figure 7The thread controller 810 further includes a second control module 812. The second control module 812 is configured to retrieve instructions from the instruction cache to the thread warp; and decode the retrieved instructions.

[0106] In the embodiment of the present application, the first control module 811 is used to control the transmission of instructions, and the second control module 812 is used to retrieve instructions and decode them. In other words, the first control module 811 and the second control module 812 in the thread controller 810 are designed as a separate structure; the first control module 811 and the second control module 812 can run independently without affecting each other.

[0107] That is to say, if there is enough space in the thread warp and there are no problems such as "missing instruction buffer line, unclear jump address, and failure to reach the end instruction", the second control module 812 can always fetch instructions to the thread warp. Accordingly, the first control module 811 only needs to check "whether the data dependency is released, whether the waiting cycle is reached, and whether the emission enable is turned on" to select the corresponding instruction to be emitted from the instruction sequence for emission.

[0108] It can be understood that the first control module 811 and the second control module 812 are designed as separate structures; in this way, the first control module 811 for transmitting instructions and the second control module 812 for retrieving instructions and decoding can operate independently; thereby avoiding mutual interference and improving their respective operating efficiency.

[0109] In some embodiments of the present application, the first control module 811 is further configured to determine at least two types of instructions whose type ratios satisfy a merging condition to use the same transmission path 820 .

[0110] In some embodiments of the present application, the first control module 811 is further configured to determine the first instruction and other types of instructions to use the same emission path 820 if the type ratio value of the first instruction is lower than a threshold value; and / or, if the type ratio values ​​of the second instruction and the third instruction are both higher than a threshold value, and the second instruction and the third instruction are not the highest instructions, determine the second instruction and the third instruction to use the same emission path 820; wherein the type ratio value of the highest instruction is the highest.

[0111] It is understandable that instructions that meet the merging conditions are merged to use the same emission path; in this way, while ensuring the instruction emission efficiency, the number of occupied emission paths can be reduced; thereby, resource occupation can be saved and power consumption can be reduced.

[0112] In some embodiments of the present application, the first control module 811 is further configured to count the number of occurrences of each type of instruction in the instruction sequence after the instruction sequence is compiled; and calculate the type proportion value based on the number of occurrences of each type of instruction.

[0113] It is understandable that the number of occurrences of each type of instruction in the instruction sequence is counted and the type proportion value is calculated. In this way, a more accurate type proportion value can be obtained to reflect the actual proportion of each type of instruction in the instruction sequence, so that the emission path can be allocated more accurately for each type of instruction.

[0114] In some embodiments of the present application, the first control module 811 is further configured to determine a type ratio value of the instruction sequence based on historical data.

[0115] It is understandable that by using the historical data of the type ratio value as the type ratio value of the current instruction sequence, it is possible to avoid the real-time calculation of the type ratio value of the instruction sequence, thus saving time and improving the efficiency of instruction emission.

[0116] In some embodiments of the present application, reference Figure 8 , a configuration register 840 is provided on each transmission path 820. The first control module 811 is further configured to configure type information for the instruction to be transmitted based on the type ratio value; and compare the type information with the information of the configuration register 840 of each transmission path 820, and if the comparison result is a match, store the instruction to be transmitted in the corresponding configuration register 840.

[0117] In an embodiment of the present application, the driver program pre-configures the type information on multiple emission paths 820 in the configuration register 840, that is, the information of the configuration register 840; then, the thread controller 810 can compare the type information of the instruction to be emitted (that is, the op information in Table 2) with the information of the configuration register 840. If the comparison result is a match, the matching instruction to be emitted is selected and stored in the corresponding configuration register 840, that is, the instruction to be emitted is passed into the corresponding emission path 820.

[0118] Fig. 9 An example of an optional structure of the instruction processing device 800 is shown. Fig. 9In the example, the instruction processing device 800 is provided with: an ALU issuing path 821, a vector issuing path 822 inside the stream processor, a vector issuing path 823 outside the stream processor, a matrix instruction issuing path 824, and a scalar instruction issuing path 825. The instruction processing device 800 is also provided with: a floating point ALU pipeline execution unit 831, an integer ALU pipeline execution unit 832, a pipeline execution unit 833 inside the stream processor, a pipeline execution unit 834 outside the stream processor, a matrix instruction pipeline execution unit 835, a control instruction pipeline execution unit 836, and a scalar instruction pipeline execution unit 837.

[0119] Combination Fig. 9 As shown in Table 1, the floating-point ALU pipeline execution unit 831 is used to execute the floating-point type instruction FP32, which can be issued via the ALU emission path 821. The integer ALU pipeline execution unit 832 is used to execute the integer instruction INT32, which can be issued via the ALU emission path 821 or the vector emission path 822 in the stream processor. The bit operation type instruction BIT can also be issued via the ALU emission path 821 or the vector emission path 822 in the stream processor.

[0120] Other instructions in Table 1 may include: vector instructions within the stream processor, vector instructions outside the stream processor, matrix instructions, and scalar instructions. These other instructions are also passed through Fig. 9 The corresponding emission path is transmitted to the corresponding pipeline execution unit.

[0121] In some embodiments of the present application, reference Figure 7 The first control module 811 is further configured to obtain pre-decoding information of the instruction to be transmitted; wherein the pre-decoding information includes: a waiting period; and, when the instruction to be transmitted reaches the corresponding waiting period, transmitting the instruction to be transmitted.

[0122] In some embodiments of the present application, the waiting period of the instruction to be issued is set based on the data dependency of the instruction to be issued; the instruction to be issued is not set with preparation information, wherein the preparation information indicates whether the data dependency is released.

[0123] In the embodiment of the present application, the waiting period can be set based on the data dependency of each instruction. When the instruction to be issued reaches the corresponding waiting period, the instruction to be issued can be issued in advance, thereby improving the issuance efficiency and the utilization rate of the instruction pipeline.

[0124] In some embodiments of the present application, reference Figure 7The first control module 811 is further configured to receive and respond to the warp emission enable signal to continuously emit the to-be-emitted instructions in the warp, or to suspend the emission of the to-be-emitted instructions in the warp.

[0125] In an embodiment of the present application, the emission enable signal is used to control whether instructions in the thread bundle can be emitted; if the emission enable signal is turned on, the thread bundle is in an enabled state, and the instructions in the thread bundle can be emitted; if the emission enable signal is turned off, the thread bundle is in a disabled state, and the instructions in the thread bundle are suspended from being emitted.

[0126] For example, if the program is set to wait for 5 seconds to Sleep, during these 5 seconds, the emission enable signal is turned off, and the instructions in the thread bundle are temporarily no longer emitted; when the required 5 seconds of waiting are reached, the emission enable signal is turned on, and the instruction sequence in the thread bundle can enter the selectable emission state again.

[0127] It should be noted that the emission enable signal of the thread warp is used to control whether the current thread warp can continue to emit instructions. When the thread warp itself does not depend on cycle waiting or data-dependent waiting, but depends on other factors to suspend emission, the emission enable signal can be used to control the thread warp to be in a disabled state. In other cases, as long as the thread warp is valid, the thread warp is always in an enabled state.

[0128] However, when a jump instruction is issued, it is not known how to jump next before the execution is completed. In this case, the emission enable signal needs to be turned off. In addition, when a Mutex instruction is issued to obtain a mutex semaphore, if it is not obtained, the emission enable signal also needs to be turned off, and subsequent instructions cannot be issued. Other related instructions include the sleep instruction Sleep, the synchronous wait instruction, the overlap safety check instruction, and the wait output buffer completion instruction.

[0129] It is understandable that by transmitting an enable signal to control the state of the thread warp, instruction transmission can be suspended in a timely manner as needed to avoid errors in instruction execution.

[0130] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the device provided in the embodiment of the present application can be used to execute the method described in the above method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0131] It should be noted that in the embodiment of the present application, if the above-mentioned instruction processing method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific hardware, software or firmware, or any combination of hardware, software, and firmware.

[0132] An embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0133] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented. The computer-readable storage medium can be transient or non-transient.

[0134] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0135] The embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, some or all of the steps in the above method are implemented. The computer program product can be implemented specifically by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0136] It should be noted here that the description of the various embodiments above tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. The description of the above device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the embodiments of the device, storage medium, computer program and computer program product of this application, please refer to the description of the method embodiment of this application for understanding.

[0137] Fig.10 A hardware entity diagram of a computer device provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the hardware entity of the computer device 1100 includes: a processor 1101 and a memory 1102, wherein the memory 1102 stores a computer program that can be run on the processor 1101, and the processor 1101 implements the steps in the method of any of the above embodiments when executing the program.

[0138] The memory 1102 stores computer programs that can be run on the processor. The memory 1102 is configured to store instructions and applications executable by the processor 1101. It can also cache data to be processed or processed by the processor 1101 and various modules in the computer device 1100 (for example, image data, audio data, voice communication data, and video communication data). This can be achieved through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0139] When the processor 1101 executes the program, the steps of any of the above instruction processing methods are implemented. The processor 1101 generally controls the overall operation of the computer device 1100.

[0140] An embodiment of the present application provides a computer storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the instruction processing method of any of the above embodiments.

[0141] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0142] The processor may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understandable that the electronic device that implements the functions of the processor may also be other, and the embodiments of the present application are not specifically limited.

[0143] The above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and the like; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0144] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0145] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0146] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0147] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0148] In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by hardware related to program instructions, and the above program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above method embodiments are executed; and the above storage medium includes: mobile storage devices, read-only memory (ROM), disks or optical disks, etc. Various media that can store program codes.

[0149] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0150] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A command processing method, characterized in that: The instruction processing method comprises: Obtaining a type ratio value of an instruction sequence; wherein each type ratio value represents a proportion of a corresponding type of instruction in the instruction sequence; Determine, based on the type ratio, a transmission path adopted by the instruction of each type; The to-be-issued instructions in the instruction sequence are issued to the corresponding pipeline execution unit via the corresponding issuing path.

2. The instruction processing method according to claim 1, characterized in that: Determining the emission path adopted by the instruction of each type based on the type ratio value includes: At least two types of instructions whose type proportions satisfy a merging condition are determined to use the same transmission path.

3. The instruction processing method according to claim 2, characterized in that: Determining at least two types of instructions whose type proportions satisfy a merging condition to use the same transmission path includes: If the type ratio of the first instruction is lower than a threshold, the first instruction and the instructions of other types are determined to use the same transmission path; and / or, If the type ratio values ​​of the second instruction and the third instruction are both higher than a threshold, and the second instruction and the third instruction are not the highest instructions, the second instruction and the third instruction are determined to use the same issuance path; wherein the type ratio value of the highest instruction is the highest.

4. The instruction processing method according to claim 1, characterized in that: Obtaining the type ratio value of the instruction sequence includes: After the instruction sequence is compiled, counting the number of occurrences of each type of instruction in the instruction sequence; Based on the number of occurrences of the instructions of each type, the type proportion value is calculated.

5. The instruction processing method according to claim 1, characterized in that: Obtaining the type proportion value of the instruction sequence further includes: Based on historical data, the type ratio of the instruction sequence is determined.

6. The instruction processing method according to claim 1, characterized in that: The instruction to be issued is issued to the corresponding pipeline execution unit, including: Acquire pre-decoding information of the instruction to be transmitted; the pre-decoding information includes: a waiting cycle; the waiting cycle represents the number of cycles that the instruction to be transmitted needs to wait before being transmitted; When the to-be-issued instruction reaches the corresponding waiting period, the to-be-issued instruction is emitted.

7. The instruction processing method according to claim 6, characterized in that: The waiting period of the instruction to be issued is set based on the data dependency of the instruction to be issued; The instruction to be issued is not provided with preparation information, wherein the preparation information indicates whether data dependency is released.

8. An instruction processing device, characterized in that: The instruction processing device includes: a thread controller, a plurality of issue paths and a plurality of pipeline execution units; Wherein, the first ends of the plurality of emission paths are electrically connected to the thread controller; each of the pipeline execution units is electrically connected to the second end of at least one corresponding emission path; the thread controller is electrically connected to the thread bundle; The thread controller comprises: a first control module; The first control module is configured to obtain a type ratio value of an instruction sequence; and, based on the type ratio value, determine the emission path adopted by each type of the instruction; and, emit the to-be-emitted instructions in the instruction sequence from the thread bundle to the corresponding pipeline execution unit via the corresponding emission path; wherein each type ratio value represents the proportion of a corresponding type of instruction in the instruction sequence.

9. The instruction processing device according to claim 8, characterized in that: The thread controller further includes: a second control module; The second control module is configured to retrieve the instruction from the instruction cache to the thread warp; and decode the retrieved instruction.

10. The instruction processing device according to claim 8, characterized in that: Each of the transmission paths is provided with a configuration register; The first control module is also configured to configure type information for the instruction to be issued based on the type ratio value; and compare the type information with the information of the configuration register of each of the emission paths, and if the comparison result is a match, store the instruction to be issued in the corresponding configuration register.

11. The instruction processing device according to claim 8, characterized in that: The first control module is further configured to determine that at least two types of instructions whose type proportions meet a merging condition adopt the same transmission path.

12. The instruction processing device according to claim 11, characterized in that: The first control module is further configured to, if the type ratio value of the first instruction is lower than a threshold value, determine the first instruction and other types of instructions to use the same transmission path; and / or, if the type ratio values ​​of the second instruction and the third instruction are both higher than a threshold value, and the second instruction and the third instruction are not the highest instructions, determine the second instruction and the third instruction to use the same transmission path; wherein the type ratio value of the highest instruction is the highest.

13. The instruction processing device according to claim 8, characterized in that: The first control module is further configured to obtain pre-decoding information of the instruction to be transmitted; The pre-decoding information includes: a waiting period; and, when the instruction to be issued reaches the corresponding waiting period, issuing the instruction to be issued.

14. The instruction processing device according to claim 8, characterized in that: The first control module is further configured to receive and respond to a warp emission enable signal to continuously emit the to-be-emitted instructions in the warp, or to suspend the emission of the to-be-emitted instructions in the warp.

15. A computer program product, characterized in that The invention comprises a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the steps in the method according to any one of claims 1 to 7.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 7 are implemented.

17. A computer device, characterized in that: The invention comprises the instruction processing device as claimed in any one of claims 8 to 14.

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