Semiconductor structure and manufacturing method thereof
By forming a side wall structure with a protective layer and a multi-layer stacked structure on the side wall of the gate structure during semiconductor manufacturing, the problem of the gate structure being corroded during the formation of the side wall structure is solved, and the uniformity of the gate contact layer is achieved The performance and high quality improve the performance and yield of semiconductor structures.
Patent Information
- Application Number
- CN202411410028.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-02-11
AI Technical Summary
During semiconductor manufacturing, the gate structure is easily corroded during the formation of the side wall structure, resulting in uneven thickness of the gate contact layer in subsequent processes.
The side wall structure is formed by forming a protective layer on the side wall of the gate structure and constructing a multi-layer stack structure thereon, including an insulating layer, a barrier layer and a top cover layer. This side wall structure not only protects the gate structure, but also ensures the accuracy and uniformity of subsequent doping regions.
It effectively avoids corrosion of the gate structure in the subsequent process, ensures uniformity and high quality of the gate contact layer, and improves the performance and yield of the semiconductor structure.
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Figure CN119419119A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] In semiconductor manufacturing, the main function of the sidewall structure is to form a low-concentration lightly doped drain (LDD) region to prevent hot carrier effects. In the 0.18um-55nm process, the sidewall structure is generally an ONO structure, and its formation process is generally as follows: the first layer is formed by thermal oxidation to form silicon dioxide as an etch stop layer, the middle layer is deposited by a furnace tube method with a thin layer of silicon nitride, and then a layer of silicon dioxide formed by decomposition of tetraethoxysilane is deposited by a furnace tube method, so that the outer silicon dioxide layer is etched first, the silicon nitride layer is used as an etch stop layer, and then the silicon dioxide layer of the first layer is used as an etch stop layer to etch the silicon nitride layer, so as to obtain a semiconductor structure including a sidewall structure, and as Figure 1 As shown, it is a schematic diagram of the structure of a semiconductor structure, including a substrate 01, a well region 011, a gate structure 02, a gate dielectric layer 021, a gate layer 022, a sidewall structure 03, an insulating layer 031, a barrier layer 032, a top covering layer 033, a first doped region 04, a second doped region 05 and a gate contact layer 06. However, in this formation process, during the subsequent wet etching process, the top sides of the gate structure will be partially etched away due to the bare leakage, resulting in the gate contact layer thickness being thickened when measured at the top of the gate structure during the subsequent formation of the gate contact layer, and the quality is uneven.
[0003] In view of this, there is an urgent need for a method for forming a semiconductor structure that can protect the gate structure from being corroded during the process of forming the spacer structure. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem in the prior art that the gate structure is easily corroded during the formation of the sidewall structure.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0006] Providing a first conductive type substrate, forming a first conductive type well region on the upper surface of the substrate, and forming a gate structure on the upper surface of the well region, wherein the gate structure includes a gate dielectric layer and a gate layer stacked in sequence;
[0007] A protective layer covering the sidewall of the gate structure and a stacked structure covering the sidewall of the gate structure away from the protective layer are formed on the upper surface of the well region, wherein the stacked structure comprises an insulating layer, a barrier layer and a top covering layer stacked in sequence, and one end of the stacked structure located on the upper surface of the well region is spaced from the gate structure by a preset distance, and the stacked structure and the protective layer constitute a sidewall structure;
[0008] A first doping region of the second conductivity type and a second doping region of the second conductivity type adjacent to the first doping region are formed on the upper surface layer of the well region on both sides of the gate structure, wherein the bottom surface of the first doping region is higher than the bottom surface of the second doping region and the doping concentration of the second doping region is greater than the doping concentration of the first doping region;
[0009] A gate contact layer is formed on the upper surface of the gate layer.
[0010] Optionally, forming the protective layer includes the following steps: forming a protective material layer covering the exposed surface of the gate structure and the upper surface of the well region, and removing the protective material layer located on the upper surface of the gate structure and the upper surface of the well region to obtain the protective layer covering the side wall of the gate structure.
[0011] Optionally, the protective material layer is made of silicon nitride.
[0012] Optionally, a method of forming the protective material layer includes chemical vapor deposition and atomic layer deposition.
[0013] Optionally, the thickness of the protective layer is in the range of
[0014] Optionally, forming the stacked structure includes the following steps: forming an insulating material layer, a blocking material layer and a top covering material layer stacked in sequence on the gate structure, the exposed surface of the protective layer and the upper surface of the substrate, and removing portions of the top covering material layer, the blocking material layer and the insulating material layer located above the gate structure and above the substrate in sequence to obtain the stacked structure covering the side walls of the protective layer away from the gate structure.
[0015] Optionally, the insulating layer is made of silicon dioxide; the barrier layer is made of silicon nitride; and the top covering layer is made of silicon dioxide.
[0016] Optionally, forming the gate contact layer includes the following steps: forming a metal layer on the upper surface of the gate layer and performing rapid annealing treatment so that the metal layer reacts with the upper surface material of the gate layer to form a gate contact layer, and removing the unreacted metal layer located on the upper surface of the gate layer.
[0017] Optionally, the material of the metal layer includes nickel.
[0018] The present invention further provides a semiconductor structure, wherein the semiconductor structure is manufactured by using any one of the above-mentioned methods for manufacturing a semiconductor structure.
[0019] As described above, the semiconductor structure and the manufacturing method thereof of the present invention have the following beneficial effects: by forming the sidewall structure including the protective layer and the stacked structure, and the stacked structure includes the insulating layer, the barrier layer and the top covering layer, that is, setting the sidewall structure as a multi-layer stacked structure, the accuracy of the first doping region and the second doping region formed subsequently is ensured, and the sidewall structure as a multi-layer stacked structure helps to reduce the device degradation caused by various stresses in the manufacturing process and improve the long-term reliability of the device, and can also achieve higher integration to adapt to different manufacturing processes and equipment requirements, and by forming the protective layer covering the sidewall of the gate structure in the sidewall structure, the gate layer and the insulating layer and the barrier layer in the stacked structure are avoided from being corroded in the subsequent process, thereby ensuring the uniformity of the formed gate contact layer and improving the performance and yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic structural diagram of a semiconductor structure in the prior art of the present invention.
[0021] Figure 2 It is a schematic diagram of the manufacturing process of the semiconductor structure of the present invention.
[0022] Figure 3 It is a schematic structural diagram of the method for manufacturing the semiconductor structure of the present invention after forming a gate structure.
[0023] Figure 4 It is a schematic diagram showing the structure after forming a protective material layer in the method for manufacturing a semiconductor structure of the present invention.
[0024] Figure 5 It is a schematic structural diagram showing the manufacturing process of the semiconductor structure of the present invention after forming a stacked structure.
[0025] Figure 6 It is a schematic diagram showing the structure after forming the first doping region and the second doping region in the manufacturing process of the semiconductor structure of the present invention.
[0026] Figure 7 It is a schematic structural diagram of the semiconductor structure of the present invention after forming a gate contact layer.
[0027] Component number description
[0028] 01 Substrate
[0029] 011 Well region
[0030] 02 Gate structure
[0031] 021 Gate dielectric layer
[0032] 022 Gate layer
[0033] 03 Side wall structure
[0034] 031 Insulation layer
[0035] 032 Barrier layer
[0036] 033 Top Cover
[0037] 04 The first doping region
[0038] 05 Second doping region
[0039] 06 Gate contact layer
[0040] 1 Substrate
[0041] 11 Well region
[0042] 2 Gate structure
[0043] 21. Gate dielectric layer
[0044] 22 Gate layer
[0045] 3 Side wall structure
[0046] 31 Protective layer
[0047] 32 Laminated structure
[0048] 321 Insulation layer
[0049] 322 Barrier layer
[0050] 323 Top Cover
[0051] 4. First doping region
[0052] 5 Second doping region
[0053] 6 Gate contact layer DETAILED DESCRIPTION
[0054] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0055] See also Figures 2 to 7. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.
[0056] Embodiment 1
[0057] This embodiment provides a method for manufacturing a semiconductor structure. Figure 2 FIG. 1 is a schematic diagram of a semiconductor structure manufacturing process, which includes the following steps:
[0058] S1: providing a first conductive type substrate, forming a first conductive type well region on the upper surface of the substrate, and forming a gate structure on the upper surface of the well region, wherein the gate structure includes a gate dielectric layer and a gate layer stacked in sequence;
[0059] S2: forming a protective layer covering the sidewall of the gate structure and a stacked structure covering the protective layer away from the sidewall of the gate structure on the upper surface of the well region, wherein the stacked structure comprises an insulating layer, a barrier layer and a top covering layer stacked in sequence, and one end of the stacked structure located on the upper surface of the well region is spaced from the gate structure by a preset distance, and the stacked structure and the protective layer constitute a sidewall structure;
[0060] S3: forming a first doping region of the second conductivity type and a second doping region of the second conductivity type adjacent to the first doping region on the upper surface layer of the well region on both sides of the gate structure, wherein the bottom surface of the first doping region is higher than the bottom surface of the second doping region and the doping concentration of the second doping region is greater than the doping concentration of the first doping region;
[0061] S4: forming a gate contact layer on the upper surface of the gate layer.
[0062] For details, please refer to Figure 3 , perform step S1, provide a first conductive type substrate 1, form a first conductive type well region 11 on the surface of the substrate 1, and form a gate structure 2 on the upper surface of the well region 11, the gate structure 2 includes a gate dielectric layer 21 and a gate layer 22 stacked in sequence.
[0063] Specifically, the first conductive type includes one of N type and P type, the second conductive type includes one of N type and P type, and the first conductive type is opposite to the second conductive type.
[0064] Specifically, the material of the substrate 1 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable semiconductor materials.
[0065] Specifically, while ensuring the performance of the semiconductor structure, the shape and size of the substrate 1 can be selected according to actual conditions and are not limited here.
[0066] Specifically, the method of forming the well region 11 includes ion implantation or other suitable methods.
[0067] Specifically, while ensuring the performance of the semiconductor structure, the shape and size of the well region 11 can be selected according to actual conditions and are not limited here.
[0068] Specifically, Figure 3 , which is a schematic diagram of the structure after the gate structure 2 is formed, and the gate structure 2 includes a gate dielectric layer 21 and a gate layer 22 stacked in sequence.
[0069] Specifically, the material of the gate dielectric layer 21 includes silicon dioxide, high-K material or other suitable dielectric materials. In this embodiment, the material of the gate dielectric layer 21 is polysilicon.
[0070] Specifically, the method of forming the gate dielectric layer 21 includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods.
[0071] Specifically, under the condition that the performance of the semiconductor structure is met, the thickness of the gate dielectric layer 21 can be adjusted according to actual conditions and is not limited here.
[0072] Specifically, the material of the gate layer 22 includes polysilicon, metal material or other suitable conductive materials. In this embodiment, the material of the gate layer 22 is polysilicon.
[0073] Specifically, the method of forming the gate layer 22 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0074] For details, please refer to Figures 4 to 5 , execute step S2, and form a protection layer 31 covering the side wall of the gate structure 2 and a stacked structure 32 covering the side wall of the protection layer 31 away from the gate structure 2 on the upper surface of the well region 11, the stacked structure 32 includes an insulating layer 321, a barrier layer 322 and a top covering layer 323 stacked in sequence, and the stacked structure 32 is located at one end of the upper surface of the well region 11 and is spaced a preset distance from the gate structure 2, and the stacked structure 32 and the protection layer 31 constitute a sidewall structure 3.
[0075] As an example, forming the protective layer 31 includes the following steps: forming a protective material layer 311 covering the exposed surface of the gate structure 2 and the upper surface of the well region 11, and removing the protective material layer 311 located on the upper surface of the gate structure 2 and the upper surface of the well region 11 to obtain a protective layer 31 covering the side wall of the gate structure 2.
[0076] As an example, the material of the protection material layer 31 includes silicon nitride or other suitable materials.
[0077] As an example, Figure 4 , which is a schematic diagram of the structure after forming the protective material layer 311 , the method of forming the protective material layer 311 includes chemical vapor deposition, atomic layer deposition or other suitable methods.
[0078] Specifically, the method for removing the protective material layer 311 located on the upper surface of the gate structure 2 and the upper surface of the well region 11 includes dry etching, wet etching or other suitable methods. In this embodiment, the method for removing the protective material layer 311 is dry etching.
[0079] As an example, the thickness of the protective layer 31 ranges from In this embodiment, the thickness of the protective layer 31 is
[0080] Specifically, the thickness of the protective layer 31 formed by setting is That is, by setting the thickness of the formed protection layer 31 to be thinner and setting the material of the gate layer 22 to be polysilicon, the stress problem of the formed protection layer 31 is reduced to reduce the influence on the performance of the semiconductor structure. It should be noted that, in order to avoid the stress problem of the formed protection layer 31 made of silicon nitride, before forming the protection layer 31, an oxide layer can be formed on the side wall of the gate layer 22 by thermal oxidation to avoid the stress problem of the protection layer 31.
[0081] Specifically, by forming a protection layer 31 covering the sidewalls of the gate structure 2, the gate layer 22 and the insulating layer 321 and the top of the barrier layer 322 in the stacked structure 32 are prevented from being corroded during the subsequent formation of the stacked structure 32, thereby improving the performance and yield of the semiconductor structure.
[0082] As an example, Figure 5 As shown, it is a schematic diagram of the structure after the stacked structure 32 is formed. The formation of the stacked structure 32 includes the following steps: forming an insulating material layer (not shown), a blocking material layer (not shown) and a top covering material layer (not shown) stacked in sequence on the gate structure 2, the exposed surface of the protective layer 31 and the upper surface of the substrate 1, and removing part of the top covering material layer, the blocking material layer and the insulating material layer located above the gate structure 2 and above the substrate 1 in sequence to obtain the stacked structure 32 covering the side wall of the protective layer 31 away from the gate structure 2.
[0083] Specifically, the method of sequentially removing the portion of the top covering material layer, the barrier material layer, and the insulating material layer located above the gate structure 2 and the substrate 1 includes wet etching, dry etching, or other suitable methods. In this embodiment, the method of removing the portion of the top covering material layer, the barrier material layer, and the insulating material layer located above the gate structure 2 and the substrate 1 is dry etching.
[0084] Specifically, when dry etching is used to sequentially remove the insulating material layer, the barrier material layer and the top covering material layer located on the upper surface of the gate structure 2 and part of the upper surface of the substrate 1, the protective layer 31 serves as an etch stop layer for the insulating material layer, the insulating layer 321 serves as an etch stop layer for the barrier material layer, and the barrier layer 322 serves as an etch stop layer for the top covering material layer.
[0085] Specifically, the insulating layer 321 covers the sidewalls of the protection layer 31 away from the gate structure 2 and located on the upper surface of the substrate 1 , the barrier layer 322 covers the sidewalls and upper surface of the insulating layer 321 , and the top covering layer 323 covers the sidewalls and upper surface of the barrier layer 322 .
[0086] Specifically, the method of forming the insulating material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0087] Specifically, the material of the insulating layer 321 includes silicon dioxide or other suitable insulating materials.
[0088] Specifically, the shape of the insulating layer 321 includes an L-shape or other suitable shapes.
[0089] Specifically, under the condition that the performance of the semiconductor structure is met, the thickness of the insulating layer 321 can be adjusted according to actual conditions and is not limited here.
[0090] Specifically, the insulating layer 321 is used to provide good adhesion and insulation performance between the sidewall structure 3 and the substrate 1 .
[0091] Specifically, the method of forming the barrier material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0092] Specifically, the material of the blocking layer 322 includes silicon nitride or other suitable insulating materials.
[0093] Specifically, the shape of the barrier layer 322 includes an L-shape or other suitable shapes.
[0094] Specifically, under the condition that the performance of the semiconductor structure is met, the thickness of the barrier layer 322 can be selected according to actual conditions and is not limited here.
[0095] Specifically, the barrier layer 322 has high thermal stability and good chemical stability, can remain stable in subsequent high-temperature processes, and prevent ions from being injected deep into the gate layer 22 during the formation of the first doping region 4 and the second doping region 5, thereby reducing parasitic capacitance and improving the switching speed of the device.
[0096] Specifically, the method of forming the top covering material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0097] Specifically, the material of the top cover layer 323 includes silicon dioxide or other suitable insulating materials.
[0098] Specifically, the sidewall of the top cover layer 323 is arranged in an arc shape.
[0099] Specifically, under the condition that the performance of the semiconductor structure is met, the thickness of the top cover layer 323 can be selected according to actual conditions and is not limited here.
[0100] Specifically, the top cover layer 323 can provide additional protection and insulation performance, and help control the stress of the barrier layer 322 to prevent the performance of the semiconductor structure from being affected due to excessive stress.
[0101] It should be noted that the stacked structure 32 is not limited to the above-mentioned stacked structure. When the performance of the semiconductor structure is met, the stacked structure 32 can be a stacked structure with more layers.
[0102] Specifically, by forming a sidewall structure 3 including a protective layer 31, an insulating layer 32, a barrier layer 33 and a top covering layer 34, that is, by setting the sidewall structure 3 as a multi-layer stacked structure, the accuracy of the first doping region 4 and the second doping region 5 formed subsequently is ensured, and the sidewall structure 3 as a multi-layer stacked structure helps to reduce device degradation caused by various stresses in the manufacturing process and improve the long-term reliability of the device. It can also adapt to different manufacturing processes and equipment requirements to achieve higher integration.
[0103] For details, please refer to Figure 6 , execute step S3 to form a first doping region 4 of the second conductivity type and a second doping region 5 of the second conductivity type on the upper surface of the well region 11, the second doping region 5 penetrates the first doping region 4 and the bottom surface of the first doping region 4 is higher than the bottom surface of the second doping region 5, the first doping region 4 is located below the sidewall structure 3, and the doping concentration of the second doping region 5 is greater than the doping concentration of the first doping region.
[0104] Specifically, Figure 6As shown, it is a schematic diagram of the structure after forming the first doping region 4 and the second doping region 5. The method of forming the first doping region 4 includes ion implantation or other suitable methods; the method of forming the second doping region 5 includes ion implantation or other suitable methods.
[0105] Specifically, the injection energy when forming the first doping region 4 by ion implantation can be selected according to actual conditions and is not limited here; the injection energy when forming the second doping region 5 by ion implantation can be selected according to actual conditions and is not limited here.
[0106] Specifically, the first doped region 4 can optimize the electrical characteristics of the semiconductor structure and improve reliability, which is helpful to realize high-performance integrated circuits.
[0107] Specifically, the first doping region 4 extends away from the sidewall of the second doping region 5 to below the gate structure 2 .
[0108] Specifically, an isolation structure (not shown) is also formed in the semiconductor structure. The isolation structure is located in the substrate 1 and is adjacent to the second doping region 5 .
[0109] For details, please refer to Figure 7 , executing step S4 to form a gate contact layer 6 on the surface of the gate layer 22 .
[0110] Specifically, Figure 7 As shown, it is a schematic diagram of the structure after the gate contact layer 6 is formed. The formation of the gate contact layer 6 includes the following steps: forming a metal layer (not shown) on the upper surface of the gate layer 22 and performing a rapid annealing treatment to allow the metal layer to react with the surface material of the gate layer 22 to form the gate contact layer 6, and removing the metal layer located on the upper surface of the gate layer 22 that does not participate in the reaction.
[0111] Specifically, the upper surface of the gate contact layer 6 is flush with the upper surface of the spacer structure 3 .
[0112] Specifically, the material of the metal layer includes nickel or other suitable metal materials.
[0113] As an example, the material of the gate contact layer 6 includes metal silicide. In this embodiment, the material of the gate contact layer 6 is nickel silicide.
[0114] Specifically, the gate contact layer 6 helps to reduce the resistance of the gate structure 2 and improve the device performance, and the protective layer 31 formed in the sidewall structure 3 and covering the sidewall of the gate structure 2 avoids the loss of the gate layer 22 and the insulating layer 321 and the barrier layer 322 in the stacked structure 32, ensures the uniformity of the formed gate contact layer 6, and improves the performance of the semiconductor structure.
[0115] The method for forming a semiconductor structure of the present embodiment forms a protective layer covering the side wall of the gate structure 2 in the sidewall structure 3, thereby avoiding the loss of the gate layer 22 and the insulating layer 321 and the barrier layer 322 in the stacked structure 32 during the subsequent formation of the stacked structure 32, ensuring the uniformity of the formed gate contact layer 6, and further improving the performance and yield of the semiconductor structure; by forming a sidewall structure 3 including a stacked structure 32 and a protective layer 31, and the stacked structure 32 includes an insulating layer 321, a barrier layer 322 and a top covering layer 323, that is, by setting the sidewall structure 3 as a multi-layer stacked structure, the accuracy of the first doping region 4 and the second doping region 5 formed subsequently is ensured, and the sidewall structure 3 as a multi-layer stacked structure helps to reduce the device degradation caused by various stresses in the manufacturing process and improve the long-term reliability of the device, and can also achieve a higher degree of integration to adapt to different manufacturing processes and equipment requirements.
[0116] Embodiment 2
[0117] The present embodiment provides a semiconductor structure, which is manufactured by the manufacturing method of the semiconductor structure described in the first embodiment. The semiconductor structure includes: a first conductive type substrate 1, a gate structure 2, a sidewall structure 3, a second conductive type first doping region 4, a second conductive type second doping region 5 and a gate contact layer 6, wherein a well region 11 is formed on the upper surface of the substrate 1, the gate structure 2 is located on the upper surface of the well region 11, and the gate structure 2 includes a gate dielectric layer 21 and a gate layer 22 stacked in sequence; the sidewall structure 3 is located on the upper surface of the well region 11, and the sidewall structure 3 includes a stacked structure 32 and a protective layer 31. The protective layer 31 covers the side wall of the gate structure 2, and the stacked structure 32 covers the side wall of the protective layer 31 away from the gate structure 2. The stacked structure 32 includes an insulating layer 321, a barrier layer 322 and a top covering layer 323 stacked in sequence, and one end of the stacked structure is located on the upper surface of the well region 11 and is separated from the gate structure 2 by a preset distance; the first doping region 4 and the second doping region 5 are located in the upper surface layer of the well region 1 on both sides of the gate structure 2, the bottom surface of the first doping region 4 is higher than the bottom surface of the second doping region 5 and the doping concentration of the second doping region 5 is greater than the doping concentration of the first doping region 4; the gate contact layer 6 is located on the upper surface layer of the gate structure 2.
[0118] Specifically, the semiconductor structure further includes an isolation structure, which is located in the substrate 1 and adjacent to the second doping region 5 .
[0119] The semiconductor structure of the present embodiment includes a stacked structure 32 and a protective layer 31 by setting a sidewall structure 3, and the stacked structure 32 includes an insulating layer 321, a barrier layer 322 and a top covering layer 323, that is, by setting the sidewall structure 3 as a multi-layer stacked structure, the accuracy of the first doping region 4 and the second doping region 5 formed subsequently is guaranteed, and the sidewall structure 3 as a multi-layer stacked structure helps to reduce the device degradation caused by various stresses in the manufacturing process and improve the long-term reliability of the device, and can also achieve a higher degree of integration to adapt to different manufacturing processes and equipment requirements; by setting a protective layer covering the side wall of the gate structure 2 in the sidewall structure 3, in the process of subsequently forming the stacked structure 32, the loss of the gate layer 22 and the insulating layer 321 and the barrier layer 322 in the stacked structure 32 is avoided, and the uniformity of the formed gate contact layer 6 is guaranteed, thereby improving the performance and yield of the semiconductor structure.
[0120] In summary, the semiconductor structure and its manufacturing method of the present invention form a sidewall structure including a protective layer and a stacked structure, and the stacked structure includes an insulating layer, a barrier layer and a top covering layer, that is, the sidewall structure is set as a multi-layer stacked structure, which ensures the accuracy of the first doping region and the second doping region formed subsequently, and the sidewall structure of the multi-layer stacked structure helps to reduce the device degradation caused by various stresses in the manufacturing process and improve the long-term reliability of the device, and can also achieve a higher degree of integration to adapt to different manufacturing processes and equipment requirements, and by forming a protective layer covering the sidewall of the gate structure in the sidewall structure, in the subsequent process of forming the insulating layer, the barrier layer and the top covering layer, the top of the gate layer is avoided from being corroded and the insulating layer and the barrier layer in the stacked structure, ensuring the uniformity of the formed gate contact layer, thereby improving the performance and yield of the semiconductor structure. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0121] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a first conductive type substrate, forming a first conductive type well region on the upper surface of the substrate, and forming a gate structure on the upper surface of the well region, wherein the gate structure includes a gate dielectric layer and a gate layer stacked in sequence; A protective layer covering the sidewall of the gate structure and a stacked structure covering the sidewall of the gate structure away from the protective layer are formed on the upper surface of the well region, wherein the stacked structure comprises an insulating layer, a barrier layer and a top covering layer stacked in sequence, and one end of the stacked structure located on the upper surface of the well region is spaced from the gate structure by a preset distance, and the stacked structure and the protective layer constitute a sidewall structure; A first doping region of the second conductivity type and a second doping region of the second conductivity type adjacent to the first doping region are formed on the upper surface layer of the well region on both sides of the gate structure, wherein the bottom surface of the first doping region is higher than the bottom surface of the second doping region and the doping concentration of the second doping region is greater than the doping concentration of the first doping region; A gate contact layer is formed on the upper surface of the gate layer.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming the protective layer includes the following steps: forming a protective material layer covering the exposed surface of the gate structure and the upper surface of the well region, and removing the protective material layer located on the upper surface of the gate structure and the upper surface of the well region to obtain the protective layer covering the side wall of the gate structure.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material of the protective material layer includes silicon nitride.
4. The method for manufacturing a semiconductor structure according to claim 2, wherein: Methods for forming the protective material layer include chemical vapor deposition and atomic layer deposition.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The thickness of the protective layer is in the range of 6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The formation of the stacked structure includes the following steps: forming an insulating material layer, a barrier material layer and a top covering material layer stacked in sequence on the gate structure, the exposed surface of the protective layer and the upper surface of the substrate, and removing the portions of the top covering material layer, the barrier material layer and the insulating material layer located above the gate structure and above the substrate in sequence to obtain the stacked structure covering the side wall of the protective layer away from the gate structure.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the insulating layer includes silicon dioxide; the material of the blocking layer includes silicon nitride; and the material of the top covering layer includes silicon dioxide.
8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming the gate contact layer includes the following steps: forming a metal layer on the upper surface of the gate layer and performing a rapid annealing process so that the metal layer reacts with the upper surface material of the gate layer to form a gate contact layer, and removing the unreacted metal layer located on the upper surface of the gate layer.
9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The material of the metal layer includes nickel.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by using the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.