Method for forming interlayer dielectric layer
By forming a first side wall structure between the gate structures and protecting the first dielectric layer during etching, the problem of poor dielectric layer filling effect in the prior art is solved, and efficient dielectric layer filling and depth reduction are achieved The effect of aspect ratio.
Patent Information
- Application Number
- CN202411423542.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-02-11
AI Technical Summary
When filling the dielectric layer between gate structures, the filling effect is poor or the filling efficiency is low, resulting in difficulty in reducing the depth-to-face ratio, which affects the subsequent deposition process.
After forming the first dielectric layer, a first dielectric layer covering the height of the side wall part of the gate structure is formed, and the first dielectric layer on the top of the gate structure is exposed, and the combined The first side wall structure protects the first dielectric layer at the bottom of the first gap to expand the opening width of the dielectric layer without increasing the gap depth.
Without increasing the gap depth, the opening width of the dielectric layer is expanded, the depth-to-width ratio of the filling dielectric layer is reduced, and the filling effect and filling efficiency of the interlayer dielectric layer are improved.
Smart Images
Figure CN119419170A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming an interlayer dielectric layer. Background Art
[0002] As device sizes continue to shrink, the size (interval) between adjacent gate structures becomes smaller and smaller, and filling a dielectric layer (interlayer dielectric layer) between gate structures becomes a problem that cannot be ignored.
[0003] In the related art, a deposition-etch-dep (DED) method is usually used to fill a dielectric layer between gate structures. The dielectric layer on the top of the gate structure is removed by etching back after deposition, so that the aspect ratio between the gate structures is reduced, the process window during subsequent deposition is increased, and the dielectric layer filled between the gate structures is prevented from generating sealed (closed) voids (gaps).
[0004] However, the filling effect of the above-mentioned dielectric layer filling method is not ideal, so that the filling effect of the dielectric layer between the gate structures is poor or the filling efficiency is low. Summary of the invention
[0005] The object of the present invention is to provide a method for forming an interlayer dielectric layer, which is used to efficiently and simply improve the filling effect and filling efficiency of the dielectric layer between gate structures.
[0006] In order to solve the above technical problems, the present invention provides a method for forming an interlayer dielectric layer, comprising:
[0007] Providing a substrate, comprising a first region and a second region, wherein a gate structure and a stop layer covering the substrate surface and an outer wall of the gate structure are disposed on the first region and the second region, and the density of the gate structure in the first region is greater than the density of the gate structure in the second region;
[0008] Forming a first dielectric layer to conformally cover the substrate surface and the stop layer surface of the outer wall of the gate structure, and the first dielectric layer between the gate structures in the first region retains an open first gap;
[0009] Forming a first dielectric layer with a first spacer structure covering a portion of the height of the sidewall of the gate structure, exposing the first dielectric layer on the top of the gate structure, and at least partially merging the first spacer structure in the first gap;
[0010] Etching the exposed first dielectric layer to remove a portion of the thickness of the first dielectric layer;
[0011] The first sidewall structure is removed, and a second dielectric layer is formed to conformally cover the first dielectric layer and fill the gate structure, and the second dielectric layer and the first dielectric layer are used as an interlayer dielectric layer.
[0012] Optionally, the step of forming the first sidewall structure includes:
[0013] Forming a spacer material layer to conformally cover the surface of the first dielectric layer in the first region and the second region, and merging at least a portion of the spacer material layer in the first gap;
[0014] A first dry etching process is performed to remove the sidewall material layer above the substrate surface and the top of the gate structure, exposing the first dielectric layer on the top of the gate structure and above the substrate surface, and using the sidewall material layer covering the height of the sidewall portion of the gate structure as the first sidewall structure.
[0015] Optionally, when performing the first dry etching process, a ratio of an etching rate of the spacer material layer to an etching rate of the first dielectric layer is greater than 5:1.
[0016] Optionally, the gate structure includes a gate dielectric layer, a gate conductive layer, a second mask layer and a first mask layer stacked in sequence from bottom to top, and the sidewall of the gate structure is also provided with a second sidewall structure, and the top of the second sidewall structure is between the gate conductive layer and the first mask layer.
[0017] Optionally, after forming the first sidewall structure, a second dry etching process is performed using the first sidewall structure as a mask to etch the exposed first dielectric layer, remove a portion of the thickness of the first dielectric layer on the top of the gate structure and above the substrate surface, and expand the opening of the first gap.
[0018] Optionally, when performing the second dry etching process, a ratio of an etching rate of the first dielectric layer to an etching rate of the stop layer is greater than 5:1.
[0019] Optionally, the first sidewall structure in the first gap has a merging portion, and after performing the second dry etching process, the merging portion and the first dielectric layer around the merging portion are removed simultaneously.
[0020] Optionally, a material of the first dielectric layer and / or the second dielectric layer includes silicon oxide, and a material of the first sidewall structure includes silicon nitride.
[0021] Optionally, the distance between the centers of adjacent gate structures is the center distance, the ratio of the center distance of adjacent gate structures in the first region to the width of the gate structure in the first region is less than 3:1, and the ratio of the center distance of adjacent gate structures in the second region to the width of the gate structure in the second region is greater than or equal to 3:1.
[0022] Optional,
[0023] removing the first side wall structure;
[0024] The formed third dielectric layer conformally covers the surface of the first dielectric layer and forms a third gap in the second gap;
[0025] Forming a third dielectric layer with a third spacer structure covering a portion of the height of the sidewall of the gate structure, exposing the third dielectric layer at the top of the gate structure, and at least partially merging the third spacer structure in the third gap;
[0026] Etching the exposed third dielectric layer to remove a portion of the thickness of the third dielectric layer;
[0027] The third spacer structure is removed, and a second dielectric layer is formed to conformally cover the third dielectric layer and fill the gate structure, and the third dielectric layer, the second dielectric layer and the first dielectric layer are used as an interlayer dielectric layer.
[0028] In summary, the present invention provides a method for forming an interlayer dielectric layer. After forming a first dielectric layer, a first sidewall structure is formed to cover a portion of the height of the sidewall of the gate structure, exposing the first dielectric layer at the top of the gate structure, and the first sidewall structure in the first gap is at least partially merged, and when etching (etching back) the first dielectric layer, the first sidewall structure merged in the first gap is used to protect the first dielectric layer at the bottom of the first gap. The opening width (average width) of the first dielectric layer can be expanded without increasing the depth of the first gap, thereby effectively reducing the aspect ratio of the dielectric layer filled in the first area (the area with a higher density of the gate structure), thereby improving the filling effect and filling efficiency of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0030] Figure 1a A schematic diagram of depositing a dielectric layer between gate structures in the related art;
[0031] Figure 1b It is a schematic diagram after etching back the dielectric layer in the related art;
[0032] Figure 2 A flow chart of a method for forming an interlayer dielectric layer provided in accordance with an embodiment of the present invention;
[0033] Figure 3a to Figure 3g This is a schematic structural diagram corresponding to the corresponding steps of the method for forming an interlayer dielectric layer provided in this embodiment.
[0034] Figure 1a to Figure 1b Middle: 10'-substrate; 11'-gate structure; 12'-dielectric layer.
[0035] Figure 3a to Figure 3g In the figure: 10-substrate; AA-first region; BB-second region; CC-third region; 11-gate structure; 11a-gate dielectric layer; 11b-gate conductive layer; 11c-second mask layer; 11d-first mask layer; 12-second sidewall structure; 13-stop layer; 21-first dielectric layer; 22-first gap; 22a-bottleneck; 23a-sidewall material layer; 23b-merging part; 24-first sidewall structure; 25-second gap; 26-second dielectric layer; 27-interlayer dielectric layer. DETAILED DESCRIPTION
[0036] As described in the background technology, Figure 1a Schematic diagram of a dielectric layer deposited between gate structures in the related art. The dielectric layer 12' conformally covers the surface of the substrate 10' and the outer wall of the gate structure 11'. The dielectric layer 12' forms a gap between the gate structures 11'. Figure 1b It is a schematic diagram after the dielectric layer is etched back in the related art. The dielectric layer 12' on the top of the gate structure 11' is removed during the back etching, but the dielectric layer 12' at the bottom between the gate structures 11' is also at least partially removed during the back etching, that is, the opening width of the gap is expanded while the depth of the gap is also increased, so that the efficiency of reducing the aspect ratio of the filling dielectric layer 12' is low or the effect is not good.
[0037] Therefore, the present invention provides a method for forming an interlayer dielectric layer. After forming the first dielectric layer, a first sidewall structure is formed to cover the height of a portion of the sidewall of the gate structure, exposing the first dielectric layer at the top of the gate structure, and the first sidewall structure in the first gap is at least partially merged, and when etching (etching back) the first dielectric layer, the first sidewall structure merged in the first gap is used to protect the first dielectric layer at the bottom of the first gap. The opening width (average width) of the first dielectric layer can be expanded without increasing the depth of the first gap, thereby effectively reducing the aspect ratio of the dielectric layer filled in the first area (the area with a higher density of the gate structure), thereby improving the filling effect and filling efficiency of the interlayer dielectric layer.
[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0039] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in other ways (rotated 90 degrees or other orientations) and the spatial descriptors used here are interpreted accordingly. The purpose of the terms used here is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used here, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "including" is used to determine the existence of features, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used here, the term "and / or" includes any and all combinations of the relevant listed items.
[0040] This embodiment provides a method for forming an interlayer dielectric layer.
[0041] Figure 2 The present invention is a flow chart of a method for forming an interlayer dielectric layer provided in the present embodiment.
[0042] like Figure 2 As shown, the method for forming an interlayer dielectric layer provided in this embodiment includes:
[0043] S01: providing a substrate, comprising a first region and a second region, wherein a gate structure and a stop layer covering the substrate surface and an outer wall of the gate structure are disposed on the first region and the second region, and a density of the gate structure in the first region is greater than a density of the gate structure in the second region;
[0044] S02: forming a first dielectric layer to conformally cover the surface of the substrate and the surface of the stop layer of the outer wall of the gate structure, and the first dielectric layer between the gate structures in the first region retains an open first gap;
[0045] S03: forming a first spacer structure to cover the first dielectric layer at a height of a portion of the sidewall of the gate structure, exposing the first dielectric layer on the top of the gate structure, and at least partially merging the first spacer structure in the first gap;
[0046] S04: etching the exposed first dielectric layer to remove a portion of the thickness of the first dielectric layer;
[0047] S05: removing the first spacer structure, forming a second dielectric layer to conformally cover the first dielectric layer and fill the gate structure, and using the second dielectric layer and the first dielectric layer as an interlayer dielectric layer.
[0048] Figure 3a to Figure 3g The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for forming the interlayer dielectric layer provided in this embodiment. Figure 3a to Figure 3g The method for forming the interlayer dielectric layer is described in detail.
[0049] First, execute step S01, please refer to Figure 3a , providing a substrate 10, which includes a first area AA and a second area BB, wherein a gate structure 11 and a stop layer 13 covering the surface of the substrate 10 and the outer wall of the gate structure 11 are provided in the first area AA and the second area BB, and the density of the gate structure 11 in the first area AA is greater than the density of the gate structure 11 in the second area BB.
[0050] The substrate 10 may be any base material known in the art that is suitable for forming a power device, for example, it may be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).
[0051] A plurality of protruding gate structures 11 are provided on the substrate 10, and the plurality of gate structures 11 are arranged at intervals. The arrangement density of the gate structures 11 in different regions of the surface of the substrate 10 may be different, wherein the region where the gate structures 11 are arranged at a higher density is the first region AA, the region where the gate structures 11 are arranged at a lower density is the second region BB, and the third region CC may be a region where no gate structures 11 are arranged. In other words, the density of the gate structures 11 in the first region AA is greater than the density of the gate structures 11 in the second region BB. The arrangement density of the gate structures 11 may be determined, for example, by the ratio of the center distance between adjacent gate structures 11 to the width of the gate structures 11, and the center distance may be the distance between the centers of adjacent gate structures 11. In the present embodiment, the first region AA may be a dense region of the gate structures 11, for example, the ratio of the center distance between adjacent gate structures 11 in the first region AA to the width of the gate structures 11 in the first region AA is less than 3:1, and the second region BB may be a non-dense region of the gate structures 11, for example, the ratio of the center distance between adjacent gate structures 11 in the second region BB to the width of the gate structures 11 in the second region BB is greater than or equal to 3:1.
[0052] Specifically, the gate structure 11 may include a gate dielectric layer 11a, a gate conductive layer 11b, a second mask layer 11c and a first mask layer 11d stacked in sequence from bottom to top, and the sidewall of the gate structure 11 is further provided with a second spacer structure 12, the second spacer structure 12 covers a portion of the height of the sidewall of the gate structure 11, and its top (top surface) may be, for example, located on the sidewall of the second mask layer 11c or the first mask layer 11d. The material of the second spacer structure 12 may include nitride and oxide, for example, it may be a composite film layer composed of silicon nitride and silicon oxide, the material of the second mask layer 11c may be nitride (such as silicon nitride), and the material of the first mask layer 11d may be silicon oxide (such as silicon oxide). The stop layer 13 covers the surface of the substrate 10 (including the first area AA, the second area BB and the third area CC) and the outer wall of each gate structure 11. The material of the stop layer 13 may be, for example, nitride. The width (average width or the width of the narrower part in the middle) of the stop layer 13 between the gate structures 11 in the first area AA may be the initial width W0. Of course, in some examples, the gate structure 11 may also be a virtual gate.
[0053] In addition, in this embodiment, the width and height of the gate structure 11 of the first area AA and the second area BB are the same, and in other examples of this embodiment, the width and / or height of the gate structure 11 of the first area AA and the second area BB may also be different.
[0054] Next, execute step S02, please refer to Figure 3b A first dielectric layer 21 is formed to conformally cover the surface of the substrate 10 and the surface of the stop layer 13 on the outer wall of the gate structure 11, and the first dielectric layer 21 between the gate structures 11 in the first area AA retains an open first gap 22.
[0055] The material of the first dielectric layer 21 may be the same as the material of the interlayer dielectric layer to be formed between the gate structures 11, and may be formed by a vapor deposition process, such as an LPCVD process. During execution, the first dielectric layer 21 to be formed may be determined by the spacing between the gate structures 11 in the first region AA, so that the formed first dielectric layer 21 conformally covers the surfaces of the first to third regions CC and the stop layer 13 of the outer wall of the gate structure 11. Moreover, the first dielectric layer 21 is not sealed or merged between the gate structures 11 in the first region AA, but forms (retains) an open first gap 22, and the width of the first gap 22 may be W1, which is smaller than W0. In this embodiment, the average width (roughly average width) of the first gap 22 or the width of the narrower part in the middle represents the width of the first gap 22, so as to judge the influence of the width of the gap on the filling effect.
[0056] In addition, the formed first dielectric layer 21 may also be determined by the subsequent first spacer structure 24, that is, if the thickness of the formed first dielectric layer 21 is too small, W2 will be larger, which is not conducive to reducing the aspect ratio when filling the interlayer dielectric layer 27. If the thickness of the formed first dielectric layer 21 is too large, W2 will be smaller, which is not conducive to the subsequent formation of the first spacer structure 24. In this embodiment, taking the material of the first spacer structure 24 as silicon nitride as an example, the minimum thickness of the first spacer structure 24 with better quality can be, for example, 30 nanometers to 50 nanometers, and the width of the first gap 22 can be, for example, 80 nanometers to 120 nanometers.
[0057] Next, step S03 is performed to form the first dielectric layer 21 with the first spacer structure 24 covering the sidewall height of the gate structure 11 , exposing the first dielectric layer 21 at the top of the gate structure 11 , and at least partially merging the first spacer structure 24 in the first gap 22 .
[0058] Please refer to Figure 3c, forming a sidewall material layer 23a conformally covering the surface of the first area AA, the second area BB and the third area CC and the first dielectric layer 21 of the outer wall of the gate structure 11, and at least partially merging the sidewall material layer 23a in the first gap 22. The sidewall material layer 23a can be a sidewall material that is easy to achieve a high selectivity with the first dielectric layer 21 during etching and is easy to remove, such as nitride (such as silicon nitride) or nitride oxide (such as silicon oxynitride), and can be formed by a vapor deposition process, such as LPCVD or PECVD. During execution, the thickness of the sidewall material layer 23a can be determined according to the width of the first gap 22. If the thickness of the sidewall material layer 23a is thick, it will not only waste materials and work hours, but also be unfavorable for the subsequent removal of the sidewall material layer 23a. If the thickness of the sidewall material layer 23a is thin, it will be unfavorable for the merging of the sidewall material layer 23a. It can be understood that the sidewall material layer 23a in the first gap 22 is merged from the narrower part (bottleneck 22a), and the sidewall material layer 23a starts to merge from the lower part of the top surface of the second sidewall structure 12, that is, from the middle part of the first gap 22. In other words, the sidewall material layer 23a is sealed in the first gap 22, and its sealing position can be near the middle part of the first gap 22. In this embodiment, the width of the first gap 22 can be, for example, 80 nanometers to 120 nanometers, and the thickness of the sidewall material layer 23a can be, for example, 60 nanometers to 100 nanometers.
[0059] Please refer to Figure 3d , perform a first dry etching process to remove the spacer material layer 23a above the surface of the substrate 10 and the top of the gate structure 11, expose the first dielectric layer 21 on the top of the gate structure 11 and above the surface of the substrate 10, and use the spacer material layer 23a covering the height of the sidewall portion of the gate structure 11 as the first spacer structure 24. When performing the first dry etching process, the etching parameters can be adjusted to make the ratio of the etching rate of the spacer material layer 23a to the etching rate of the first dielectric layer 21 greater than 5:1, so as to minimize the damage to the first dielectric layer 21 when removing the spacer material layer 23a. Among them, the side walls of the gate structure 11 in the first area AA and the second area BB (the first dielectric layer 21) both form the above-mentioned first sidewall structure 24, and the first sidewall structure 24 in the first gap 22 is at least partially merged, and the first dielectric layer 21 on the top of the exposed gate structure 11 not only includes the first dielectric layer 21 on the top wall of the gate structure 11, but also includes the first dielectric layer 21 on the slope surface extending from its top wall to the side wall. For example, only the sealed portion (merged portion 23b) in the first gap 22 and the sidewall material layer 23a thereunder may be retained.
[0060] Next, please refer to Figure 3e , performing step S04, etching the exposed first dielectric layer 21 to remove a portion of the thickness of the first dielectric layer 21.
[0061] Specifically, after forming the first spacer structure 24, the first spacer structure 24 is used as a mask to perform a second dry etching process to etch the exposed first dielectric layer 21, remove the top of the gate structure 11 and the first dielectric layer 21 partially above the surface of the substrate 10, and expand the opening of the first gap 22. When performing the second dry etching process, the etching parameters can be adjusted to make the ratio of the etching rate of the first dielectric layer 21 to the etching rate of the stop layer 13 greater than 5:1, so that the etching stops on the stop layer 13 and the damage to the stop layer 13 is minimized. It can be understood that the first spacer structure 24 is also synchronously etched in the second dry etching process, so that the height of the first spacer structure 24 becomes lower, and as the height of the first spacer structure 24 becomes lower, the width (opening width) of the first gap 22 near the top of the first spacer structure 24 is further expanded, but the first spacer structure 24 is not completely removed, that is, the first dielectric layer 21 at the bottom of the first gap 22 is not affected. In a preferred example, after the second dry etching process, the sealing portion (merging portion 23b) of the first sidewall structure 24 is removed, so that the first dielectric layer 21 near the sealing portion is at least partially removed. In other words, the second dry etching process also opens the bottleneck 22a of the first gap 22, making its narrow width wider.
[0062] Next, step S05 is performed to remove the first spacer structure 24 and form a second dielectric layer 26 to conformally cover the first dielectric layer 21 and fill the gate structure 11 . The second dielectric layer 26 and the first dielectric layer 21 serve as an interlayer dielectric layer 27 .
[0063] Please refer to Figure 3f , remove the first sidewall structure 24, and take the gap between the first dielectric layer 21 of the first region AA gate structure 11 as the second gap 25, the depth of the second gap 25 is the same as the depth of the first gap 22, and the opening width of the second gap 25 is increased relative to the opening width of the first gap 22, so that the average width of the second gap 25 is increased relative to the average width of the first gap 22, thereby effectively reducing the depth-to-width ratio of the subsequent filled dielectric layer. In particular, the second dry etching process also opens the bottleneck 22a of the first gap 22, so that the formed second gap 25 is more conducive to avoiding the formation of a sealed gap when filling the dielectric layer relative to the first gap 22, that is, it is more conducive to improving the filling effect of the dielectric layer. Taking the material of the first sidewall structure 24 including silicon nitride as an example, a wet etching process including phosphoric acid can be used to remove the first sidewall structure 24.
[0064] Please refer to Figure 3g, forming a second dielectric layer 26 to conformally cover the first dielectric layer 21 and fill it to the top of the gate structure 11, with the second dielectric layer 26 and the first dielectric layer 21 as the interlayer dielectric layer 27. The material of the second dielectric layer 26 can be the same as that of the first dielectric layer 21, and can be formed by the same process. Since the opening width and the average width of the second gap 25 are respectively larger than the opening width and the average width of the first gap 22, the two have the same depth, that is, the aspect ratio of the second gap 25 is smaller than the aspect ratio of the first gap 22, and the minimum width of the second gap 25 (bottleneck 22a) is larger than the minimum width of the first gap 22, therefore, the second dielectric layer 26 has a relatively low process difficulty when filling the second gap 25, and it is relatively easy to achieve gapless (void) filling of the second dielectric layer 26 between the gate structures 11.
[0065] Therefore, this embodiment has a more obvious effect on reducing the aspect ratio of the first gap, and usually only requires one Figure 3b to Figure 3f The steps are only required, which is beneficial to reduce the repeated deposition-etching cycle steps, that is, it has a higher filling efficiency. However, it can be understood that in other examples of the present embodiment, if the depth-to-width ratio of the first gap is relatively large, after removing the first sidewall structure to form the second gap, a third dielectric layer can be formed to conformally cover the surface of the first dielectric layer, and form a third gap in the second gap (the gap between the first dielectric layers of the gate structure in the first area is the second gap); a third sidewall structure is formed to cover the third dielectric layer at a height of part of the sidewall of the gate structure, exposing the third dielectric layer at the top of the gate structure, and the third sidewall structure in the third gap is at least partially merged; the exposed third dielectric layer is etched to remove part of the thickness of the third dielectric layer; the third sidewall structure is removed to form a second dielectric layer to conformally cover the third dielectric layer and fill it above the gate structure, with the third dielectric layer, the second dielectric layer and the first dielectric layer as the interlayer dielectric layer. In other words, the above example is equivalent to repeating the similar example twice. Figure 3b to Figure 3f The specific steps can refer to the above embodiments.
[0066] In summary, the present invention provides a method for forming an interlayer dielectric layer. After forming a first dielectric layer, a first sidewall structure is formed to cover a portion of the height of the sidewall of the gate structure, exposing the first dielectric layer at the top of the gate structure, and the first sidewall structure in the first gap is at least partially merged, and when etching (etching back) the first dielectric layer, the first sidewall structure merged in the first gap is used to protect the first dielectric layer at the bottom of the first gap. The opening width (average width) of the first dielectric layer can be expanded without increasing the depth of the first gap, thereby effectively reducing the aspect ratio of the dielectric layer filled in the first area (the area with a higher density of the gate structure), thereby improving the filling effect and filling efficiency of the interlayer dielectric layer.
[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for forming an interlayer dielectric layer, characterized in that: include: Providing a substrate, comprising a first region and a second region, wherein a gate structure and a stop layer covering the substrate surface and an outer wall of the gate structure are disposed on the first region and the second region, and the density of the gate structure in the first region is greater than the density of the gate structure in the second region; Forming a first dielectric layer to conformally cover the substrate surface and the stop layer surface of the outer wall of the gate structure, and the first dielectric layer between the gate structures in the first region retains an open first gap; Forming a first dielectric layer with a first spacer structure covering a portion of the height of the sidewall of the gate structure, exposing the first dielectric layer at the top of the gate structure, and at least partially merging the first spacer structure in the first gap; Etching the exposed first dielectric layer to remove a portion of the thickness of the first dielectric layer; The first sidewall structure is removed, and a second dielectric layer is formed to conformally cover the first dielectric layer and fill the gate structure, and the second dielectric layer and the first dielectric layer are used as an interlayer dielectric layer.
2. The method for forming an interlayer dielectric layer according to claim 1, characterized in that: The step of forming the first sidewall structure includes: Forming a spacer material layer to conformally cover the surface of the first dielectric layer in the first region and the second region, and merging at least a portion of the spacer material layer in the first gap; A first dry etching process is performed to remove the sidewall material layer above the substrate surface and the top of the gate structure, exposing the first dielectric layer on the top of the gate structure and above the substrate surface, and using the sidewall material layer covering the height of the sidewall portion of the gate structure as the first sidewall structure.
3. The method for forming an interlayer dielectric layer according to claim 2, characterized in that: When performing the first dry etching process, a ratio of an etching rate of the spacer material layer to an etching rate of the first dielectric layer is greater than 5:
1.
4. The method for forming an interlayer dielectric layer according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a gate conductive layer, a second mask layer and a first mask layer stacked in sequence from bottom to top. The sidewall of the gate structure is also provided with a second sidewall structure, and the top of the second sidewall structure is between the gate conductive layer and the first mask layer.
5. The method for forming an interlayer dielectric layer according to claim 1, characterized in that: After forming the first sidewall structure, a second dry etching process is performed using the first sidewall structure as a mask to etch the exposed first dielectric layer, remove the top of the gate structure and a portion of the thickness of the first dielectric layer above the substrate surface, and expand the opening of the first gap.
6. The method for forming an interlayer dielectric layer according to claim 5, characterized in that: When performing the second dry etching process, a ratio of an etching rate of the first dielectric layer to an etching rate of the stop layer is greater than 5:
1.
7. The method for forming an interlayer dielectric layer according to claim 5, characterized in that: The first sidewall structure in the first gap has a merging portion. After the second dry etching process is performed, the merging portion and the first dielectric layer around the merging portion are removed synchronously.
8. The method for forming an interlayer dielectric layer according to claim 1, characterized in that: The material of the first dielectric layer and / or the second dielectric layer includes silicon oxide, and the material of the first spacer structure includes silicon nitride.
9. The method for forming an interlayer dielectric layer according to claim 1, characterized in that: The distance between the centers of adjacent gate structures is the center distance, the ratio of the center distance of adjacent gate structures in the first region to the width of the gate structure in the first region is less than 3:1, and the ratio of the center distance of adjacent gate structures in the second region to the width of the gate structure in the second region is greater than or equal to 3:
1.
10. The method for forming an interlayer dielectric layer according to any one of claims 1 to 9, characterized in that: removing the first side wall structure; The formed third dielectric layer conformally covers the surface of the first dielectric layer and forms a third gap in the second gap; Forming a third dielectric layer with a third spacer structure covering a portion of the height of the sidewall of the gate structure, exposing the third dielectric layer at the top of the gate structure, and at least partially merging the third spacer structure in the third gap; Etching the exposed third dielectric layer to remove a portion of the thickness of the third dielectric layer; The third spacer structure is removed, and a second dielectric layer is formed to conformally cover the third dielectric layer and fill the gate structure, and the third dielectric layer, the second dielectric layer and the first dielectric layer are used as an interlayer dielectric layer.