Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The formation method includes: providing a substrate, forming a dielectric layer on the substrate, and forming an interconnect structure penetrating the dielectric layer within the dielectric layer, including a first interconnect opening and a second interconnect opening isolated from each other, wherein the opening size of the first interconnect opening is smaller than the opening size of the second interconnect opening; forming a first interconnect structure in the first interconnect opening and forming a second interconnect structure in the second interconnect opening; wherein the resistivity of the second interconnect structure material is lower than the resistivity of the first interconnect structure material, and the gap-filling capability of the first interconnect structure material is greater than the gap-filling capability of the second interconnect structure material. This invention, through the formation of the first and second interconnect structures, improves both the gap-filling performance of the interconnect structure material and ensures the conductivity of the interconnect structure, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the requirements of interconnects after the critical size reduction, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through interconnect structures. As technology nodes advance, the size of interconnect structures is becoming smaller and smaller; correspondingly, the process of forming interconnect structures is becoming more and more difficult. The formation quality of interconnect structures has a significant impact on the back end of line (BEOL) electrical performance and device reliability, and in severe cases, it can affect the normal operation of semiconductor devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which balances the filling ability of metal to interconnect openings and the overall resistivity of the device, thereby improving the electrical performance and reliability of the device.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, and an interconnect structure penetrating the dielectric layer is formed within the dielectric layer, including a first interconnect opening and a second interconnect opening isolated from each other, wherein the opening size of the first interconnect opening is smaller than the opening size of the second interconnect opening; forming a first interconnect structure in the first interconnect opening, and forming a second interconnect structure in the second interconnect opening; wherein the resistivity of the second interconnect structure material is less than the resistivity of the first interconnect structure material, and the gap-filling capability of the first interconnect structure material is greater than the gap-filling capability of the second interconnect structure material.

[0006] Optionally, before forming the first interconnect structure and the second interconnect structure, the forming method further includes: forming an impregnation layer at the bottom and sidewalls of the interconnect opening; forming a suppression layer covering the impregnation layer in the second interconnect opening; forming the first interconnect structure in the first interconnect opening using a selective forming process; and after forming the first interconnect structure, the forming method further includes: removing the suppression layer; and after removing the suppression layer, forming the second interconnect structure in the second interconnect opening.

[0007] Optionally, the wetting layer may be formed using a chemical vapor deposition process.

[0008] Optionally, the surface of the impregnation layer is treated using a chemical impregnation process to form the inhibition layer.

[0009] Optionally, the inhibition layer is an organic polymer molecular layer, wherein the physical diameter of the molecules in the organic polymer molecular layer is larger than the opening size of the first interconnection opening and smaller than the opening size of the second interconnection opening.

[0010] Optionally, the physical diameter of the molecules in the organic polymer molecular layer is greater than or equal to 10 nm.

[0011] Optionally, the material of the organic polymer molecular layer contains at least two elements selected from C, N, H, and O.

[0012] Optionally, the organic polymer molecular layer material includes one or both of poly(3-bipyridine) and polyethylene glycol-like substances.

[0013] Optionally, the thickness of the suppression layer is 0.5 nm to 5 nm.

[0014] Optionally, the inhibition layer can be removed using a drying process.

[0015] Optionally, the selective forming process includes selective deposition and selective electroplating.

[0016] Optionally, an electrochemical plating process is used to form a second interconnect structure in the second interconnect opening.

[0017] Optionally, the material of the first interconnect structure includes one or more of Co, W, Mo and Ru, and the material of the second interconnect structure includes one or more of Cu, Al, Ag and Au.

[0018] Optionally, before forming an impregnation layer at the bottom and sidewalls of the interconnect opening, the forming method further includes forming a barrier layer at the bottom and sidewalls of the interconnect opening.

[0019] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a dielectric layer located on the substrate; an interconnect opening penetrating the dielectric layer, the interconnect opening including a first interconnect opening and a second interconnect opening isolated from each other, the opening size of the first interconnect opening being smaller than the opening size of the second interconnect opening; a first interconnect structure located in the first interconnect opening; and a second interconnect structure located in the second interconnect opening; wherein the resistivity of the second interconnect structure material is less than the resistivity of the first interconnect structure material, and the gap-filling capability of the first interconnect structure material is greater than the gap-filling capability of the second interconnect structure material.

[0020] Optionally, the semiconductor structure further includes: an impregnation layer located at the bottom and sidewalls of the interconnect opening; a first interconnect structure located in the first interconnect opening where the impregnation layer is formed and in contact with the impregnation layer; and a second interconnect structure located in the second interconnect opening where the impregnation layer is formed.

[0021] Optionally, the material of the wetting layer includes one or more of Co and Ru.

[0022] Optionally, the material of the first interconnect structure includes one or more of Co, W, Mo and Ru, and the material of the second interconnect structure includes one or more of Cu, Al, Ag and Au.

[0023] Optionally, the semiconductor structure further includes: a barrier layer located between the bottom of the interconnect opening and the wetting layer, and between the sidewall of the interconnect opening and the wetting layer.

[0024] Optionally, the material of the barrier layer includes one or more of TiN, TaN, TiSiN, TaSiN, Ti, and Ta.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] This invention provides an embodiment in which interconnect openings are formed within an inter-metal dielectric (IMD). These interconnect openings include a first interconnect opening and a second interconnect opening that are isolated from each other. The opening size of the first interconnect opening is smaller than that of the second interconnect opening. A first interconnect structure is formed within the first interconnect opening, and a second interconnect structure is formed within the second interconnect opening. The resistivity of the material of the second interconnect structure is lower than that of the material of the first interconnect structure, and the gap-filling capability of the material of the first interconnect structure is greater than that of the material of the second interconnect structure. Because the opening size of the first interconnect opening is smaller, the requirement for the gap-filling capability of the first interconnect structure material is correspondingly higher. Conversely, the opening size of the second interconnect opening is larger, making it easier for the material of the second interconnect structure to fill the second interconnect opening, thus requiring a lower gap-filling capability. Therefore, by employing a first interconnect structure with better gap-filling capability and a second interconnect structure with lower material resistivity, the filling effect of the material of the first interconnect structure within the first interconnect opening is improved, while the overall resistivity of the interconnect structure is reduced. In other words, the gap-filling performance of the interconnect structure material is improved while ensuring the conductivity of the interconnect structure, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance. Attached Figure Description

[0027] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0028] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0029] Figures 6 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0030] The electrical performance and reliability of current devices still need improvement. This paper analyzes the reasons why the electrical performance and reliability of a semiconductor structure still need improvement, using the formation method of such a structure as an example.

[0031] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1 The substrate includes a front dielectric layer 10 and a front interconnect structure 11 located in the front dielectric layer 10; a dielectric layer 30 is formed on the substrate, and an interconnect opening 50 is formed in the dielectric layer 30, the interconnect opening 50 including a first interconnect opening 51 and a second interconnect opening 52 isolated from each other, the opening size of the first interconnect opening 51 being smaller than the opening size of the second interconnect opening 52, and a hard mask layer 40 is formed on the top of the dielectric layer 30.

[0033] As an example, both the first interconnect opening 51 and the second interconnect opening 52 include a groove 53 and a through hole 54, the bottom of the groove 53 is connected to the top of the through hole 54, and the opening size of the groove 53 in the first interconnect opening 51 is smaller than the opening size of the groove 53 in the second interconnect opening 52.

[0034] refer to Figure 2 A barrier layer 60 is formed at the bottom and sidewalls of the interconnection opening 50, and a seed layer 70 is formed on the barrier layer 60.

[0035] refer to Figure 3 The interconnection opening 50 is filled with conductive material 80, which covers the seed layer 70.

[0036] refer to Figure 4 For the conductive material 80 (e.g. Figure 3 The conductive material 80, seed layer 70, barrier layer 60, and hard mask layer 40 (as shown) above the top surface of dielectric layer 30 are planarized, and the conductive material 80, seed layer 70, barrier layer 60, and hard mask layer 40 above the top surface of dielectric layer 30 are removed. Figure 3As shown), the interconnection opening 50 is retained (as shown). Figure 1 The remaining conductive material 80 in the diagram forms the first interconnect structure 81 and the second interconnect structure 82.

[0037] The interconnect structure 90 includes the first interconnect structure 81 and the second interconnect structure 82. To reduce the resistance of the interconnect structure 90, a material with low resistivity is typically selected. For example, Cu is selected as the conductive material 80.

[0038] However, since some interconnect openings have small opening sizes (such as the interconnect opening 50 including a first interconnect opening 51 and a second interconnect opening 52 that are isolated from each other, the opening size of the first interconnect opening 51 is smaller than the opening size of the second interconnect opening 52, that is, the opening size of the first interconnect opening 51 is smaller), the requirements for the gap filling ability of the conductive material are high when the conductive material is filled into the interconnect opening with a smaller opening size.

[0039] Furthermore, as device feature sizes continue to shrink, the opening size of interconnect apertures also decreases, placing higher demands on the gap-filling capability of interconnect structure materials. Therefore, when forming the interconnect structure 81, a conductive material 80 with strong gap-filling capability must be selected. For example, Co is selected as the conductive material 80.

[0040] However, it is difficult to ensure that the conductive material 80 with strong gap filling ability also has the characteristic of low resistivity. Although it can improve the filling of the interconnect structure 81 in the interconnect opening 51, it is easy to cause the problem of excessive resistance of the interconnect structure 81, which leads to poor conductivity of the formed interconnect opening 81, and consequently, a decrease in the electrical performance and reliability of the device. For example, the electrical performance of the later stage cannot meet the process requirements, and there are problems such as electromigration failure.

[0041] For example, Co has better interstitial filling ability than Cu, but Cu has lower resistivity than Co.

[0042] Therefore, there is an urgent need to provide a method for forming interconnect structures to balance the requirements for the resistance and gap filling capability of the interconnect structures.

[0043] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, and an interconnect structure penetrating the dielectric layer is formed within the dielectric layer, including a first interconnect opening and a second interconnect opening isolated from each other, wherein the opening size of the first interconnect opening is smaller than the opening size of the second interconnect opening; forming a first interconnect structure in the first interconnect opening, and forming a second interconnect structure in the second interconnect opening; wherein the resistivity of the second interconnect structure material is less than the resistivity of the first interconnect structure material, and the gap-filling capability of the first interconnect structure material is greater than the gap-filling capability of the second interconnect structure material.

[0044] This invention provides an embodiment in which interconnect openings are formed within an inter-metal dielectric (IMD). These interconnect openings include a first interconnect opening and a second interconnect opening that are isolated from each other. The opening size of the first interconnect opening is smaller than that of the second interconnect opening. A first interconnect structure is formed within the first interconnect opening, and a second interconnect structure is formed within the second interconnect opening. The resistivity of the material of the second interconnect structure is lower than that of the material of the first interconnect structure, and the gap-filling capability of the material of the first interconnect structure is greater than that of the material of the second interconnect structure. Because the opening size of the first interconnect opening is smaller, the requirement for the gap-filling capability of the first interconnect structure material is correspondingly higher. Conversely, the opening size of the second interconnect opening is larger, making it easier for the material of the second interconnect structure to fill the second interconnect opening, thus requiring a lower gap-filling capability. Therefore, by employing a first interconnect structure with better gap-filling capability and a second interconnect structure with lower material resistivity, the filling effect of the material of the first interconnect structure within the first interconnect opening is improved, while the overall resistivity of the interconnect structure is reduced. In other words, the gap-filling performance of the interconnect structure material is improved while ensuring the conductivity of the interconnect structure, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance.

[0045] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] refer to Figure 5 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0047] The semiconductor structure includes: a substrate 101; a dielectric layer 301 located on the substrate 101; an interconnect opening (not shown) penetrating the dielectric layer 301, the interconnect opening including a first interconnect opening (not shown) and a second interconnect opening (not shown) isolated from each other, the opening size of the first interconnect opening being smaller than the opening size of the second interconnect opening; a first interconnect structure 701 located in the first interconnect opening; and a second interconnect structure 711 located in the second interconnect opening.

[0048] Wherein, the resistivity of the second interconnect structure 711 material is less than that of the first interconnect structure 701 material, and the gap-filling capacity of the first interconnect structure 701 material is greater than that of the second interconnect structure 711 material.

[0049] Because the opening size of the first interconnect is smaller, the requirements for the gap-filling ability of the first interconnect structure material are correspondingly higher. On the other hand, the opening size of the second interconnect is larger, and the material of the second interconnect structure is easier to fill into the second interconnect opening, thus requiring less gap-filling ability. Therefore, by using a first interconnect structure with better gap-filling ability and a second interconnect structure with lower material resistivity, the filling effect of the first interconnect structure material in the first interconnect opening is improved, while the overall resistivity of the interconnect structure is reduced. In other words, the gap-filling performance of the interconnect structure material is improved, while the conductivity of the interconnect structure is ensured, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance.

[0050] The substrate 101 provides the basis for the process operation of forming the semiconductor structure.

[0051] In this embodiment, depending on the actual process, a functional structure can be formed within the substrate. For example, a semiconductor device such as a MOS field-effect transistor can be formed within the substrate, as can a resistive structure. In other embodiments, at least one interlayer metal structure (i.e., Mx layer) can also be formed within the substrate.

[0052] In this embodiment, the substrate includes a front dielectric layer 101 and a front interconnect structure 111 located in the front dielectric layer 101.

[0053] The front-layer interconnect structure 111 is used to achieve electrical connection with the first interconnect structure 701 and the second interconnect structure 711.

[0054] In this embodiment, the front interconnect structure 111 is used as the first interlayer metal structure (i.e., M1 layer) for illustration.

[0055] In other embodiments, when an interlayer metal structure is formed within the substrate, the front-layer interconnect structure is also used to achieve electrical connection with the interlayer metal structure within the substrate. For example, when a first interlayer metal structure is formed within the substrate, the front-layer interconnect structure is correspondingly a second interlayer metal structure (i.e., M2layer).

[0056] In this embodiment, the material of the front-layer interconnect structure 111 is Cu. Cu has low resistivity, which is beneficial for reducing the RC delay (resistance-capacitance delay) of the device, and Cu also has excellent electromigration resistance. In other embodiments, depending on actual process requirements, the material of the front-layer interconnect structure may also be Al or W.

[0057] In this embodiment, the semiconductor structure further includes an etch stop layer 201 located between the dielectric layer 301 and the substrate 101.

[0058] The interconnect opening is formed by etching the dielectric layer 301 and the etch stop layer 201, with the top surface of the etch stop layer 201 serving as the etch termination point when etching the dielectric layer 301.

[0059] The material of the etching stop layer 201 includes at least one of SiCN, SiOC, SiN, SiON, AlN, and Al2O3.

[0060] The dielectric layer 301 is used to insulate the interconnect structures formed subsequently from each other, and also to provide a process platform for the subsequent formation of interconnect structures.

[0061] The dielectric layer 301 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the bottom dielectric layer 301 is made of an ultra-low k dielectric material, which is SiOCH containing pores. The process for forming the bottom dielectric layer 301 is chemical vapor deposition.

[0062] The interconnection opening provides space for forming the first interconnection structure 701 and the second interconnection structure 711, and the interconnection opening exposes the underlying interconnection structure 111, thereby enabling the first interconnection structure 701 and the second interconnection structure 711 to be electrically connected to the underlying interconnection structure 111.

[0063] The interconnection opening can be a trench, a through hole, or a combination of both. In this embodiment, the interconnection opening includes a through trench (not shown) and a through hole (not shown) that are perpendicular to each other. The bottom of the trench and the top of the through hole are connected, and the width of the bottom of the trench is greater than the width of the top of the through hole.

[0064] In this embodiment, the opening size of the first interconnect opening is smaller than the opening size of the second interconnect opening.

[0065] It should be noted that the opening size refers to the top opening size of the first interconnect opening and the second interconnect opening.

[0066] The first interconnect structure 701 is used to electrically connect with the front interconnect structure 111 below it, thereby realizing the electrical connection between the corresponding front interconnect structure 111 and other circuits.

[0067] The material of the first interconnect structure 701 includes one or more of Co, W, Mo, and Ru. In this embodiment, the material of the first interconnect structure 701 is Co. Specifically, Co has better gap-filling properties.

[0068] The second interconnect structure 711 is used to electrically connect with the front interconnect structure 111 below it, thereby realizing the electrical connection between the corresponding front interconnect structure 111 and other circuits.

[0069] The material of the second interconnect structure 711 includes one or more of Cu, Al, Ag, and Au. In this embodiment, the material of the second interconnect structure 711 is Cu. Cu has a low resistivity.

[0070] In this embodiment, the semiconductor structure further includes a barrier layer 601 located at the bottom and sidewalls of the interconnect opening.

[0071] The barrier layer 601 is used to prevent the materials of the first interconnect structure 701 and the second interconnect structure 711 from diffusing into the dielectric layer 301.

[0072] The barrier layer 601 is made of one or more of TiN, TaN, TiSiN, TaSiN, Ti, and Ta. In this embodiment, the barrier layer 601 is made of TiN.

[0073] In this embodiment, the semiconductor structure further includes an impregnation layer 611 located at the bottom and sidewalls of the interconnect opening. Specifically, the impregnation layer 611 is located on the barrier layer 601.

[0074] The impregnation layer 611 is used to provide a growth basis for the filling of the first interconnect structure 701 and the second interconnect structure 711 in the first interconnect opening.

[0075] In this embodiment, the first interconnect structure 701 is located in the first interconnect opening in which the impregnation layer 611 is formed, and is in contact with the impregnation layer 611.

[0076] During the formation of the semiconductor structure, the first interconnect structure 701 is formed in the first interconnect opening by selective deposition, and therefore, the first interconnect structure 701 is in contact with the wetting layer 611.

[0077] In this embodiment, the second interconnect structure is located in the second interconnect opening in which the impregnation layer 611 is formed.

[0078] The material of the wetting layer 611 is one or more of Co and Ru. In this embodiment, the material of the wetting layer 611 is Co.

[0079] In this embodiment, the semiconductor structure further includes a seed layer 631 located on the impregnation layer 611 in the second interconnect opening 521. Specifically, the seed layer 631 is located between the second interconnect structure 811 and the impregnation layer 611.

[0080] The seed layer 631 is used to provide a growth basis for the formation of the second interconnect structure 811 in the second interconnect opening.

[0081] The seed layer 631 is made of one or more of Cu, CuMn, or CuAl. In this embodiment, the seed layer 631 is made of Cu.

[0082] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure. Figures 6 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0083] refer to Figure 6 A substrate is provided, on which a dielectric layer 300 is formed. An interconnect opening 500 is formed in the dielectric layer 300, penetrating the dielectric layer 300. The interconnect opening 500 includes a first interconnect opening 510 and a second interconnect opening 520 that are isolated from each other. The opening size of the first interconnect opening 510 is smaller than the opening size of the second interconnect opening 520.

[0084] The substrate provides the basis for subsequent process operations.

[0085] In this embodiment, depending on the actual process, functional structures can be formed within the substrate. For example, semiconductor devices such as MOS field-effect transistors and resistive structures can be formed within the substrate. In other embodiments, at least one interlayer metal structure (Mx layer) can also be formed within the substrate.

[0086] In this embodiment, the substrate includes a front dielectric layer 100 and a front interconnect structure 110 located in the front dielectric layer 100.

[0087] The front dielectric layer 100 is used to insulate the front interconnect structures 110 from each other.

[0088] The material of the front dielectric layer 100 is one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the material of the front dielectric layer 100 is an ultra-low k dielectric material (ultra-low k dielectric material refers to a dielectric material with a relative permittivity of less than 2.6), and the ultra-low k dielectric material is SiOCH containing pores.

[0089] The front-layer interconnect structure 110 is used to achieve electrical connection with the interconnect structure to be formed.

[0090] In this embodiment, the front interconnect structure 110 is used as the first interlayer metal structure (i.e., M1 layer) for illustration.

[0091] In other embodiments, when an interlayer metal structure is formed within the substrate, the front-layer interconnect structure is also used to achieve electrical connection with the interlayer metal structure within the substrate. For example, when a first interlayer metal structure is formed within the substrate, the front-layer interconnect structure is correspondingly a second interlayer metal structure (i.e., M2layer).

[0092] In this embodiment, the material of the front-layer interconnect structure 110 is Cu. Cu has low resistivity, which is beneficial for reducing the RC delay (resistance-capacitance delay) of the device, and Cu also has excellent electromigration resistance. In other embodiments, depending on actual process requirements, the material of the front-layer interconnect structure may also be Al or W.

[0093] In this embodiment, an etch stop layer 200 is also formed between the dielectric layer 300 and the substrate.

[0094] The interconnect opening 500 is formed by etching the dielectric layer 300 and the etch stop layer 200, with the top surface of the etch stop layer 200 serving as the etch termination point when etching the dielectric layer 300.

[0095] The material of the etching stop layer 200 includes at least one of SiCN, SiOC, SiN, SiON, AlN, and Al2O3.

[0096] The dielectric layer 300 is used to insulate the interconnect structures formed subsequently from each other, and also to provide a process platform for the subsequent formation of interconnect structures.

[0097] The dielectric layer 300 is made of one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. In this embodiment, the bottom dielectric layer 300 is made of an ultra-low k dielectric material, which is SiOCH containing pores, and the bottom dielectric layer 300 is formed by chemical vapor deposition.

[0098] In this embodiment, a hard mask layer 400 is also formed on the dielectric layer 300.

[0099] The hard mask layer 400 serves as an etching mask during the patterning of the dielectric layer 300 to form the interconnect opening 500.

[0100] In this embodiment, the hard mask layer 400 is a metal hard mask layer, and the material of the hard mask layer 400 includes one or more of TiN, AlN, Al2O3, WCN, and Cu3N, that is, the hard mask layer 400 can be a single-layer structure or a stacked structure. As an example, the material of the metal hard mask layer is TiN, that is, the hard mask layer 400 is a single-layer TiN layer.

[0101] Specifically, a hard mask layer 400 is formed on the dielectric layer 300 using a physical vapor deposition process.

[0102] The interconnect opening 500 provides space for the subsequent formation of the first interconnect structure and the second interconnect structure, and the interconnect opening 500 exposes the underlying interconnect structure 110, thereby enabling the subsequent first interconnect structure and the second interconnect structure to be electrically connected to the corresponding underlying interconnect structure 110.

[0103] Specifically, the step of forming the interconnection opening 500 includes: as follows Figure 5 As shown, the patterned hard mask layer 400 is used as a mask to pattern the dielectric layer 300. An interconnect opening 500 is formed in the dielectric layer 300 to expose the underlying interconnect structure 110. The interconnect opening 500 includes a first interconnect opening 510 and a second interconnect opening 520 that are isolated from each other. The opening size of the first interconnect opening 510 is smaller than the opening size of the second interconnect opening 520.

[0104] Etching with the patterned hard mask layer 400 as a mask can better control the pattern morphology of the interconnect opening 500, making the sidewalls of the interconnect opening 500 smoother.

[0105] The interconnect opening 500 can be a trench, a via, or a combination of both. In this embodiment, the dielectric layer 300 is etched using a dual damascene process to form the interconnect opening 500. Therefore, in the step of forming the interconnect opening 500, the interconnect opening 500 includes a through trench 530 and a via 540 that are interconnected, the bottom of the trench 530 and the top of the via 540 are connected, and the width of the bottom of the trench 530 is greater than the width of the top of the via 540.

[0106] Specifically, the interconnect opening 500 is formed by integral etching, and the patterned hard mask layer 400 is used as an etching mask for forming the trench 530.

[0107] In this embodiment, the opening size of the first interconnect opening 510 is smaller than the opening size of the second interconnect opening 520.

[0108] It should be noted that the opening size refers to the top opening size of the first interconnect opening 510 and the second interconnect opening 520.

[0109] As an example, the minimum opening size of the second interconnect opening 520 is greater than or equal to 10 nm.

[0110] In some embodiments, the minimum opening size of the second interconnect opening is greater than or equal to 15 nm, and in other embodiments, the minimum opening size of the second interconnect opening is greater than or equal to 20 nm.

[0111] The first interconnection opening 510 and the second interconnection opening 520 can be distinguished by selecting an appropriate opening size standard according to process requirements.

[0112] refer to Figure 7 After the interconnection opening 500 is formed, a barrier layer 600 is formed at the bottom and sidewall of the interconnection opening 500, and an impregnation layer 610 is formed on the barrier layer 600.

[0113] Subsequently, an interconnect structure is formed in the interconnect opening 500, and the barrier layer 600 is used to prevent the diffusion of the material of the interconnect structure.

[0114] In this embodiment, the barrier layer 600 is formed using a physical vapor deposition process.

[0115] The barrier layer 600 is made of one or more of TiN, TaN, TiSiN, TaSiN, Ti, and Ta. In this embodiment, the barrier layer 600 is made of TiN.

[0116] The wetting layer 610 provides a growth base for the subsequent growth of conductive materials within the interconnect opening 500.

[0117] In this embodiment, the wetting layer 610 is formed using a chemical vapor deposition process.

[0118] The material of the wetting layer 610 is one or more of Co and Ru. In this embodiment, the material of the wetting layer 610 is Co.

[0119] In subsequent processes, Co and Ru have a strong binding force with the seed layer, which facilitates the growth of the seed layer.

[0120] refer to Figure 8 After the wetting layer 610 is formed, the inhibition layer 620 is formed at the bottom and sidewall of the second interconnection opening 520.

[0121] The inhibition layer 620 covers the impregnation layer 610 in the second interconnect opening 520 and is used to inhibit the growth of the subsequent first interconnect structure in the second interconnect opening.

[0122] In this embodiment, the surface of the impregnation layer 610 is treated by chemical impregnation to form the inhibition layer 620.

[0123] The chemical impregnation process is simple and easy to operate, and it also facilitates the subsequent removal of the inhibition layer 620.

[0124] In this embodiment, the inhibition layer 620 is an organic polymer molecular layer.

[0125] The organic polymer molecules can adhere to the surfaces of materials of different shapes and are easily volatile, which is beneficial for removing the inhibition layer 620 in subsequent processes.

[0126] In this embodiment, the physical diameter of the molecules in the organic polymer molecular layer is larger than the opening size of the first interconnection opening 510 and smaller than the opening size of the second interconnection opening 520.

[0127] Due to the size limitation of the polymer or polymer salt molecules in the inhibition layer 620, molecules in the organic polymer molecular layer can only enter interconnect openings larger than or equal to a preset size. In this embodiment, during the formation of the inhibition layer 610, molecules in the organic polymer molecular layer cannot enter the first interconnect opening 510, but can enter the second interconnect opening 520, thereby allowing the inhibition layer 620 to cover the wetting layer 610 in the second interconnect opening 520, while the wetting layer 610 in the first interconnect opening 510 is exposed.

[0128] In this embodiment, the physical diameter of the molecules in the organic polymer molecular layer is greater than or equal to 10 nm. Accordingly, this allows the polymer molecules to enter trenches or vias with a minimum opening size greater than or equal to 10 nm.

[0129] In other cases, polymer molecules of appropriate size are selected based on the opening sizes of the first interconnect opening and the second interconnect opening, so that they can only enter the interconnect opening with the larger opening size. For example, the size of the polymer molecules is adjusted so that they can only enter trenches or vias with a minimum opening size greater than or equal to 15 nm; in other cases, the size of the polymer molecules is adjusted so that they can only enter trenches or vias with a minimum opening size greater than or equal to 20 nm.

[0130] In this embodiment, the suppression layer 620 also covers the top of the dielectric layer 300.

[0131] In this embodiment, the material of the organic polymer molecular layer contains at least two elements selected from C, N, H, and O.

[0132] Containing C, N, H and O elements helps to inhibit electroplating, thus acting as an inhibitory layer.

[0133] In this embodiment, the organic polymer molecular layer material includes one or both of poly(3-bipyridine) and polyethylene glycol-like substances.

[0134] Poly(3-bipyridine) and polyethylene glycol-like compounds are commonly used in industry and have good chemical stability.

[0135] It should be noted that the thickness of the inhibition layer 620 should not be too small or too large. If the thickness of the inhibition layer 620 is too small, insufficient inhibition of the growth of the first interconnect structure material in the second interconnect opening will occur in subsequent processes; if the thickness of the inhibition layer 620 is too large, it will not be completely removed during removal, resulting in a too slow selective electroplating rate in subsequent processes. Therefore, in this embodiment, the thickness of the inhibition layer is 0.5 nm to 5 nm.

[0136] It should also be noted that, compared with the method of forming a sacrificial layer that fills the second interconnection opening, by forming a suppression layer 620 covering the impregnation layer 610, the total amount of suppression layer 620 is removed in the subsequent removal. Therefore, the suppression layer 620 is easier to remove in the subsequent removal, and correspondingly, the damage to other film layers is also less.

[0137] refer to Figures 9 to 13 In the first interconnection opening 510 (e.g. Figure 8 A first interconnect structure 700 is formed in the second interconnect opening 520, and a second interconnect structure 710 is formed in the second interconnect opening 520.

[0138] Wherein, the resistivity of the second interconnect structure 710 material is less than that of the first interconnect structure 700 material, and the gap-filling capability of the first interconnect structure 700 material is greater than that of the second interconnect structure 710 material.

[0139] Because the opening size of the first interconnect is smaller, the requirements for the gap-filling ability of the first interconnect structure material are correspondingly higher. On the other hand, the opening size of the second interconnect is larger, and the material of the second interconnect structure is easier to fill into the second interconnect opening, thus requiring less gap-filling ability. Therefore, by using a first interconnect structure with better gap-filling ability and a second interconnect structure with lower material resistivity, the filling effect of the first interconnect structure material in the first interconnect opening is improved, while the overall resistivity of the interconnect structure is reduced. In other words, the gap-filling performance of the interconnect structure material is improved, while the conductivity of the interconnect structure is ensured, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance.

[0140] The first interconnect structure 700 and the second interconnect structure 710 formed improve the filling effect of the material in the first interconnect structure within the first interconnect opening and reduce the overall resistivity of the interconnect structure. This makes the interconnect structure not only improve the gap filling performance of the metal material, but also ensure the conductivity of the interconnect structure, thereby improving the electrical performance and reliability of the device, such as back-end electrical performance and electromigration (EM) performance.

[0141] In this embodiment, the second interconnect structure is formed after the first interconnect structure is formed.

[0142] Specifically, refer to Figure 9 In the first interconnection opening 510 (e.g. Figure 8 As shown, the first interconnect structure 700 is formed.

[0143] The first interconnect structure 700 is electrically connected to the front interconnect structure 110 located below it, thereby realizing the electrical connection between the corresponding front interconnect structure 110 and other circuits.

[0144] In this embodiment, the first interconnect structure 700 is formed in the first interconnect opening 510 using a selective forming process.

[0145] By employing a selective forming process, the first interconnect structure 700 can be selectively formed on the surface of a highly conductive layer (e.g., a metal layer), while it is difficult to form on the surface of a less conductive film layer (e.g., a less conductive conductive layer or a dielectric layer). Since the bottom and sidewalls of the first interconnect opening 510 are covered by a wetting layer 610, which is conductive, and the inhibition layer 620 covers the wetting layer 610 in the second interconnect opening 520, the first interconnect structure 700 cannot grow on the surface of the inhibition layer 620. Therefore, the material of the first interconnect structure 700 will only grow and fill within the first interconnect opening 510.

[0146] In this embodiment, the selective forming process is a selective electroplating process. The selective electroplating process has lower costs and produces higher film quality.

[0147] In other embodiments, the selective forming process can also be a selective deposition process. In this embodiment, a second interconnect structure is subsequently formed in the second interconnect opening 520, and the gap-filling capacity of the material of the first interconnect structure 700 is greater than that of the material of the second interconnect structure.

[0148] Since the material activity and flowability of the first interconnect structure 700 are better than those of the material of the second interconnect structure, the gap filling capacity of the material of the first interconnect structure 700 is greater than that of the material of the second interconnect structure.

[0149] The material of the first interconnect structure 700 includes one or more of Co, W, Mo and Ru.

[0150] Co, W, Mo, and Ru have similar chemical properties and all have good metal filling ability, making them suitable for filling small gaps.

[0151] In this embodiment, the material of the first interconnect structure 700 is Co. Specifically, Co has better filling performance.

[0152] The area covered by the suppression layer 620 cannot form the first interconnect structure 700, so that the first interconnect structure 700 is formed only in the first interconnect opening 510.

[0153] refer to Figure 10 After forming the first interconnect structure 700, the suppression layer 620 is removed (e.g., Figure 9 (As shown).

[0154] Remove the inhibition layer 620 to expose the second interconnect opening 520, which provides space for the subsequent formation of the second interconnect structure in the second interconnect opening 520.

[0155] In this embodiment, the inhibition layer 620 is removed using a drying process.

[0156] Since the inhibition layer 620 is an organic molecular material, it can be naturally removed through a drying process. Compared with etching, the drying process helps to reduce damage to other film layers and has a lower process risk.

[0157] In other embodiments, the inhibition layer can also be removed using a chemical cleaning process.

[0158] refer to Figure 11 After the inhibition layer 620 is removed, a seed layer 630 is formed on the surface of the wetting layer 610 within the second interconnection opening 520.

[0159] The seed layer 630 is used to provide a growth basis for the subsequent formation of the second interconnect structure in the second interconnect opening 520.

[0160] In this embodiment, a seed layer 630 is formed on the surface of the wetting layer 610 using a chemical vapor deposition or physical vapor deposition process. The seed layer 630 also covers the top of the dielectric layer 300.

[0161] It should be noted that a first interconnect structure 700 is formed in the first interconnect opening, therefore, the seed layer 630 also covers the top of the first interconnect structure 700.

[0162] The seed layer 630 is made of one or more of Cu, CuMn, or CuAl. In this embodiment, the seed layer 630 is made of Cu.

[0163] Reference Figure 12 and Figure 13 In the second interconnection opening 520 (e.g. Figure 11 The second interconnect structure 710 is formed in the diagram.

[0164] The second interconnect structure 710 is electrically connected to the front interconnect structure 110 located below it, thereby realizing the electrical connection between the corresponding front interconnect structure 110 and other circuits.

[0165] In this embodiment, an electrochemical plating process is used to form the second interconnect structure 710 in the second interconnect opening 520. The electrochemical plating process is simple and helps to reduce process complexity.

[0166] Specifically, the steps for forming the second interconnect structure 710 include: combining with a reference Figure 12 and Figure 13After the seed layer 630 is formed, conductive material 710 is filled into the second interconnect opening 520, and the conductive material 710 covers the seed layer 630; the conductive material 710 is planarized, and the conductive material 710, the first interconnect structure 700, the seed layer 630, the wetting layer 610, the barrier layer 60 and the hard mask layer 400 above the top of the dielectric layer 300 are removed, and the remaining conductive material 710 in the second interconnect opening 520 is retained as the second interconnect structure 710.

[0167] Accordingly, after the second interconnect structure 710 is formed, the top of the second interconnect structure 710 and the first interconnect structure 700 are flush with the top of the dielectric layer 300.

[0168] In this embodiment, after the seed layer 630 is formed, an electrochemical plating process is used to fill the second interconnect opening 520 with conductive material 710.

[0169] The material of the second interconnect structure 710 includes one or more of Cu, Al, Ag and Au.

[0170] In this embodiment, the material of the second interconnect structure 710 is Cu.

[0171] In this embodiment, the second interconnect structure 710 is formed after the first interconnect structure 700 is formed. Therefore, it is easy to selectively form the first interconnect structure in the first interconnect opening, which simplifies the process steps for forming the interconnect structure.

[0172] In other embodiments, the first interconnect structure may be formed after the second interconnect structure is formed.

[0173] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0174] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a dielectric layer is formed, and an interconnection opening penetrating the dielectric layer is formed within the dielectric layer. The interconnection opening includes a first interconnection opening and a second interconnection opening that are isolated from each other, wherein the opening size of the first interconnection opening is smaller than the opening size of the second interconnection opening. A first interconnect structure is formed in the first interconnect opening, and a second interconnect structure is formed in the second interconnect opening; Wherein, the resistivity of the second interconnect structure material is less than that of the first interconnect structure material, and the gap-filling capacity of the first interconnect structure material is greater than that of the second interconnect structure material; Before forming the first interconnect structure and the second interconnect structure, the forming method further includes: forming an impregnation layer at the bottom and sidewalls of the interconnect opening; and forming an inhibition layer covering the impregnation layer in the second interconnect opening. A selective forming process is used to form the first interconnect structure in the first interconnect opening; After forming the first interconnect structure, the forming method further includes: removing the suppression layer; After removing the suppression layer, a second interconnect structure is formed in the second interconnect opening.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The wetting layer is formed using a chemical vapor deposition process.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The surface of the impregnation layer is treated using a chemical impregnation process to form the inhibition layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The inhibition layer is an organic polymer molecular layer, wherein the physical diameter of the molecules in the organic polymer molecular layer is larger than the opening size of the first interconnection opening and smaller than the opening size of the second interconnection opening.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The physical diameter of the molecules in the organic polymer molecular layer is greater than or equal to 10 nm.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The material of the organic polymer molecular layer contains at least two elements selected from C, N, H, and O.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, The organic polymer molecular layer material includes one or both of poly(3-bipyridine) and polyethylene glycol-like substances.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the suppression layer is 0.5 nm to 5 nm.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The inhibition layer is removed using a drying process.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The selective forming process includes selective deposition and selective electroplating.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, An electrochemical plating process is used to form a second interconnect structure in the second interconnect opening.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first interconnect structure includes one or more of Co, W, Mo and Ru, and the material of the second interconnect structure includes one or more of Cu, Al, Ag and Au.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming an impregnation layer on the bottom and sidewalls of the interconnect opening, the forming method further includes forming a barrier layer on the bottom and sidewalls of the interconnect opening.

14. A semiconductor structure, characterized in that, include: Base; A dielectric layer is located on the substrate; An interconnect opening extends through the dielectric layer, and the interconnect opening includes a first interconnect opening and a second interconnect opening that are isolated from each other, wherein the opening size of the first interconnect opening is smaller than the opening size of the second interconnect opening; A first interconnect structure is located in the first interconnect opening; The second interconnect structure is located in the second interconnect opening; Wherein, the resistivity of the second interconnect structure material is less than that of the first interconnect structure material, and the gap-filling capacity of the first interconnect structure material is greater than that of the second interconnect structure material; An impregnation layer is located at the bottom and sidewalls of the interconnection opening; The first interconnect structure is located in the first interconnect opening in which the impregnation layer is formed, and is in contact with the impregnation layer; The second interconnect structure is located in the second interconnect opening in which the impregnation layer is formed; There is no residue of the first interconnect structure material between the second interconnect structure and the impregnation layer.

15. The semiconductor structure as described in claim 14, characterized in that, The material of the impregnation layer includes one or more of Co and Ru.

16. The semiconductor structure as claimed in claim 14, characterized in that, The material of the first interconnect structure includes one or more of Co, W, Mo and Ru, and the material of the second interconnect structure includes one or more of Cu, Al, Ag and Au.

17. The semiconductor structure as claimed in claim 14, characterized in that, The semiconductor structure further includes: a barrier layer located between the bottom of the interconnect opening and the wetting layer, and between the sidewall of the interconnect opening and the wetting layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The material of the barrier layer includes one or more of TiN, TaN, TiSiN, TaSiN, Ti, and Ta.

Images