Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus

Abstract

The application provides a semiconductor device, a manufacturing method of the semiconductor device and an electronic device. A first field plate polysilicon in a groove is arranged in a plurality of L-shaped structures arranged in layers, and a voltage division cascade groove field plate structure is formed by connecting the first field plate polysilicons in the same layer through a voltage division ring. In this way, by increasing the number of voltage division cascade field plates in the unit groove depth, the electric field distribution in the drift region can be closer to a rectangular distribution, higher voltage resistance efficiency can be achieved, the area of the active region drift region can be increased, the resistivity of the drift region can be reduced, and the current density of the device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. Background Technology

[0002] In semiconductor device technology, trench-structured oxide-bypassed (OB) technology is widely used, such as in low- and medium-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) and trench MOS barrier Schottky (TMBS) devices. It is also employed in fast recovery diodes (FRDs) and insulated-gate bipolar transistors (IGBTs). Typical mass-produced products include shielded-gate trench MOSFETs (SGT-MOSFETs). In a trench field-plate structure, all conductors are at the same potential as the surface metal electrodes when the device is reverse-biased. Its disadvantage is the uneven electric field distribution within the drift region, which becomes more uneven with increasing trench depth. The charge coupling strength between floating field plates is related to the area between the plates. To achieve ideal charge coupling, the trench width needs to be significantly increased, thus hindering device optimization. For side-passed MOSFETs, the electric field distribution in the drift region is uneven, falling short of the superjunction structure. This led to the design concept of graded oxide-by-passed (GOB) structures, which can optimize the electric field distribution in the drift region, achieving an approximately rectangular distribution and maximizing breakdown voltage. However, this structure has drawbacks: firstly, its fabrication process is difficult; secondly, different breakdown voltages correspond to different field oxide thicknesses—the higher the breakdown voltage, the thicker the field oxide layer, thus limiting the achievable maximum breakdown voltage. Summary of the Invention

[0003] To overcome the aforementioned shortcomings in the prior art, the present application aims to provide a semiconductor device, the semiconductor device comprising:

[0004] Silicon wafers;

[0005] Multiple trenches located on the silicon wafer extending along a first direction, the first direction being from the terminal region to the active region;

[0006] A first insulating layer covering the inner wall of the trench;

[0007] The trench contains multiple L-shaped layers of first field plate polysilicon and second insulating layer, which are alternately stacked and nested. The first field plate polysilicon includes a first extension extending along a first direction and a second extension extending along a second direction, which is the thickness direction of the silicon wafer. The first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area. Adjacent first field plate polysilicon layers are isolated from each other by the second insulating layer. The trench opening exposes the first polysilicon exposure area of ​​the first field plate polysilicon.

[0008] A plurality of voltage dividing ring metals are located on one side of the trench opening, each of the voltage dividing ring metals electrically connecting the first polysilicon exposed area of ​​the first field plate polysilicon in the same layer.

[0009] In one possible implementation, the semiconductor device further includes:

[0010] A plurality of spaced voltage divider ring impurity regions are formed on one side of the trench opening, extending along a third direction, the third direction being perpendicular to the second direction and intersecting the first direction; one voltage divider ring impurity region corresponds to one first polysilicon exposure region;

[0011] The voltage divider ring metal electrically connects the first polysilicon exposed region of the first field plate polysilicon in the same layer and the corresponding voltage divider ring impurity region.

[0012] In one possible implementation, in the first direction, the voltage divider ring impurity region is located at the end of the first field plate polysilicon exposed near the active region at the trench opening corresponding to the voltage divider ring impurity region.

[0013] In one possible implementation, in the first direction, the first boundary of the voltage divider ring impurity region near the active region is located between the two first polysilicon exposed regions and is close to the first polysilicon exposed region corresponding to the voltage divider ring impurity region; in the first direction, the second boundary of the voltage divider ring impurity region away from the active region does not exceed the first polysilicon exposed region corresponding to the voltage divider ring impurity region.

[0014] In one possible implementation, the drift regions formed by the polysilicon of the plurality of first field plates have a greater length in the first direction than in the second direction.

[0015] In one possible implementation, the semiconductor device further includes:

[0016] The second field plate polysilicon is located in the L-shaped opening of the first field plate polysilicon closest to the trench opening. The second field plate polysilicon is rectangular and extends along the first direction. The second field plate polysilicon is isolated from the first field plate polysilicon by the second insulating layer.

[0017] The main junction impurity region located at the trench opening and corresponding to the polysilicon position of the second field plate;

[0018] The active region electrode metal is located on one side of the trench opening.

[0019] In one possible implementation, the semiconductor device further includes:

[0020] The gate polysilicon is located in the L-shaped opening of the first field plate polysilicon closest to the trench opening. The gate polysilicon is rectangular and extends along the first direction. The gate polysilicon is isolated from the first field plate polysilicon by a gate oxide layer.

[0021] The main junction impurity region and N+ source region are located at the trench opening and corresponding to the gate polysilicon position;

[0022] The active region electrode metal is located on one side of the trench opening.

[0023] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0024] Provide a silicon wafer;

[0025] Multiple trenches extending along a first direction are formed on the silicon wafer, the first direction being from the terminal region to the active region;

[0026] A first insulating layer is formed within the trench, covering the inner wall of the trench;

[0027] Multiple layers of first field plate polysilicon and second insulating layer are sequentially formed in the trench; the multiple layers of first field plate polysilicon and second insulating layer are alternately stacked and nested; the first field plate polysilicon includes a first extension extending along a first direction and a second extension extending along a second direction, the second direction being the thickness direction of the silicon wafer; the first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area; adjacent first field plate polysilicon is isolated from each other by the second insulating layer; the trench opening exposes the first polysilicon exposure area of ​​the first field plate polysilicon.

[0028] Multiple voltage dividing ring metals are formed on one side of the trench opening, and each voltage dividing ring metal electrically connects the first polysilicon exposed area of ​​the first field plate polysilicon in the same layer.

[0029] In one possible implementation, the step of sequentially forming a multilayer first field plate polysilicon and a second insulating layer in the trench includes repeatedly performing the following steps to form a multilayer first field plate polysilicon and a second insulating layer:

[0030] The trench is filled with an nth layer of polycrystalline silicon; where n is greater than or equal to 1.

[0031] The nth layer of polysilicon is partially etched, retaining the portion of the nth layer of polysilicon near the bottom of the trench and away from the active region, to form an L-shaped nth layer of first field plate polysilicon.

[0032] An insulating medium is deposited or polycrystalline silicon is oxidized in the trench to form a second insulating layer covering the inner side of the L-shaped opening of the first field plate in the nth layer.

[0033] This application also provides an electronic device, characterized in that the electronic device includes the semiconductor device provided within this community.

[0034] Compared with the prior art, this application has the following beneficial effects:

[0035] The semiconductor device, semiconductor device manufacturing method, and electronic device provided in this application embodiment are formed by setting the first field plate polysilicon in the trench in a multi-layered L-shaped structure, and connecting the first field plate polysilicon in the same layer with voltage divider rings to form a voltage divider cascaded trench field plate structure. In this way, by increasing the number of voltage divider cascaded field plates per unit trench depth, the electric field distribution in the drift region can be made closer to a rectangular distribution, achieving higher withstand voltage efficiency, thereby increasing the area of ​​the active drift region, reducing the resistivity of the drift region, and increasing the current density of the device. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 One of the schematic diagrams of the semiconductor device provided in this embodiment;

[0038] Figure 2 This is a second schematic diagram of the semiconductor device provided in this embodiment;

[0039] Figure 3 This is the third schematic diagram of the semiconductor device provided in this embodiment;

[0040] Figure 4 This is a schematic flowchart of the manufacturing method of the semiconductor device provided in this embodiment;

[0041] Figure 5 This is one of the schematic diagrams illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0042] Figure 6 This is a second schematic diagram illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0043] Figure 7 This is the third schematic diagram illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0044] Figure 8 This is the fourth schematic diagram illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0045] Figure 9 Fifth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0046] Figure 10 This is the sixth schematic diagram illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0047] Figure 11 This is the seventh schematic diagram illustrating the manufacturing process of the semiconductor device provided in this embodiment;

[0048] Figure 12 This is the eighth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0051] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0052] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0053] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0054] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0055] Please see Figure 1 and Figure 2 , Figure 1 and Figure 2 These are schematic diagrams of two semiconductor devices provided in this embodiment, wherein, Figure 1 The image shown is of a diode with a trench structure. Figure 2 The image shows a trench MOSFET device.

[0056] In this embodiment, the semiconductor device may mainly include a silicon wafer 100, a trench formed on the silicon wafer 100, an L-shaped multilayer first field plate polysilicon 131 in the trench, and a voltage dividing ring metal located on one side of the trench opening.

[0057] Specifically, a plurality of the trenches are located on the silicon wafer 100 and extend along a first direction D1, the first direction D1 being the direction from the terminal region to the active region. A first insulating layer 120 covering the inner wall of the trench is also provided within the trench.

[0058] The trench also contains multiple L-shaped first field plate polysilicon 131s and second insulating layers 140. These multiple layers of first field plate polysilicon 131s and second insulating layers 140 are alternately stacked and nested. Each first field plate polysilicon 131 includes a first extension extending along a first direction D1 and a second extension extending along a second direction D2, where D2 is the thickness direction of the silicon wafer 100. The first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area. Adjacent first field plate polysilicon 131s are isolated from each other by the second insulating layer 140. The trench opening exposes the first polysilicon exposure area of ​​the first field plate polysilicon 131.

[0059] For example, the (n+1)th layer of first field plate polysilicon 131, which is relatively closer to the trench opening, is located in the L-shaped opening of the nth layer of first field plate polysilicon 131, which is relatively closer to the bottom of the trench. The first extensions of a plurality of first field plate polysilicon 131 are stacked and arranged in a direction from the bottom of the trench to the trench opening, and the second extensions of a plurality of first field plate polysilicon 131 are arranged sequentially in a direction from the terminal region to the active region. Adjacent first field plate polysilicon 131 are isolated from each other by the second insulating layer 140.

[0060] Multiple voltage divider rings are located on one side of the trench opening, and each voltage divider ring electrically connects the first polysilicon exposed area of ​​the first field plate polysilicon 131 on the same layer. For example, a second insulating layer 140 covering the trench opening is also provided on one side of the trench opening, and the voltage divider rings are located on the side of the second insulating layer 140 away from the silicon wafer 100. The voltage divider rings extend through a first contact hole 201 penetrating the second insulating layer 140 to make electrical contact with the first field plate polysilicon 131.

[0061] In one possible implementation, the semiconductor device may further include a plurality of voltage divider ring impurity regions 160. The plurality of spaced-apart voltage divider ring impurity regions 160 are formed on one side of the trench opening and extend along a third direction D3, which is perpendicular to the second direction D2 and intersects the first direction D1. Each voltage divider ring impurity region corresponds to the first polysilicon exposed area of ​​the first field plate polysilicon 131 in the same layer. Preferably, the third direction D3 is perpendicular to both the first direction D1 and the second direction D2.

[0062] The voltage divider ring metal electrically connects the first polysilicon exposed region of the first field plate polysilicon 131 in the same layer and the corresponding voltage divider ring impurity region. For example, the voltage divider ring metal extends through the second contact hole 202 penetrating the second insulating layer 140 to make electrical contact with the voltage divider ring impurity region, thereby electrically connecting the first polysilicon exposed region of the first field plate polysilicon 131 in the same layer and the corresponding voltage divider ring impurity region.

[0063] Based on the above design, the semiconductor device provided in this embodiment forms a voltage-dividing cascaded trench field plate structure by arranging the first field plate polysilicon 131 in the trench into multiple stacked L-shaped structures and connecting the first field plate polysilicon 131 in the same layer through voltage divider rings. In this way, by increasing the number of voltage-dividing cascaded field plates per unit trench depth, the electric field distribution in the drift region can be made closer to a rectangular distribution, achieving higher breakdown voltage efficiency. This increases the area of ​​the active drift region, reduces the resistivity of the drift region, and improves the current density of the device.

[0064] In one possible implementation, please refer to Figure 3 In the first direction D1, the voltage divider ring impurity region 160 is located at the end of the first field plate polysilicon 131 exposed at the trench opening corresponding to the voltage divider ring impurity region 160, near the active region.

[0065] Furthermore, in the first direction D1, the first boundary of the voltage divider ring impurity region 160 near the active region is located between the two first polysilicon exposed regions, and is close to the first polysilicon exposed region corresponding to the voltage divider ring impurity region 160. In the first direction D1, the second boundary of the voltage divider ring impurity region 160 away from the active region does not exceed the first polysilicon exposed region corresponding to the voltage divider ring impurity region 160.

[0066] In one possible implementation, please refer again. Figure 1 and Figure 2 The length W1 of the drift region formed by the plurality of first field plate polysilicon 131 in the first direction D1 is greater than the length W2 in the second direction D2.

[0067] Please refer to this again. Figure 1 For trench diodes, the semiconductor device further includes a second field plate polysilicon 132, a main junction impurity region 170, and an active region electrode metal 220.

[0068] The second field plate polysilicon 132 is located in the L-shaped opening of the first field plate polysilicon 131 closest to the trench opening. The second field plate polysilicon 132 is rectangular and extends along the first direction D1. The second field plate polysilicon 132 is isolated from the first field plate polysilicon 131 by the second insulating layer 140.

[0069] The main junction impurity region 170 is located at the trench opening and corresponds to the position of the second field plate polysilicon 132. For example, the main junction impurity region 170 may extend along the third direction D3 and correspond to the positions of the second field plate polysilicon 132 exposed by the plurality of trenches.

[0070] The active region electrode metal 220 is located on one side of the trench opening. For example, the active region electrode metal 220 may be located on the side of the third insulating layer 200 away from the silicon wafer 100, and electrically contact the main junction impurity region 170 through the third contact hole 203 of the third insulating layer 200.

[0071] In addition, the semiconductor device may also include another electrode layer (not shown) located on the side of the silicon wafer 100 away from the trench opening and other components, which will not be described in detail here.

[0072] Please refer to this again. Figure 2 For trench MOSFET devices, the semiconductor device further includes a gate polysilicon 133, a main junction impurity region 170, an N+ source region 180, and an active region electrode metal 220.

[0073] The gate polysilicon 133 is located in the L-shaped opening of the first field plate polysilicon 131 closest to the trench opening. The gate polysilicon 133 is rectangular and extends along the first direction D1. The gate polysilicon 133 is isolated from the first field plate polysilicon 131 by a gate oxide layer.

[0074] The main junction impurity region 170 and the N+ source region 180 are located at the trench opening and correspond to the position of the gate polysilicon 133.

[0075] The active region electrode metal 220 is located on one side of the trench opening. For example, the active region electrode metal 220 may be located on the side of the third insulating layer 200 away from the silicon wafer 100, and electrically contact the main junction impurity region 170 and the N+ source region 180 through the third contact hole 203 of the third insulating layer 200. The active region electrode metal 220 may also electrically contact the first polysilicon exposed area of ​​the first field plate polysilicon 131 closest to the trench opening through a first contact hole 201.

[0076] Please refer to Figure 4This embodiment also provides a method for manufacturing a semiconductor device, and the steps of the method are described in detail below.

[0077] Step S110: Provide a silicon wafer 100.

[0078] In this embodiment, the silicon wafer 100 can be an N-type silicon wafer 100. For example, the silicon wafer 100 can include a single wafer or an epitaxial wafer.

[0079] Step S120: A plurality of trenches 110 extending along a first direction D1 are formed on the silicon wafer 100, wherein the first direction D1 is the direction from the terminal region to the active region.

[0080] Please refer to Figure 5 In this embodiment, a plurality of trenches 110 can be formed on the silicon wafer 100 by etching.

[0081] Step S130: A first insulating layer 120 is formed in the trench, covering the inner wall of the trench.

[0082] Please refer to Figure 6 In this embodiment, a field oxide layer can be formed by surface deposition or thermal oxidation as the first insulating layer 120.

[0083] Step S140, a multilayer first field plate polysilicon 131 and a second insulating layer 140 are sequentially formed in the trench.

[0084] Multiple layers of first field plate polysilicon 131 and second insulating layer 140 are alternately stacked and nested. The first field plate polysilicon 131 includes a first extension extending along a first direction D1 and a second extension extending along a second direction D2, where the second direction D2 is the thickness direction of the silicon wafer 100. The first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area. Adjacent first field plate polysilicon 131 are isolated from each other by the second insulating layer 140. The first field plate polysilicon 131 of the same layer exposed at the openings of the plurality of trenches forms a first polysilicon exposure area.

[0085] In step S150, a plurality of voltage dividing ring metals are formed on one side of the trench opening, and each voltage dividing ring metal electrically connects the first polysilicon exposed area of ​​the first field plate polysilicon 131 in the same layer.

[0086] Specifically, in step S140, the following steps can be repeated to form a multilayer first field plate polysilicon 131 and a second insulating layer 140.

[0087] The trench is filled with an nth layer of polysilicon, where n is greater than or equal to 1. The nth layer of polysilicon is then partially etched, retaining the portion near the bottom of the trench and away from the active region, forming an L-shaped first field plate polysilicon layer 131. An insulating dielectric is then deposited or polysilicon is oxidized within the trench to form a second insulating layer 140 covering the inner side of the L-shaped opening of the nth layer of first field plate polysilicon 131.

[0088] Specifically, please refer to Figure 7 After step S140, the first layer of polysilicon 130 can be filled into the trench, and the polysilicon 130 on one side of the trench opening can be removed.

[0089] Then please see Figure 8 The first layer of polysilicon 130 filled by photolithography can be partially etched, retaining the portion near the bottom of the trench and away from the active region, so as to form an L-shaped first layer of first field plate polysilicon 131.

[0090] Then please see Figure 9 An insulating dielectric can be deposited in the trench or polycrystalline silicon can be oxidized to form an insulating dielectric located in the trench as the second insulating layer 140.

[0091] Then please see Figure 10 The second layer of polysilicon 130 can be refilled into the trench, and the polysilicon 130 on one side of the trench opening can be removed. Then, the above steps are repeated to locally etch the second layer of polysilicon 130, re-form the second insulating layer 140, and refill the third layer of polysilicon (e.g., ...). Figure 11 (As shown). Similarly, multiple layers of the first field plate polysilicon 131 and the second insulating layer 140 can be formed.

[0092] For diode devices, after step S140, local impurity doping can be formed on the surface using photolithography and ion implantation to form a main junction region and a voltage divider ring impurity region 160, or a barrier region such as silicide can be formed. Then, an insulating dielectric layer such as an oxide layer is deposited on the surface on one side of the trench opening to form the third insulating layer 200. Then, a third contact hole 203 exposing the source region, a second contact hole 202 exposing the voltage divider ring impurity region 160, and a second contact hole 202 exposing the first field plate polysilicon 131 are formed using photolithography and etching processes. Then, in step S150, metal is deposited on the side of the third insulating layer 200 away from the silicon wafer 100, and the active region electrode metal 220 and the voltage divider ring metal are formed using photolithography and etching processes to form... Figure 1 The structure shown.

[0093] For trench MOSFET devices, after step S140, the polysilicon in the trench can be partially removed by photolithography and etching, and the field oxide layer can be partially removed by wet etching. Then, a gate oxide layer can be formed by deposition or thermal oxidation. Polysilicon is then deposited to form the gate polysilicon 133. Local impurity doping is then formed on the surface using photolithography and ion implantation to form the main junction region and voltage divider ring impurity region 160, or a silicide barrier region. Then, local impurity doping is formed on the surface using photolithography and ion implantation to form the N+ source region 180. An insulating dielectric layer such as an oxide layer is then deposited on the surface on one side of the trench opening to form the third insulating layer 200. The first contact hole 201, the second contact hole 202, and the third contact hole 203 are formed using photolithography and etching. Then, in step S150, metal is deposited on the side of the third insulating layer 200 away from the silicon wafer 100, and the active region electrode metal 220 and the voltage divider ring metal are formed using photolithography and etching. Figure 2 The structure shown.

[0094] This application also provides an electronic device, which includes the semiconductor device described in this application.

[0095] In summary, the semiconductor device, semiconductor device manufacturing method, and electronic device provided in this application embodiment, by setting the first field plate polysilicon in the trench in a multi-layered L-shaped structure, and connecting the first field plate polysilicon in the same layer with voltage divider rings to form a voltage divider cascaded trench field plate structure, thereby increasing the number of voltage divider cascaded field plates per unit trench depth, can make the electric field distribution in the drift region closer to a rectangular distribution, achieving higher withstand voltage efficiency, thereby increasing the area of ​​the active drift region, reducing the resistivity of the drift region, and increasing the current density of the device.

[0096] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0097] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Silicon wafers; Multiple trenches located on the silicon wafer extending along a first direction, the first direction being from the terminal region to the active region; A first insulating layer covering the inner wall of the trench; The trench contains multiple L-shaped layers of first field plate polysilicon and second insulating layer, which are alternately stacked and nested. The first field plate polysilicon includes a first extension extending along a first direction and a second extension extending along a second direction, which is the thickness direction of the silicon wafer. The first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area. Adjacent first field plate polysilicon layers are isolated from each other by the second insulating layer. The trench opening exposes the first polysilicon exposure area of ​​the first field plate polysilicon. Multiple voltage dividing ring metals located on one side of the trench opening, each of the voltage dividing ring metals electrically connecting the first polysilicon exposed area of ​​the first field plate polysilicon in the same layer.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Multiple spaced voltage-dividing ring impurity regions are formed on one side of the trench opening, extending along a third direction, the third direction being perpendicular to the second direction and intersecting the first direction; one of the voltage-dividing ring impurity regions corresponds to the first polysilicon exposure area of ​​the first field plate polysilicon in the same layer; The voltage divider ring metal electrically connects the first polysilicon exposed region of the first field plate polysilicon in the same layer and the corresponding voltage divider ring impurity region.

3. The semiconductor device according to claim 2, characterized in that, In the first direction, the voltage divider ring impurity region is located at the end of the first field plate polysilicon exposed near the active region at the trench opening corresponding to the voltage divider ring impurity region.

4. The semiconductor device according to claim 3, characterized in that, In the first direction, the first boundary of the voltage divider ring impurity region near the active region is located between the two first polysilicon exposed regions and is close to the first polysilicon exposed region corresponding to the voltage divider ring impurity region; in the first direction, the second boundary of the voltage divider ring impurity region away from the active region does not exceed the first polysilicon exposed region corresponding to the voltage divider ring impurity region.

5. The semiconductor device according to claim 1, characterized in that, The length of the drift region formed by the polycrystalline silicon of the first field plate is greater in the first direction than in the second direction.

6. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: The second field plate polysilicon is located in the L-shaped opening of the first field plate polysilicon closest to the trench opening. The second field plate polysilicon is rectangular and extends along the first direction. The second field plate polysilicon is isolated from the first field plate polysilicon by the second insulating layer. The main junction impurity region located at the trench opening and corresponding to the polysilicon position of the second field plate; The active region electrode metal located on one side of the trench opening.

7. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: The gate polysilicon is located in the L-shaped opening of the first field plate polysilicon closest to the trench opening. The gate polysilicon is rectangular and extends along the first direction. The gate polysilicon is isolated from the first field plate polysilicon by a gate oxide layer. The main junction impurity region and N+ source region are located at the trench opening and corresponding to the gate polysilicon position; The active region electrode metal located on one side of the trench opening.

8. A method for manufacturing a semiconductor device, characterized in that, The method includes: Provide a silicon wafer; Multiple trenches extending along a first direction are formed on the silicon wafer, the first direction being from the terminal region to the active region; A first insulating layer is formed within the trench, covering the inner wall of the trench; Multiple layers of first field plate polysilicon and second insulating layer are sequentially formed in the trench; the multiple layers of first field plate polysilicon and second insulating layer are alternately stacked and nested; the first field plate polysilicon includes a first extension extending along a first direction and a second extension extending along a second direction, the second direction being the thickness direction of the silicon wafer; the first extension is located near the bottom of the trench, and the second extension is located at the end of the first extension near the terminal area; adjacent first field plate polysilicon is isolated from each other by the second insulating layer; the trench opening exposes the first polysilicon exposure area of ​​the first field plate polysilicon. Multiple voltage dividing ring metals are formed on one side of the trench opening, and each voltage dividing ring metal electrically connects the first polysilicon exposed area of ​​the first field plate polysilicon in the same layer.

9. The method according to claim 8, characterized in that, The step of sequentially forming a multilayer first field plate polysilicon and a second insulating layer in the trench includes repeatedly performing the following steps to form a multilayer first field plate polysilicon and a second insulating layer: The trench is filled with an nth layer of polycrystalline silicon; where n is greater than or equal to 1. The nth layer of polysilicon is partially etched, retaining the portion of the nth layer of polysilicon near the bottom of the trench and away from the active region, to form an L-shaped nth layer of first field plate polysilicon. An insulating medium is deposited or polycrystalline silicon is oxidized in the trench to form a second insulating layer covering the inner side of the L-shaped opening of the first field plate in the nth layer.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-7.

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