Timing circuit, chip and electronic product
By designing a timing circuit that can detect the dangling state of the external port and lock the output signal, the problem of high cost and troublesome use when the timing function is not required in the prior art is solved, and the effect of simplicity of operation and cost saving is achieved.
Patent Information
- Application Number
- CN202411424356.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-02-11
Smart Images
Figure CN119420328A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a timing circuit, a chip and an electronic product. Background Art
[0002] Timer circuits are often used in integrated circuits. Generally, timer circuits charge the capacitor connected to the chip through a constant current source. The time it takes for the voltage on the capacitor to reach the specified voltage value is the timing time. The timing time can be changed by changing the capacitance value of this external capacitor.
[0003] For applications that do not require a timing function, the timer circuit does not require an external capacitor, but the external port must be grounded through a solder joint or a wire tie. The solder joint and the wire tie increase the cost and are inconvenient to use.
[0004] Therefore, how to reduce the cost and facilitate use when the timing function is not needed has become one of the problems that those skilled in the art need to solve urgently.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a timing circuit, chip and electronic product for solving the problem in the prior art that when the timing function of the timing circuit is not needed, it must be grounded through solder joints or wires, resulting in increased costs and inconvenience in use.
[0007] To achieve the above-mentioned and other related purposes, the present invention provides a timing circuit, which at least comprises:
[0008] Timing module, comparison module and timing end signal generating module;
[0009] The timing module is controlled by a timing start signal, and starts timing when the timing start signal is valid;
[0010] The comparison module is connected to the output end of the timing module, detects the output voltage of the timing module, and outputs a timing end prediction signal when the output voltage of the timing module reaches the reference voltage;
[0011] The timing end signal generating module is connected to the output end of the comparison module and receives the timing start signal; when the output end of the timing module is externally connected to a capacitor, if the timing start signal and the timing end prediction signal are both valid, a valid timing end signal is output, otherwise an invalid timing end signal is output; when the output end of the timing module is grounded or suspended, an invalid timing end signal is output.
[0012] Optionally, the timing module includes a current source and a pull-down tube; the first end of the current source is connected to the power supply voltage, and the second end is grounded via the pull-down tube; the control end of the pull-down tube receives the timing start signal; the second end of the current source serves as the output end of the timing module.
[0013] More optionally, the pull-down tube is an NMOS tube, a drain of the NMOS tube is connected to the second end of the current source, a source is grounded, and a gate is connected to the timing start signal.
[0014] Optionally, the non-phase input terminal of the comparison module is connected to the output terminal of the timing module, the inverting input terminal is connected to the reference voltage, and the output terminal outputs the timing end prediction signal.
[0015] More optionally, the timing end signal generating module includes a hanging detection unit and a logic unit;
[0016] The hanging detection unit is connected to the output end of the comparison module and receives the timing start signal. When the output end of the timing module is hanging, it outputs a valid detection signal; when the output end of the timing module is grounded or connected to an external capacitor, it outputs an invalid detection signal.
[0017] The first input end of the logic unit is connected to the output end of the comparison module, and the second input end is connected to the output end of the hanging detection unit; when the detection signal is valid, the logic unit locks the timing end signal to an invalid state based on the detection signal; when the detection signal is invalid, the logic unit generates the timing end signal based on the timing end prediction signal.
[0018] More optionally, the suspension detection unit includes a delay unit, an OR gate, an inverter and an RS trigger;
[0019] The delay unit receives the timing start signal, and outputs a delayed pulse signal or a delayed signal of the timing start signal when the timing start signal is valid, wherein the delay duration of the delay unit is less than the timing duration of the timing circuit;
[0020] The first input end of the OR gate is connected to the output end of the comparison module, the second input end is connected to the output end of the delay unit, and outputs the result of the OR logic operation;
[0021] The inverter receives the timing start signal and outputs an inverted signal of the timing start signal;
[0022] The set end of the RS trigger is connected to the output end of the OR gate, and the reset end is connected to the output end of the inverter, so as to output the detection signal.
[0023] More optionally, the logic unit is an AND gate.
[0024] Optionally, the timing circuit further includes an external capacitor, one end of the capacitor is connected to the output end of the timing module, and the other end is grounded.
[0025] In order to achieve the above-mentioned object and other related objects, the present invention also provides a chip, which at least includes: the above-mentioned timing circuit.
[0026] In order to achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned timing circuit or the above-mentioned chip.
[0027] As described above, the timing circuit, chip and electronic product of the present invention have the following beneficial effects:
[0028] The timing circuit, chip and electronic product of the present invention detect the suspended state of the external port. When it is detected that the external port is in the suspended state, the output signal of the timing circuit is locked to an invalid state to avoid affecting the subsequent circuits. Furthermore, when the timing function is not needed, the external port can be suspended, which is easy to operate and saves costs.
[0029] The timing circuit, chip and electronic product of the present invention can also lock the output signal of the timing circuit into an invalid state when the external port is grounded, and are flexible to use and highly selective. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 Shown is a schematic diagram of the structure of a timing circuit.
[0031] Figure 2 Display as Figure 1 Waveform diagram of the timing circuit.
[0032] Figure 3 Shown is a schematic structural diagram of the timing circuit of the present invention.
[0033] Figure 4 It is a schematic diagram of waveforms when the timing circuit of the present invention is connected to an external capacitor to perform a timing function.
[0034] Figure 5 It is a waveform diagram showing when the external port of the timing circuit of the present invention is grounded and does not perform the timing function.
[0035] Figure 6 It is a waveform diagram showing when the external port of the timing circuit of the present invention is left floating and does not perform the timing function.
[0036] Component number description
[0037] 1 Timing circuit
[0038] 11 Current Source
[0039] 12 NMOS tube
[0040] 13. Comparator
[0041] 2 Timing Circuit
[0042] 21 Timing Module
[0043] 211 Current Source
[0044] 212 pull-down tube
[0045] 22 Comparison Module
[0046] 23 Timing end signal generation module
[0047] 231 suspension detection unit
[0048] 231a Delay Unit
[0049] 231b OR Gate
[0050] 231c Inverter
[0051] 231d RS Flip Flop
[0052] 232 logic units DETAILED DESCRIPTION
[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0054] See also Figure 1 to Figure 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0055] like Figure 1The figure shows a timing circuit 1, which includes a current source 11, an NMOS tube 12, a comparator 13 and an external capacitor C1. The current source 11 is grounded through the NMOS tube 12; the upper plate of the external capacitor C1 is connected to the connection node between the current source 11 and the NMOS tube 12, and the lower plate is grounded; the positive input terminal of the comparator 13 is connected to the upper plate of the external capacitor C1, and the negative input terminal is connected to the preset voltage Vr, and the output signal Output is used as an indication signal of the end of timing.
[0056] The NMOS tube 12 is controlled by the control signal F0; Figure 1 and Figure 2 As shown, when the control signal F0 is invalid (high level), the NMOS tube 12 is turned on, and the voltage value Vc of the external port is 0V when the control signal F0 is valid (from high level to low level), the NMOS tube 12 changes from the on state to the off state; the current source 11 charges the external capacitor C1, and the voltage value Vc on the external capacitor C1 rises linearly from 0V; when the voltage value Vc on the external capacitor C1 rises to a value greater than the preset voltage Vr, the output signal Output of the comparator 13 changes from a low level to a high level (indicating that the timing duration has been reached). When the control signal F0 is invalid again, the timing circuit 1 is reset, the voltage value Vc on the external capacitor C1 is pulled down to 0V, and the output signal Output of the comparator 13 jumps to a low level.
[0057] When the external capacitor C1 is charged, the time taken for the voltage value Vc on the external capacitor C1 to rise from 0 to the preset voltage Vr is the timing duration Tr, which satisfies Tr=C1*Vr / Ir, where C1 is the capacitance of the external capacitor, Vr is the preset voltage value, and Ir is the value of the current source. By changing the capacitance of the external capacitor C1, different timing durations can be set. When the system application does not require the timing function, it is necessary to set the timing duration Tr to infinity, and the external port can be connected to the ground line; at this time, the voltage value Vc on the external capacitor C1 is always maintained at 0, and the output signal Output of the comparator 13 is maintained at a low level. If the external port is suspended, it is equivalent to the capacitance of the external capacitor C1 being 0, and the timing duration is 0. Therefore, the external port cannot be suspended, and additional cost expenditure is required when the timing function is not required, and the operation is cumbersome.
[0058] In order to solve the above problem, the present invention provides a timing circuit, when the timing function is not needed, the external port can be left floating, thereby reducing costs and facilitating use.
[0059] like Figure 3 As shown, the timing circuit 2 of the present invention comprises: a timing module 21 , a comparison module 22 and a timing end signal generating module 23 .
[0060] like Figure 3 As shown, the timing module 21 is controlled by the timing start signal S0 and starts timing when the timing start signal S0 is valid.
[0061] As an example, in this embodiment, the timing module 21 includes a current source 211 and a pull-down tube 212. The first end of the current source 211 is connected to the power supply voltage, and the second end is grounded via the pull-down tube 212; the control end of the pull-down tube 212 receives the timing start signal S0; the second end of the current source 211 serves as the output end of the timing module 21. As an example, the pull-down tube 212 adopts an NMOS tube, then the drain of the NMOS tube is connected to the second end of the current source 211, the source is grounded, and the gate is connected to the timing start signal S0; in this example, the timing start signal S0 is valid at a low level. In actual use, the timing module 21 can be set to any circuit structure that can perform timing based on an external capacitor as needed, and is not limited to this embodiment.
[0062] like Figure 3 As shown, the comparison module 22 is connected to the output end of the timing module 21, detects the output voltage of the timing module 21, and outputs a timing end prediction signal S1 when the output voltage of the timing module 21 reaches the reference voltage Vref.
[0063] Specifically, in this embodiment, the non-inverting input terminal of the comparison module 22 is connected to the output terminal of the timing module 21, the inverting input terminal is connected to the reference voltage Vref, and the output terminal outputs the timing end prediction signal; when the output voltage of the timing module 21 is greater than the reference voltage, the comparison module 22 outputs a high level (the timing end prediction signal S1 is valid), and when the output voltage of the timing module 21 is less than the reference voltage, the comparison module 22 outputs a low level (the timing end prediction signal S1 is invalid). In actual use, the corresponding relationship between the input polarity of the comparison module 22 and the input signal can be adjusted by adding an inverter, which will not be described one by one here.
[0064] like Figure 3 As shown, the timing end signal generating module 23 is connected to the output end of the comparison module 22 and receives the timing start signal S0; when the output end of the timing module 21 is externally connected to a capacitor, if the timing start signal S0 and the timing end prediction signal S1 are both valid, a valid timing end signal Output is output, otherwise an invalid timing end signal Output is output; when the output end of the timing module 21 is grounded or suspended, an invalid timing end signal Output is output.
[0065] Specifically, in this embodiment, the timing end signal generating module 23 includes a floating detection unit 231 and a logic unit 232 .
[0066] More specifically, the suspension detection unit 231 is connected to the output end of the comparison module 22, and receives the timing start signal S0, and determines whether the output end of the timing module 21 is suspended based on the timing start signal S0 and the timing end prediction signal S1; in this example, if the timing end prediction signal S1 is in a valid state when the timing starts, it means that the output end of the timing module 21 is suspended, and the suspension detection unit 231 outputs a valid detection signal S5; if the timing end prediction signal S1 is in an invalid state when the timing starts, it means that the output end of the timing module 21 is grounded or connected to an external capacitor, and the suspension detection unit 231 outputs an invalid detection signal. Any circuit structure that can realize the function of the suspension detection unit 231 of the present invention is applicable to the present invention, and will not be described one by one here; as an example, the suspension detection unit 231 includes a delay unit 231a, an OR gate 231b, an inverter 231c and an RS trigger 231d. The delay unit 231a receives the timing start signal S0, and outputs a delayed pulse signal or a delayed signal S2 of the timing start signal S0 when the timing start signal S0 is valid, wherein the delay time length Td of the delay unit 231a is less than the timing time length Ts of the timing circuit 2, that is, 0<Td<Ts. The first input end of the OR gate 231b is connected to the output end of the comparison module 22, and the second input end is connected to the output end of the delay unit 231a, and the OR logic operation result S3 is output. The inverter 231c receives the timing start signal S0, and outputs the inverse signal S4 of the timing start signal S0. The set end S of the RS flip-flop 231d is connected to the output end of the OR gate 231b, and the reset end R is connected to the output end of the inverter 231c, and the detection signal S5 is output.
[0067] More specifically, the first input terminal of the logic unit 232 is connected to the output terminal of the comparison module 22, and the second input terminal is connected to the output terminal of the dangling detection unit 231; when the detection signal S5 is valid, the logic unit 232 locks the timing end signal Output to an invalid state based on the detection signal S5; when the detection signal S5 is invalid, the logic unit 232 generates the timing end signal Output based on the timing end prediction signal S1 (that is, without considering the detection signal S5, if the timing end prediction signal S1 is valid, the timing end signal Output is valid and the timing ends; if the timing end prediction signal S1 is invalid, the timing end signal Output is invalid and the timing does not end). Any circuit structure that can realize the functions of the logic unit 232 of the present invention is applicable to the present invention, and will not be described one by one here; as an example, the logic unit 232 is implemented using an AND gate.
[0068] The present invention further provides a chip, which at least includes the timing circuit 2 (excluding the external capacitor), that is, the timing module 21, the comparison module 22 and the timing end signal generating module 23 are integrated into the chip.
[0069] It should be noted that when the timing function of the timing circuit 2 of the present invention is not used, the output terminal (external port) of the timing module 21 is grounded or floating; preferably, it is set to float, thereby reducing costs. When the timing circuit 2 of the present invention needs to perform the timing function, it further includes an externally connected capacitor C2. One end of the capacitor C2 is connected to the output terminal of the timing module 21, and the other end is grounded. By changing the capacitance value of the capacitor C2, the setting of the timing duration Ts can be achieved.
[0070] In the case of connecting the capacitor C2 to the external port to perform the timing function:
[0071] As Figure 4 shown, when the timing start signal S0 is at a high level (invalid), the pull-down transistor 212 is turned on, and the capacitor C2 is quickly discharged until the voltage value Vc of the external port is 0V; the comparison module 22 outputs a low level (the timing end pre-judgment signal S1 is invalid). At the same time, the inverted signal S4 of the timing start signal S0 received by the reset terminal R of the RS flip-flop 231d is at a low level, and the detection signal S5 output by the RS flip-flop 231d is cleared to a low level. Since both input signals of the logic unit 232 (AND gate) are at low levels, the timing end signal Output is at a low level (invalid).
[0072] As Figure 4 shown, when the timing start signal S0 changes from a high level to a low level (valid), the pull-down transistor 212 changes from the on state to the off state, and the current source 211 charges the capacitor C2, and the voltage value Vc on the capacitor C2 linearly rises from 0V. The falling edge of the timing start signal S0 generates a low-level delay pulse signal S2 (which can also be a low-level signal, triggering the RS flip-flop 231d based on the falling edge) after passing through the delay time Td of the delay unit 231a. Since Td < Ts, when the delay unit 231a outputs a narrow low-level pulse signal, the delay pulse signal S2 output by the comparison module 22 is still at a low level, and the operation result S3 output by the OR gate 231b is a low pulse signal, so that the detection signal S5 output by the RS flip-flop 231d is set to a high level. When the Vc voltage rises above the reference voltage Vref, the comparison module 22 outputs a high level (the timing end pre-judgment signal S1 is valid); since both input signals of the logic unit 232 are at high levels, the timing end signal Output is at a high level (valid), and the timing ends. Among them, when the capacitor C2 is charged, the time taken for the voltage value Vc on the capacitor C2 to rise from 0 to the reference voltage Vref is the timing duration Ts, which satisfies Ts = C2 * Vref / Is, where C2 is the capacitance value of the capacitor, Vref is the voltage value of the reference voltage, and Is is the current value of the current source.
[0073] In the case of grounding the external port and not requiring the timing function:
[0074] As Figure 5 As shown, at this time, the voltage Vc of the external port is always maintained at 0V, the output signal of the comparison module 22 remains at a low level, the timing end prediction signal S1 is invalid, the timing end signal Output output by the logic unit 232 remains at a low level (invalid), and the timing duration Ts is set to infinity.
[0075] When the external port is left unconnected and the timing function is not required:
[0076] like Figure 6 As shown, when the external port is suspended, the capacitance of the capacitor C2 is equivalent to 0. After the timing start signal S0 changes from a high level to a low level, the timing end prediction signal S1 output by the comparison module 22 changes from a low level to a high level, so that the operation result S3 output by the OR gate 231b is maintained at a high level, and the detection signal S5 output by the RS trigger 231d is maintained at a low level; the timing end signal Output output by the logic unit 232 is maintained at a low level (invalid), and the timing duration Ts is set to infinity.
[0077] Due to the setting of the timing end signal generating module 23 of the present invention, the external port that should be connected to the capacitor C2 can be left suspended when the timing function is not used. At this time, the timing duration Ts is set to be infinite, which does not affect the normal operation of the subsequent circuit. For the patch PCB circuit board, the present invention can omit a welding point; for the wire binding circuit, the present invention can save a wire binding, save costs, and is also convenient to use.
[0078] The present invention further provides an electronic product, which includes: the timing circuit 2 of the present invention (including capacitor C2 or excluding capacitor C2) or the chip of the present invention. The electronic product includes but is not limited to mobile phones, watches, computers, tablets, which are not described one by one here.
[0079] In summary, the present invention provides a timing circuit, chip and electronic product, including: a timing module, a comparison module and a timing end signal generating module; the timing module is controlled by a timing start signal, and starts timing when the timing start signal is valid; the comparison module is connected to the output end of the timing module, detects the output voltage of the timing module, and outputs a timing end prediction signal when the output voltage of the timing module reaches a reference voltage; the timing end signal generating module is connected to the output end of the comparison module and receives the timing start signal; when the output end of the timing module is externally connected to a capacitor, if the timing start signal and the timing end prediction signal are both valid, a valid timing end signal is output, otherwise an invalid timing end signal is output; when the output end of the timing module is grounded or suspended, an invalid timing end signal is output. The timing circuit, chip and electronic product of the present invention detect the suspended state of the external port, and when it is detected that the external port is in a suspended state, the output signal of the timing circuit is locked to an invalid state to avoid affecting the subsequent circuit, and then when the timing function is not needed, the external port can be suspended, which is easy to operate and saves costs. In addition, the timing circuit, chip and electronic product of the present invention can also lock the output signal of the timing circuit to an invalid state when the external port is grounded, and is flexible to use and highly selective. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high industrial utilization value.
[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A timing circuit, characterized in that: The timing circuit at least comprises: Timing module, comparison module and timing end signal generating module; The timing module is controlled by a timing start signal, and starts timing when the timing start signal is valid; The comparison module is connected to the output end of the timing module, detects the output voltage of the timing module, and outputs a timing end prediction signal when the output voltage of the timing module reaches the reference voltage; The timing end signal generating module is connected to the output end of the comparison module and receives the timing start signal; when the output end of the timing module is externally connected to a capacitor, if the timing start signal and the timing end prediction signal are both valid, a valid timing end signal is output, otherwise an invalid timing end signal is output; when the output end of the timing module is grounded or suspended, an invalid timing end signal is output.
2. The timing circuit according to claim 1, characterized in that: The timing module includes a current source and a pull-down tube; the first end of the current source is connected to the power supply voltage, and the second end is grounded via the pull-down tube; the control end of the pull-down tube receives the timing start signal; the second end of the current source serves as the output end of the timing module.
3. The timing circuit according to claim 2, characterized in that: The pull-down tube is an NMOS tube, a drain of the NMOS tube is connected to the second end of the current source, a source is grounded, and a gate is connected to the timing start signal.
4. The timing circuit according to claim 1, characterized in that: The non-phase input terminal of the comparison module is connected to the output terminal of the timing module, the inverting input terminal is connected to the reference voltage, and the output terminal outputs the timing end prediction signal.
5. The timing circuit according to any one of claims 1 to 4, characterized in that: The timing end signal generating module includes a hanging detection unit and a logic unit; The hanging detection unit is connected to the output end of the comparison module and receives the timing start signal. When the output end of the timing module is hanging, it outputs a valid detection signal; when the output end of the timing module is grounded or connected to an external capacitor, it outputs an invalid detection signal. The first input end of the logic unit is connected to the output end of the comparison module, and the second input end is connected to the output end of the hanging detection unit; when the detection signal is valid, the logic unit locks the timing end signal to an invalid state based on the detection signal; when the detection signal is invalid, the logic unit generates the timing end signal based on the timing end prediction signal.
6. The timing circuit according to claim 5, characterized in that: The hanging detection unit includes a delay unit, an OR gate, an inverter and an RS trigger; The delay unit receives the timing start signal, and outputs a delayed pulse signal or a delayed signal of the timing start signal when the timing start signal is valid, wherein the delay duration of the delay unit is less than the timing duration of the timing circuit; The first input end of the OR gate is connected to the output end of the comparison module, the second input end is connected to the output end of the delay unit, and outputs the result of the OR logic operation; The inverter receives the timing start signal and outputs an inverted signal of the timing start signal; The set end of the RS trigger is connected to the output end of the OR gate, and the reset end is connected to the output end of the inverter, so as to output the detection signal.
7. The timing circuit according to claim 5, characterized in that: The logic unit is an AND gate.
8. The timing circuit according to claim 1, characterized in that: The timing circuit also includes an external capacitor, one end of which is connected to the output end of the timing module, and the other end of which is grounded.
9. A chip, characterized in that: The chip at least comprises: a timing circuit as described in any one of claims 1-7.
10. An electronic product, characterized in that: The electronic product at least comprises: the timing circuit according to any one of claims 1 to 8 or the chip according to claim 9.