Signal detection circuit and signal detection method

Abstract

The invention discloses a signal detection circuit and a signal detection method. The signal detection circuit comprises a latch comparator, an SR latch, a signal loss detection module and a reset signal generator. After the latch comparator receives an input signal to be detected, the level state of the output end of the latch comparator is transmitted to the input end of the reset signal generator, the input end of the signal loss detection module and the setting end of the SR latch; after receiving the clock signal, the reset signal generator generates a reset pulse signal according to a level state and transmits the reset pulse signal to a reset end of the latch comparator; the signal loss detection module adjusts the level state of the output end of the signal loss detection module according to the level state and transmits the level state to the reset end of the SR latch; and the SR latch outputs a detection result according to the level state of the set end and the level state of the reset end of the SR latch. Compared with the prior art in which a latch comparator is triggered by a clock signal to detect the signal, the method has obvious advantages.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a signal detection circuit and a signal detection method. Background Art

[0002] In the signal transmission system, the receiving end often needs to respond according to whether there is an input signal. When there is an input signal, the receiving end is in working state and performs signal processing; when there is no input signal, the receiving end is in dormant state and does not perform signal processing. At this time, the receiving end needs to detect the input signal quickly. If the receiving end cannot detect the input signal quickly, it will cause the receiving end to be unable to process the signal in time, affecting the accuracy of the signal transmission system.

[0003] In the prior art, signals are mainly detected by triggering a latch comparator through a clock signal. Since it is necessary to wait for the clock signal to be triggered, there is a time difference from signal input to latch comparator output, resulting in the inability to quickly detect the input signal.

[0004] Therefore, how to detect signals quickly and accurately is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Based on the above problems, the present application provides a signal detection circuit and a signal detection method, the purpose of which is to detect signals quickly and accurately.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] In a first aspect, the present application provides a signal detection circuit, which includes: a latch comparator, an SR latch, a signal loss detection module and a reset signal generator:

[0008] The input end of the latch comparator is used to receive the input signal to be detected, the output end of the latch comparator is connected to the set end of the SR latch, the input end of the signal loss detection module and the input end of the reset signal generator, and the reset end of the latch comparator is connected to the output end of the reset signal generator;

[0009] The reset end of the SR latch is connected to the output end of the signal loss detection module, and the output end of the SR latch serves as the output end of the signal detection circuit;

[0010] The clock end of the signal loss detection module and the clock end of the reset signal generator are connected to the same clock signal output end;

[0011] The latch comparator is used to transmit the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch after receiving the input signal to be detected;

[0012] The reset signal generator is used to generate a reset pulse signal according to the level state after receiving the clock signal at its own clock end, and transmit the reset pulse signal to the reset end of the latch comparator, wherein the reset pulse signal is used to reset the output signal of the latch comparator;

[0013] The signal loss detection module is used to adjust the level state of its own output terminal according to the level state, and transmit its own level state to the reset terminal of the SR latch;

[0014] The SR latch is used to output a detection result of the input signal to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch.

[0015] Optionally, under the condition that the signal detection circuit does not receive the input signal to be detected, the latch comparator is also used to output a low level;

[0016] The signal loss detection module is further configured to wait for a preset time under the condition that the input end of the signal loss detection module receives the low level output by the latch comparator, and if the input end of the signal loss detection module remains at a low level within the preset time, the output end of the signal loss detection module outputs a high level;

[0017] The SR latch is also used to output a low level when its reset terminal is at a high level.

[0018] The signal loss detection module includes a sampler and a counter:

[0019] The input end of the sampler is connected to the output end of the latch comparator, and the clock end of the sampler serves as the clock end of the signal loss detection module;

[0020] The input end of the counter is connected to the output end of the sampler, and the output end of the counter serves as the output end of the signal loss detection module;

[0021] The sampler is used to sample the level state based on the clock signal to obtain a sampling signal;

[0022] The counter is used to determine whether the sampling signals are all at low level within a preset time, and if so, output a high level; if the sampling signals appear at a high level within the preset time, output a low level.

[0023] If the set end of the SR latch is at a high level and the reset end of the SR latch is at a low level, the output end of the SR latch outputs a high level;

[0024] If the set end of the SR latch is at a low level and the reset end of the SR latch is at a low level, the output end of the SR latch remains unchanged;

[0025] If the set end of the SR latch is at a low level and the reset end of the SR latch is at a high level, the output end of the SR latch outputs a low level.

[0026] The second aspect of the present application provides a signal detection method, which is applied to the signal detection circuit provided in the first aspect. The method comprises:

[0027] After receiving the input signal to be detected, the latch comparator transmits the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch;

[0028] After receiving the clock signal at its own clock end, the reset signal generator generates a reset pulse signal according to the level state, and transmits the reset pulse signal to the reset end of the latch comparator, wherein the reset pulse signal is used to reset the output signal of the latch comparator;

[0029] The signal loss detection module adjusts the level state of its own output terminal according to the level state, and transmits its own level state to the reset terminal of the SR latch;

[0030] The SR latch outputs a detection result of the input signal to be detected according to a level state of a set terminal of the SR latch and a level state of a reset terminal of the SR latch.

[0031] Optionally, the method further comprises:

[0032] Under the condition that the signal detection circuit does not receive the input signal to be detected, the latch comparator outputs a low level;

[0033] The signal loss detection module waits for a preset time under the condition that its input terminal receives the low level output by the latch comparator. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level.

[0034] The SR latch outputs a low level when its reset terminal is at a high level.

[0035] The signal loss detection module comprises a sampler and a counter: the input end of the sampler is connected to the output end of the latch comparator, and the clock end of the sampler is used as the clock end of the signal loss detection module; the input end of the counter is connected to the output end of the sampler, and the output end of the counter is used as the output end of the signal loss detection module;

[0036] The signal loss detection module adjusts the level state of its output terminal according to the level state, and transmits its own level state to the reset terminal of the SR latch, including:

[0037] The sampler samples the level state based on the clock signal to obtain a sampling signal;

[0038] The counter determines whether the sampling signals are all at low level within a preset time, and if so, outputs a high level; if the sampling signals are at high level within the preset time, outputs a low level.

[0039] The SR latch outputs a detection result of the input signal to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch, including:

[0040] If the set end of the SR latch is at a high level and the reset end of the SR latch is at a low level, the output end of the SR latch outputs a high level;

[0041] If the set end of the SR latch is at a low level and the reset end of the SR latch is at a low level, the output end of the SR latch remains unchanged;

[0042] If the set end of the SR latch is at a low level and the reset end of the SR latch is at a high level, the output end of the SR latch outputs a low level;

[0043] The output terminal of the SR latch outputs a high level, indicating that the detection result is: the signal detection circuit detects the presence of the input signal to be detected;

[0044] The output terminal of the SR latch is at a low level, indicating that the detection result is: the signal detection circuit does not detect the existence of the input signal to be detected.

[0045] Compared with the prior art, this application has the following beneficial effects:

[0046] The present application provides a signal detection circuit and a signal detection method, wherein the signal detection circuit includes: a latch comparator, an SR latch, a signal loss detection module and a reset signal generator. The input end of the latch comparator is used to receive an input signal to be detected, the output end of the latch comparator is connected to the set end of the SR latch, the input end of the signal loss detection module and the input end of the reset signal generator, the reset end of the latch comparator is connected to the output end of the reset signal generator; the reset end of the SR latch is connected to the output end of the signal loss detection module, and the output end of the SR latch serves as the output end of the signal detection circuit.

[0047] Since the latch comparator described in the present application does not need to be triggered by a clock signal, after receiving the input signal to be detected, the latch comparator transmits the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch; when the input signal to be detected is continuously input, after receiving the clock signal at its own clock end, the reset signal generator generates a reset pulse signal according to the level state, transmits the reset pulse signal to the reset end of the latch comparator, and continuously resets the latch comparator, so that the latch comparator continuously responds to the input signal to be detected; when the input signal to be detected stops inputting, the signal loss detection module adjusts the level state of its own output end according to the level state, and transmits its own level state to the reset end of the SR latch; the SR latch outputs the detection result of the input signal to be detected according to the level state of its own set end and the level state of the reset end.

[0048] In summary, the signal detection circuit and signal detection method provided in the present application effectively realize real-time detection of the input signal to be detected. They can not only respond to changes in the input signal to be detected in a timely manner, but also make corresponding processing when the signal stops inputting or the signal is lost, thereby ensuring that the signal detection is fast and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0050] Figure 1 A schematic diagram of the structure of a signal detection circuit provided in an embodiment of the present application;

[0051] Figure 2A schematic diagram of the structure of a signal loss detection module provided in an embodiment of the present application;

[0052] Figure 3 A flow chart of a signal detection method provided in an embodiment of the present application;

[0053] Figure 4 A flowchart of another signal detection method provided in an embodiment of the present application;

[0054] Figure 5 A schematic diagram of a signal waveform provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] As described above, current signal detection requires waiting for the clock signal to trigger the latch comparator. There is a time difference from signal input to latch comparator output, resulting in the inability to quickly detect the input signal.

[0056] In view of the above problems, the inventor has proposed a signal detection method and a signal detection circuit after research, the signal detection circuit includes: a latch comparator, an SR latch, a signal loss detection module and a reset signal generator. After receiving the input signal to be detected, the latch comparator transmits the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch; after receiving the clock signal at its own clock end, the reset signal generator generates a reset pulse signal according to the level state, transmits the reset pulse signal to the reset end of the latch comparator, and the reset pulse signal is used to reset the output signal of the latch comparator; the signal loss detection module adjusts the level state of its own output end according to the level state, and transmits its own level state to the reset end of the SR latch; the SR latch outputs the detection result of the input signal to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch.

[0057] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] See also Figure 1 , which is a schematic diagram of the structure of a signal detection circuit provided in an embodiment of the present application. Figure 1As shown, the circuit includes: a latch comparator 11, an SR latch 14, a signal loss detection module 12 and a reset signal generator 13:

[0059] The input end of the latch comparator 11 is used to receive the input signal to be detected, the output end of the latch comparator 11 is connected to the set end of the SR latch 14, the input end of the signal loss detection module 12 and the input end of the reset signal generator 13, and the reset end of the latch comparator 11 is connected to the output end of the reset signal generator 13;

[0060] The reset end of the SR latch 14 is connected to the output end of the signal loss detection module 12 , and the output end of the SR latch 14 serves as the output end of the signal detection circuit.

[0061] The clock end of the signal loss detection module 12 and the clock end of the reset signal generator 13 are connected to the same clock signal output end.

[0062] The latch comparator 11 includes an input terminal, an output terminal and a reset terminal, and is mainly used to detect the change of the input signal relative to a certain threshold value and maintain the result of the change until it is reset. For example, when the input signal starts to input, there is no need to wait for any clock signal to trigger, and the output terminal of the latch comparator 11 outputs a high level.

[0063] The SR latch 14 comprises a set end S, a reset end R and an output end. If the set end of the SR latch 14 is at a high level and the reset end of the SR latch 14 is at a low level, the output end of the SR latch 14 outputs a high level; if the set end of the SR latch 14 is at a low level and the reset end of the SR latch 14 is at a low level, the output end of the SR latch 14 remains unchanged; if the set end of the SR latch 14 is at a low level and the reset end of the SR latch 14 is at a high level, the output end of the SR latch 14 outputs a low level.

[0064] Figure 2 Schematic diagram of the structure of a signal loss detection module 12 provided in an embodiment of the present application. The signal loss detection module 12 includes a sampler 31 and a counter 32, such as Figure 2As shown, the input end of the sampler 31 is connected to the output end of the latch comparator 11, and the clock end of the sampler 31 is used as the clock end of the signal loss detection module 12; the input end of the counter 32 is connected to the output end of the sampler 31, and the output end of the counter 32 is used as the output end of the signal loss detection module 12. The sampler 31 is used to sample the level state based on the clock signal to obtain a sampling signal; the counter 32 is used to determine whether the sampling signals are all low levels within a preset time, and if they are all low levels, then the counter 32 outputs a high level; if the sampling signal appears high level within the preset time, then the counter 32 outputs a low level.

[0065] The reset signal generator 13 comprises an input terminal, a clock terminal and an output terminal, and is used to generate a reset pulse signal to reset the level state of the output terminal of the latch comparator 11 .

[0066] When the input signal starts to be input, the output end of the latch comparator 11 outputs a high level, the set end of the SR latch 14 is a high level, and the input end of the signal loss detection module 12 is a high level, then the output end of the signal loss detection module 12 is a low level, the reset end of the SR latch 14 is a low level, and the output end of the SR latch 14 outputs a high level; when the input signal is continuously input, the reset signal generator 13 generates a reset pulse signal to continuously reset the latch comparator 11, so that the latch comparator 11 can continuously detect the input signal and update the level state of its output end; the SR latch 14 outputs a signal detection result according to the level state of its own set end and the level state of the reset end.

[0067] In summary, the signal detection circuit implements that when there is an input signal, the latch comparator 11 can respond quickly, and when the input signal is continuously input, the reset signal generator 13 generates a reset pulse signal according to the clock signal to continuously reset the latch comparator 11, so that the latch comparator 11 can continuously detect the input signal; when the input signal stops inputting or the input signal is lost, the signal loss detection module 12 waits for a preset time, samples and judges the level state of the output end of the latch comparator 11, and updates the level state of each part in time, and the SR latch 14 outputs the detection result, so that the detection result of the entire signal detection circuit is accurate and fast.

[0068] Based on the signal detection circuit in the above embodiment, the present application also provides an embodiment of a signal detection method, which is described in detail below.

[0069] See also Figure 3 , which is a flow chart of a signal detection method provided in an embodiment of the present application. Figure 3As shown, the method comprises the following steps:

[0070] S301. After receiving the input signal to be detected, the latch comparator transmits the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch.

[0071] After receiving the input signal to be detected, the latch comparator changes the level state of its output end according to the relationship between the characteristics of the input signal and the preset threshold. This changed level state will be transmitted to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch at the same time. The latch comparator can not only quickly respond to the change of the input signal to be detected, but also effectively transmit the information of this change to other parts, thereby ensuring that the entire circuit can quickly and accurately respond to the input signal to be detected.

[0072] S302, after receiving the clock signal at its own clock end, the reset signal generator generates a reset pulse signal according to the level state, and transmits the reset pulse signal to the reset end of the latch comparator, wherein the reset pulse signal is used to reset the output signal of the latch comparator.

[0073] The input end of the reset signal generator detects the level state change of the output end of the latch comparator and generates a reset pulse signal. After receiving the reset pulse signal, the reset end of the latch comparator resets the level state of its output end to restore it to its initial state. In this way, the reset signal generator ensures that the latch comparator can respond to the input signal quickly and accurately, and correctly resets the latch comparator after each detection.

[0074] S303: The signal loss detection module adjusts the level state of its own output terminal according to the level state, and transmits its own level state to the reset terminal of the SR latch.

[0075] The sampler samples the level state based on the clock signal to obtain a sampling signal; the counter determines whether the sampling signals are all low levels within a preset time, and if they are all low levels, outputs a high level; if the sampling signal appears high level within the preset time, outputs a low level.

[0076] S304: The SR latch outputs a detection result of the input signal to be detected according to a level state of the set end of the SR latch and a level state of the reset end of the SR latch.

[0077] The output terminal of the SR latch outputs a high level, indicating that the detection result is: the signal detection circuit detects the presence of the input signal to be detected;

[0078] The output terminal of the SR latch is at a low level, indicating that the detection result is: the signal detection circuit does not detect the existence of the input signal to be detected.

[0079] The signal detection method realizes that when there is an input signal, the latch comparator can respond quickly, and when the input signal is continuously input, the reset signal generator generates a reset pulse signal according to the clock signal to continuously reset the latch comparator, so that the latch comparator can continuously detect the input signal; when the input signal stops inputting or the input signal is lost, the signal loss detection module waits for a preset time, samples and judges the level state of the output end of the latch comparator, and updates the level state of each part in time. The SR latch outputs the detection result, so that the detection result of the entire signal detection circuit is accurate and fast. The various parts of the signal detection method respond quickly and cooperate with each other, and can quickly and accurately detect whether the input signal exists and reflect the changes contained in the input signal.

[0080] See also Figure 4 , which is a flow chart of another signal detection method provided by an embodiment of the present application. The method fully presents the response process of the latch comparator, signal loss detection module, reset signal generator and SR latch when the input signal starts to input, continues to input until it disappears. Figure 5 is a schematic diagram of the signal waveform. This method is effective for Figure 5 The input signal V in Signal detection is performed, the level state of the output end of the latch comparator is V1, the level state of the output end of the signal loss detection module is V2, and the reset pulse signal generated by the reset signal generator is V rst , the level state of the SR latch output is V out ; wherein the signal loss detection module and the reset signal generator receive the same clock signal Clk, the method comprising the following steps:

[0081] S401: receiving an input signal V to be detected in The output terminal V1 of the latch comparator outputs a high level, and transmits its level state to the input terminal of the reset signal generator, the input terminal of the signal loss detection module and the set terminal of the SR latch.

[0082] At this time, the set end of the SR latch is at a high level, the input end of the signal loss detection module is at a high level, so that its own output end V2 outputs a low level, making the reset end of the SR latch at a low level. Therefore, the output end V out Outputting a high level indicates that the signal detection circuit detects the presence of an input signal to be detected.

[0083] S402, when the input signal V in When the input is continuous, the reset signal generator generates a reset pulse signal V according to the level state after receiving the clock signal Clk at its own clock end. rst , the reset pulse signal V rst The voltage is transmitted to the reset terminal of the latch comparator to reset the latch comparator, so that the output terminal V1 of the latch comparator outputs a low level.

[0084] Among them, the frequency of the clock signal Clk is related to the input signal V in At this time, the output terminal V1 of the reset latch comparator outputs a low level. When the latch comparator continuously detects the input signal V in After that, it immediately jumps to a high level and updates the level state of its output terminal V1. This reset process corresponds to Figure 5 The V1 waveform shows a brief fluctuation.

[0085] S403 : The latch comparator transmits the level state of its output terminal V1 to the input terminal of the reset signal generator, the input terminal of the signal loss detection module and the set terminal of the SR latch.

[0086] When the set terminal of the SR latch is at a low level, the level state of the output terminal depends on the reset terminal of the SR latch.

[0087] Wait for a preset time, during which the input end of the signal loss detection module appears high level, and the output end of the signal loss detection module outputs low level, so that the reset end of the SR latch is low level. At this time, the output end V out Maintain the level state when there is an input signal, that is, high level. In summary, when the input signal V in When the input starts and continues, the output terminal V of the SR latch out Output high level.

[0088] S404, when the input signal V in When the input is stopped, the output terminal V1 of the latch comparator outputs a low level, and transmits its level state to the input terminal of the reset signal generator, the input terminal of the signal loss detection module and the set terminal of the SR latch.

[0089] At this time, the set end of the SR latch is at a low level, and the level state of the output end depends on the reset end of the SR latch.

[0090] Waiting for a preset time, during which the input terminal of the signal loss detection module remains at a low level, and the output terminal V2 of the signal loss detection module outputs a high level, so that the reset terminal of the SR latch is at a high level.

[0091] For example, the sampler in the signal loss detection module samples the level state of the output terminal V1 of the latch comparator. Assuming the preset time T=5ms and the frequency f of the clock signal Clk=10kHz, the sampling number n is n=T / (1 / f)=50. When the counter in the signal loss detection module detects that the sampling signal is at a low level for 50 consecutive times within the preset time, it means that the level state of the output terminal V1 of the latch comparator is always at a low level. Then, the output terminal V2 of the signal loss detection module outputs a high level, so that the reset terminal of the SR latch is at a high level.

[0092] S405, the SR latch outputs a response to the input signal V to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch. in The test results.

[0093] At this time, the set end of the SR latch is at a low level, the reset end of the SR latch is at a high level, and the output end V out Output low level, indicating that no input signal V is detected in .

[0094] The method can detect the input signal quickly when there is a signal input, and can continuously detect the input signal until the input signal disappears, thereby ensuring fast and accurate signal detection.

[0095] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0096] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal detection circuit, characterized in that: The circuit includes: a latch comparator, an SR latch, a signal loss detection module and a reset signal generator: The input end of the latch comparator is used to receive the input signal to be detected, the output end of the latch comparator is connected to the set end of the SR latch, the input end of the signal loss detection module and the input end of the reset signal generator, and the reset end of the latch comparator is connected to the output end of the reset signal generator; The reset end of the SR latch is connected to the output end of the signal loss detection module, and the output end of the SR latch serves as the output end of the signal detection circuit; The clock end of the signal loss detection module and the clock end of the reset signal generator are connected to the same clock signal output end; The latch comparator is used to transmit the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch after receiving the input signal to be detected; The reset signal generator is used to generate a reset pulse signal according to the level state after receiving the clock signal at its own clock end, and transmit the reset pulse signal to the reset end of the latch comparator, wherein the reset pulse signal is used to reset the output signal of the latch comparator; The signal loss detection module is used to adjust the level state of its output terminal according to the level state, and transmit its own level state to the reset terminal of the SR latch; The SR latch is used to output a detection result of the input signal to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch.

2. The circuit according to claim 1, characterized in that Under the condition that the signal detection circuit does not receive the input signal to be detected, the latch comparator is also used to output a low level; The signal loss detection module is further configured to wait for a preset time under the condition that the input end of the signal loss detection module receives the low level output by the latch comparator, and if the input end of the signal loss detection module remains at a low level within the preset time, the output end of the signal loss detection module outputs a high level; The SR latch is also used to output a low level when its reset terminal is at a high level.

3. The circuit according to claim 1, characterized in that The signal loss detection module includes a sampler and a counter: The input end of the sampler is connected to the output end of the latch comparator, and the clock end of the sampler serves as the clock end of the signal loss detection module; The input end of the counter is connected to the output end of the sampler, and the output end of the counter serves as the output end of the signal loss detection module; The sampler is used to sample the level state based on the clock signal to obtain a sampling signal; The counter is used to determine whether the sampling signals are all at low level within a preset time, and if so, output a high level; if the sampling signals appear at a high level within the preset time, output a low level.

4. The circuit according to claim 1, characterized in that If the set end of the SR latch is at a high level and the reset end of the SR latch is at a low level, the output end of the SR latch outputs a high level; If the set end of the SR latch is at a low level and the reset end of the SR latch is at a low level, the output end of the SR latch remains unchanged; If the set end of the SR latch is at a low level and the reset end of the SR latch is at a high level, the output end of the SR latch outputs a low level.

5. A signal detection method, characterized in that: The method is applied to the signal detection circuit according to claim 1; The method comprises: After receiving the input signal to be detected, the latch comparator transmits the level state of the output end of the latch comparator to the input end of the reset signal generator, the input end of the signal loss detection module and the set end of the SR latch; After receiving the clock signal at its own clock end, the reset signal generator generates a reset pulse signal according to the level state, and transmits the reset pulse signal to the reset end of the latch comparator, wherein the reset pulse signal is used to reset the output signal of the latch comparator; The signal loss detection module adjusts the level state of its own output terminal according to the level state, and transmits its own level state to the reset terminal of the SR latch; The SR latch outputs a detection result of the input signal to be detected according to a level state of a set terminal of the SR latch and a level state of a reset terminal of the SR latch.

6. The method according to claim 5, characterized in that The method further comprises: Under the condition that the signal detection circuit does not receive the input signal to be detected, the latch comparator outputs a low level; The signal loss detection module waits for a preset time under the condition that its input terminal receives the low level output by the latch comparator. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level. The SR latch outputs a low level when its reset terminal is at a high level.

7. The method according to claim 5, characterized in that The signal loss detection module comprises a sampler and a counter: the input end of the sampler is connected to the output end of the latch comparator, and the clock end of the sampler serves as the clock end of the signal loss detection module; The input end of the counter is connected to the output end of the sampler, and the output end of the counter serves as the output end of the signal loss detection module; The signal loss detection module adjusts the level state of its output terminal according to the level state, and transmits its own level state to the reset terminal of the SR latch, including: The sampler samples the level state based on the clock signal to obtain a sampling signal; The counter determines whether the sampling signals are all at low level within a preset time, and if so, outputs a high level; if the sampling signals are at high level within the preset time, outputs a low level.

8. The method according to claim 6, characterized in that The SR latch outputs a detection result of the input signal to be detected according to the level state of the set end of the SR latch and the level state of the reset end of the SR latch, including: If the set end of the SR latch is at a high level and the reset end of the SR latch is at a low level, the output end of the SR latch outputs a high level; If the set end of the SR latch is at a low level and the reset end of the SR latch is at a low level, the output end of the SR latch remains unchanged; If the set end of the SR latch is at a low level and the reset end of the SR latch is at a high level, the output end of the SR latch outputs a low level; The output terminal of the SR latch outputs a high level, indicating that the detection result is: the signal detection circuit detects the presence of the input signal to be detected; The output terminal of the SR latch is at a low level, indicating that the detection result is: the signal detection circuit does not detect the existence of the input signal to be detected.

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