Thin film transistor and manufacturing method thereof, display substrate and display device
By etching the insulating layer and active layer in the via area of the thin film transistor, the source-drain metal layer in the side contact is formed, and the influence of process by-products and plasma on the contact interface is solved, and the contact uniformity and display effect are improved.
Patent Information
- Application Number
- CN202411354196.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-02-11
AI Technical Summary
During the process of existing thin film transistors, process by-products and plasma have a great impact on the contact interface between the source and drain electrodes and the active layer, resulting in uneven contact and affecting the display effect.
By etching the insulating layer and the active layer in the preset via area of the thin film transistor, vias through the insulating layer and the active layer are formed, and a source-drain metal layer is formed on the insulating layer to make it with the active layer side contact.
This method effectively reduces the influence of process by-products and plasma on the contact interface between the source and drain metal layer and the active layer, improves contact uniformity, and improves low gray-scale image quality and display effect.
Smart Images
Figure CN119421432A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, a display substrate, and a display device. Background Art
[0002] Thin Film Transistor (TFT) is a very important component in the field of display technology and plays a very important role in Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED).
[0003] Among them, a contact hole (CNT) needs to be opened on the upper layer of the TFT to lead out the source and drain of the TFT. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a thin film transistor and a manufacturing method thereof, a display substrate, and a display device, which can effectively reduce the influence of process byproducts and plasma on the contact interface between the source, drain and active layer.
[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:
[0006] In one aspect, a method for manufacturing a thin film transistor is provided, comprising:
[0007] providing a substrate;
[0008] forming a buffer layer on the substrate;
[0009] forming an active layer on the buffer layer and an insulating layer covering the active layer;
[0010] Etching the insulating layer and the active layer in a preset via hole area to form a via hole that at least penetrates the insulating layer and the active layer;
[0011] A source-drain metal layer is formed on the insulating layer, and the source-drain metal layer fills the via hole and contacts the side surface of the active layer exposed by the via hole.
[0012] In some embodiments, etching the insulating layer and the active layer in the preset via hole area to form a via hole at least penetrating the insulating layer and the active layer comprises:
[0013] The insulating layer and the active layer are overetched to etch away a portion of the buffer layer to form the via hole penetrating the insulating layer, the active layer and a portion of the buffer layer.
[0014] In some embodiments, the thickness of the etched portion of the buffer layer is 500-2000 angstroms.
[0015] In some embodiments, when etching the insulating layer and the active layer, the etching gas used is a mixed gas of CF4 and O2, the flow ratio of CF4 and O2 is 720:480, the etching power is 18KW, and the etching pressure is 10mT.
[0016] In some embodiments, before forming an active layer on the buffer layer and an insulating layer covering the active layer, the method further comprises:
[0017] forming a first metal layer in the preset via area;
[0018] Wherein, after the source-drain metal layer is formed, the source-drain metal layer is connected to the first metal layer through the via hole.
[0019] An embodiment of the present invention further provides a thin film transistor, which is manufactured using the manufacturing method described above.
[0020] In some embodiments, the thin film transistor comprises:
[0021] substrate;
[0022] a buffer layer located on the substrate;
[0023] an active layer located on the buffer layer and an insulating layer covering the active layer;
[0024] A source-drain metal layer is located on the insulating layer, and the source-drain metal layer contacts the side surface of the active layer through a via hole penetrating the active layer and the insulating layer.
[0025] In some embodiments, the thin film transistor comprises:
[0026] substrate;
[0027] a buffer layer located on the substrate;
[0028] a first metal layer located on the buffer layer;
[0029] an active layer located on the first metal layer and an insulating layer covering the active layer;
[0030] A source-drain metal layer is located on the insulating layer, and the source-drain metal layer contacts the side surface of the active layer through a via hole penetrating the active layer and the insulating layer, and contacts the first metal layer.
[0031] In some embodiments, the first metal layer is made of Mo, Ti, Ag or indium gallium zinc oxide.
[0032] In some embodiments, the thickness of the first metal layer is 10-2000 angstroms.
[0033] An embodiment of the present invention further provides a display substrate, comprising the thin film transistor as described above.
[0034] An embodiment of the present invention further provides a display device, comprising the display substrate as described above.
[0035] The embodiments of the present invention have the following beneficial effects:
[0036] In the above scheme, the active layer in the via area is etched away so that the source-drain metal layer overlaps the side of the active layer. This structure can effectively reduce the influence of process by-products and plasma on the contact interface between the source-drain metal layer and the active layer, improve the contact uniformity between the source-drain metal layer and the active layer, improve low-grayscale display unevenness, white spot mura, black cluster mura, cluster mura and other defects under low-grayscale image quality, and improve the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 A schematic diagram of a prior art method for making a thin film transistor;
[0038] Figure 2 A schematic diagram of over-engraving the active layer;
[0039] Figure 3 The schematic diagram is that the active layer is not over-etched enough and the contact area between the source and drain metal layers and the active layer is small;
[0040] Figure 4 The schematic diagram is that the active layer is over-etched, and the contact area between the source and drain metal layers and the active layer is large;
[0041] Figure 5 A schematic diagram of etching an active layer and an insulating layer according to an embodiment of the present invention;
[0042] Figure 6 and Figure 7 A schematic diagram of the contact between the source-drain metal layer and the active layer according to an embodiment of the present invention;
[0043] Figure 8 A schematic diagram of the location where the source and drain metal layers are prone to fracture;
[0044] Fig. 9 A schematic diagram of the structure of a thin film transistor according to an embodiment of the present invention;
[0045] Fig.10 A schematic diagram of a display screen under low grayscale quality of an existing display substrate;
[0046] Fig.11 It is a schematic diagram of a display screen with low grayscale quality of a display substrate according to an embodiment of the present invention.
[0047] Reference numerals
[0048] 01 Buffer layer
[0049] 02 Active layer
[0050] 03 First gate insulation layer
[0051] 04 Second gate insulation layer
[0052] 05 Interlayer insulation layer
[0053] 06 Source and drain metal layer
[0054] 07 First Metal Layer DETAILED DESCRIPTION
[0055] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.
[0056] In the prior art, at the CNT hole, the source and drain metal layers are overlapped with the active layer in a surface contact manner. Figure 1 As shown, the thin film transistor includes a buffer layer 01, an active layer 02, a first gate insulating layer 03, a second gate insulating layer 04 and an interlayer insulating layer 05 located on a substrate; before forming a source-drain metal layer, the CNT hole is etched to the active layer 02, and the active layer 02 is overetched, as shown in FIG. Figure 2 As shown, a portion of the active layer (P-Si) is etched away to ensure that the source-drain metal layer is in contact with the surface of the active layer 02. The thickness of the active layer 02 is about 450 angstroms, and the active layer 02 needs to be overetched by about 200 angstroms, as shown in FIG. Figure 3 As shown, when the active layer is less overetched, the contact area between the source-drain metal layer 06 and the active layer 02 is relatively small; Figure 4 As shown, when the active layer is overetched more, the contact area between the source-drain metal layer 06 and the active layer 02 is relatively large.
[0057] It is difficult to control the uniformity of the overetching amount of the active layer 02. In order to control the overetching amount of the active layer 02, etching the active layer 02, the first gate insulating layer 03, the second gate insulating layer 04 and the interlayer insulating layer 05 is divided into two steps. In the first etching step, the etching gas is a mixed gas of CF4 and O2, the flow ratio is CF4 / O2=720 / 480, the power (Power): 18 / 18 (KW), and the pressure is: 10 (mT), wherein 18 / 18 (KW) represents that the power of the upper electrode is 18KW, and the power of the lower electrode is 18KW, mT is the unit of pressure, 1 Torr (Torr) = 1000mT, and the etching is carried out to the second gate insulating layer 04, and the etching takes about 140s; in the second etching step, the etching gas is a mixed gas of CF4, CHF3 and Ar, and the flow ratio is CF4 / CHF3 / Ar=100 / 450 / 450, Power: 18 / 18 (KW), and the pressure is 10 (mT). The first gate insulating layer 03 and a small amount of active layer 02 are etched, and the etching takes about 50s.
[0058] Due to the high etching power and many etching steps, there are process byproducts on the residual interface of the active layer 02, such as Figure 1 As shown, process byproducts and plasma bombardment will have a significant impact on the roughness and interface activity of the active layer interface, resulting in a large difference in contact resistance between the source and drain metal layers and the active layer, affecting the uniformity of the on-state current of the display circuit, resulting in poor low-grayscale image quality of the display substrate.
[0059] The embodiments of the present invention provide a thin film transistor and a manufacturing method thereof, a display substrate, and a display device, which can effectively reduce the influence of process byproducts and plasma on the contact interface between the source, drain and active layer.
[0060] An embodiment of the present invention provides a method for manufacturing a thin film transistor, comprising:
[0061] providing a substrate;
[0062] forming a buffer layer on the substrate;
[0063] forming an active layer on the buffer layer and an insulating layer covering the active layer;
[0064] Etching the insulating layer and the active layer in a preset via hole area to form a via hole that at least penetrates the insulating layer and the active layer;
[0065] A source-drain metal layer is formed on the insulating layer, and the source-drain metal layer fills the via hole and contacts the side surface of the active layer exposed by the via hole.
[0066] The source-drain metal layer is used to form the source and drain of the thin film transistor.
[0067] In the present embodiment, the active layer in the via area is etched away so that the source-drain metal layer overlaps the side of the active layer. This structure can effectively reduce the influence of process byproducts and plasma on the contact interface between the source-drain metal layer and the active layer, improve the contact uniformity between the source-drain metal layer and the active layer, improve low-grayscale display unevenness, white spot mura, black cluster mura, cluster mura and other defects under low grayscale image quality, and improve the display effect of the display device.
[0068] In this embodiment, all insulating layers and all active layers in the preset via area are removed, and the contact mode between the source-drain metal layer and the active layer is changed, so that the source-drain metal layer contacts the side of the active layer, so that the contact area between the source-drain metal layer and the active layer is not affected by the etching uniformity of the active layer, but is only related to the film thickness uniformity of the active layer. Compared with the surface contact, the side contact resistance between the source-drain metal layer and the active layer is smaller and the uniformity is better. In this embodiment, the active layer in the via area is completely etched away, eliminating the influence of plasma bombardment on the contact interface between the source-drain metal layer and the active layer; in addition, the active layer in the via area is completely etched away, which also eliminates the influence of process residual particles on the contact interface between the source-drain metal layer and the active layer.
[0069] In this embodiment, in order to ensure that the active layer in the via region is completely etched away, the active layer is overetched to remove part of the buffer layer below the active layer. In some embodiments, etching the insulating layer and the active layer in the preset via region to form a via that at least penetrates the insulating layer and the active layer includes:
[0070] The insulating layer and the active layer are overetched to etch away a portion of the buffer layer to form the via hole penetrating the insulating layer, the active layer and a portion of the buffer layer.
[0071] like Figure 5 As shown, in a specific example, the thin film transistor includes a buffer layer 01, an active layer 02, a first gate insulating layer 03, a second gate insulating layer 04 and an interlayer insulating layer 05 located on a substrate; before forming the source and drain metal layers, the buffer layer 01, the active layer 02, the first gate insulating layer 03, the second gate insulating layer 04 and the interlayer insulating layer 05 in the area where the CNT holes are to be formed are etched until part of the buffer layer 01 is removed, and the buffer layer 01 can be made of silicon oxide with a thickness of about 3000 angstroms, and the thickness of the etched part of the buffer layer can be 500-2000 angstroms, for example, 1000 angstroms.
[0072] In this embodiment, since there is no need to control the uniformity of the overetching amount of the active layer 02, the buffer layer 01, the active layer 02, the first gate insulating layer 03, the second gate insulating layer 04, the interlayer insulating layer 05 and part of the buffer layer 01 can be removed by one-step etching, which can simplify the etching process. Specifically, the etching gas used can be a mixed gas of CF4 and O2, the flow ratio of CF4 and O2 is 720:480, the etching power is 18KW, and the etching pressure is 10mT.
[0073] In this embodiment, the active layer 02 in the via region is completely removed, and no matter how much the buffer layer 01 is overetched, the contact area between the source-drain metal layer 06 and the active layer 02 is not affected. Figure 6 As shown, the overetching amount of the buffer layer 01 is small, and the contact area between the source-drain metal layer 06 and the active layer 02 is part A1 and part A2; Figure 7 As shown, the buffer layer 01 has a large over-etching amount, and the contact area between the source-drain metal layer 06 and the active layer 02 is still the A1 part and the A2 part. In this way, the contact area between the source-drain metal layer 06 and the active layer 02 is not affected by the over-etching depth of the active layer, but only by the uniformity of the thickness of the active layer, and there is no influence of plasma bombardment and process residual particles on the interface of the active layer, which ensures better uniformity of the contact resistance between the source-drain metal layer and the active layer, improves the uniformity of the on-state current, and thus makes the display effect more uniform.
[0074] like Figure 8 As shown, the buffer layer 01 is an insulating layer, and also has a high etching rate. The over-etching depth is difficult to control. When the over-etching depth is large, and because the etching selectivity of the active layer is relatively high, the active layer 02 is prone to form steps in the via hole, and the source-drain metal layer 06 (SD) at position B is prone to cracking. The cracking of the source-drain metal layer 06 will affect the side overlap between the source-drain metal layer 06 and the active layer 02, and the integrity of the source-drain metal layer 06. In order to improve this problem, in some embodiments, before the active layer and the insulating layer covering the active layer are formed on the buffer layer, as shown in FIG. Fig. 9 As shown, the method also includes:
[0075] Forming a first metal layer 07 in the preset via area;
[0076] After the source-drain metal layer 06 is formed, the source-drain metal layer 06 is connected to the first metal layer 07 through the via hole.
[0077] In this embodiment, the first metal layer 07 can be made of a metal with a high etching selectivity, such as Mo, Ti, Ag or indium gallium zinc oxide and other high etching selectivity materials. In this embodiment, when etching the buffer layer 01, the active layer 02, the first gate insulating layer 03, the second gate insulating layer 04 and the interlayer insulating layer 05 in the preset via area, the etching is stopped at the first metal layer 07, the active layer 02 in the via area is completely removed, and no steps are formed in the via. The first metal layer 07 is in contact with the source-drain metal layer 06, which can avoid the source-drain metal layer 06 at the via to break, ensure the integrity of the source-drain metal layer 06 in the via, and then ensure the side overlap of the source-drain metal layer 06 and the active layer 02, and improve the defects such as bright and dark spots caused by the break of the source-drain metal layer 06 in the via.
[0078] Fig.10 This is a schematic diagram of a display screen under low grayscale quality of an existing display substrate. It can be seen that under low grayscale quality, display unevenness, white spot mura, black cluster mura, cluster mura and other defects occur; Fig.11 Schematic diagram of a display screen under low grayscale quality of a display substrate according to an embodiment of the present invention. It can be seen that display unevenness, white spot mura, black cluster mura, cluster mura and other defects are improved.
[0079] An embodiment of the present invention further provides a thin film transistor, which is manufactured using the manufacturing method described above.
[0080] In some embodiments, Figure 6 and Figure 7 As shown, the thin film transistor includes:
[0081] substrate;
[0082] A buffer layer 01 located on the substrate;
[0083] An active layer 02 located on the buffer layer 01 and an insulating layer covering the active layer 02;
[0084] A source-drain metal layer 06 is located on the insulating layer, and the source-drain metal layer 06 contacts the side surface of the active layer 02 through a via hole penetrating the active layer 02 and the insulating layer.
[0085] The insulating layer may include a first gate insulating layer 03 , a second gate insulating layer 04 and an interlayer insulating layer 05 .
[0086] In this embodiment, the active layer 02 in the via region is completely removed, and no matter how much the buffer layer 01 is overetched, the contact area between the source-drain metal layer 06 and the active layer 02 is not affected. Figure 6 As shown, the overetching amount of the buffer layer 01 is small, and the contact area between the source-drain metal layer 06 and the active layer 02 is part A1 and part A2; Figure 7 As shown, the buffer layer 01 has a large over-etching amount, and the contact area between the source-drain metal layer 06 and the active layer 02 is still the A1 part and the A2 part. In this way, the contact area between the source-drain metal layer 06 and the active layer 02 is not affected by the over-etching depth of the active layer, but only by the uniformity of the thickness of the active layer, and there is no influence of plasma bombardment and process residual particles on the interface of the active layer, which ensures better uniformity of the contact resistance between the source-drain metal layer and the active layer, improves the uniformity of the on-state current, and thus makes the display effect more uniform.
[0087] In some embodiments, Fig. 9 As shown, the thin film transistor includes:
[0088] substrate;
[0089] A buffer layer 01 located on the substrate;
[0090] A first metal layer 07 located on the buffer layer 01;
[0091] An active layer 02 located on the first metal layer 07 and an insulating layer covering the active layer 02;
[0092] The source-drain metal layer 06 is located on the insulating layer, and the source-drain metal layer 06 contacts the side surface of the active layer 02 through a via hole penetrating the active layer 02 and the insulating layer, and contacts the first metal layer 07 .
[0093] The insulating layer may include a first gate insulating layer 03 , a second gate insulating layer 04 and an interlayer insulating layer 05 .
[0094] In this embodiment, the first metal layer 07 can be made of a metal with a high etching selectivity, such as Mo, Ti, Ag or indium gallium zinc oxide and other high etching selectivity materials. In some embodiments, the thickness of the first metal layer is 10-2000 angstroms. In this embodiment, when etching the buffer layer 01, the active layer 02, the first gate insulating layer 03, the second gate insulating layer 04 and the interlayer insulating layer 05 in the preset via area, over-etching is performed, and the etching stops at the first metal layer 07. The active layer 02 in the via area is completely removed, and no steps are formed in the via. The first metal layer 07 is in contact with the source-drain metal layer 06, which can avoid the source-drain metal layer 06 at the via to break, ensure the integrity of the source-drain metal layer 06 in the via, and then ensure the side overlap of the source-drain metal layer 06 and the active layer 02, and improve the defects such as bright and dark spots caused by the break of the source-drain metal layer 06 in the via.
[0095] Fig.10 This is a schematic diagram of a display screen under low grayscale quality of an existing display substrate. It can be seen that under low grayscale quality, display unevenness, white spot mura, black cluster mura, cluster mura and other defects occur; Fig.11Schematic diagram of a display screen under low grayscale quality of a display substrate according to an embodiment of the present invention. It can be seen that display unevenness, white spot mura, black cluster mura, cluster mura and other defects are improved.
[0096] An embodiment of the present invention further provides a display substrate, comprising the thin film transistor as described above.
[0097] An embodiment of the present invention further provides a display device, comprising the display substrate as described above.
[0098] The display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not constitute a limitation on the display device, and the display device may include more or less of the above-mentioned components, or a combination of certain components, or different component arrangements. In an embodiment of the present invention, the display device includes but is not limited to a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
[0099] The display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board and a backplane.
[0100] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.
[0101] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0102] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.
[0103] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.
[0104] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A method for manufacturing a thin film transistor, characterized in that: include: providing a substrate; forming a buffer layer on the substrate; forming an active layer on the buffer layer and an insulating layer covering the active layer; Etching the insulating layer and the active layer in a preset via hole area to form a via hole that at least penetrates the insulating layer and the active layer; A source-drain metal layer is formed on the insulating layer, and the source-drain metal layer fills the via hole and contacts the side surface of the active layer exposed by the via hole.
2. The method for manufacturing a thin film transistor according to claim 1, characterized in that: The step of etching the insulating layer and the active layer in the preset via hole area to form a via hole at least penetrating the insulating layer and the active layer comprises: The insulating layer and the active layer are overetched to etch away a portion of the buffer layer to form the via hole penetrating the insulating layer, the active layer and a portion of the buffer layer.
3. The method for manufacturing a thin film transistor according to claim 2, characterized in that: The thickness of the etched portion of the buffer layer is 500-2000 angstroms.
4. The method for manufacturing a thin film transistor according to claim 1, characterized in that: When etching the insulating layer and the active layer, the etching gas used is a mixed gas of CF4 and O2, the flow ratio of CF4 and O2 is 720:480, the etching power is 18KW, and the etching pressure is 10mT.
5. The method for manufacturing a thin film transistor according to claim 1, characterized in that: Before forming an active layer on the buffer layer and an insulating layer covering the active layer, the method further comprises: forming a first metal layer in the preset via area; Wherein, after the source-drain metal layer is formed, the source-drain metal layer is connected to the first metal layer through the via hole.
6. A thin film transistor, characterized in that: The method is prepared according to any one of claims 1 to 5.
7. The thin film transistor according to claim 6, characterized in that: The thin film transistor comprises: substrate; a buffer layer located on the substrate; an active layer located on the buffer layer and an insulating layer covering the active layer; A source-drain metal layer is located on the insulating layer, and the source-drain metal layer contacts the side surface of the active layer through a via hole penetrating the active layer and the insulating layer.
8. The thin film transistor according to claim 6, characterized in that: The thin film transistor comprises: substrate; a buffer layer located on the substrate; a first metal layer located on the buffer layer; an active layer located on the first metal layer and an insulating layer covering the active layer; A source-drain metal layer is located on the insulating layer, and the source-drain metal layer contacts the side surface of the active layer through a via hole penetrating the active layer and the insulating layer, and contacts the first metal layer.
9. The thin film transistor according to claim 8, characterized in that: The first metal layer is made of Mo, Ti, Ag or indium gallium zinc oxide.
10. The thin film transistor according to claim 8, characterized in that: The thickness of the first metal layer is 10-2000 angstroms.
11. A display substrate, characterized in that: A thin film transistor comprising the thin film transistor as claimed in any one of claims 6 to 10.
12. A display device, characterized in that: Comprising the display substrate as claimed in claim 11.