Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, an epitaxial layer, a first well region and a source electrode, the epitaxial layer, the first well region and the source electrode are sequentially deposited on the substrate, a drain electrode is arranged below the substrate, a source region groove is formed in the first well region, and a source region is arranged in the source region groove; the epitaxial layer is provided with a groove, the groove penetrates through the first well region and the source region, the bottom and the side wall of the groove are provided with gate oxide layers, a first dielectric layer and a gate conductive layer are sequentially arranged in the groove, a second dielectric layer is arranged above the groove, and source electrodes are arranged on the two sides of the second dielectric layer. And the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device and a preparation method thereof. Background Art

[0002] In application areas such as wind power generation, photovoltaic energy storage, electric vehicles, chargers, etc., different forms of power conversion are key technologies. These power conversions include converting DC into AC, converting AC into DC, and converting DC at different voltage levels into each other.

[0003] Among the power conversion components, power switch semiconductor devices are key components. The switching speed, switching loss, breakdown voltage capability, size, and cost of power switch semiconductor devices are key factors affecting their commercial use. Simply put, the performance, price, and size of power switch semiconductor devices are the compromises that need to be considered during product design.

[0004] At present, power switch semiconductor devices can be simply divided into two categories: one is based on the first generation of semiconductor materials, such as IGBT, Power MOS, etc.; the other is based on the third generation of semiconductor materials, such as gallium nitride high electron mobility transistor (GaN HEMT), SiC MOSFET, etc. Among them, SiC MOSFET is a very important type of power semiconductor device, which has a wide range of application scenarios in power electronics design, such as the electronic control system in electric vehicles.

[0005] According to the different gate structures, SiC MOSFET can be divided into two categories, one is planar gate SiC MOSFET, and the other is trench gate SiC MOSFET. Compared with the planar gate device structure, the trench gate SiC MOSFET device forms a conductive channel on both sides of the trench, which has the advantages of low on-resistance, high power density and small cell size, and is currently the mainstream commercial technology solution in the industry.

[0006] Compared with the planar gate device structure, the gate oxide quality of trench gate SiC MOSFET is its weak point, especially the gate oxide at the bottom of the trench. In the manufacturing process of trench gate SiC MOSFET devices, the gate oxide is usually grown by thermal oxidation. The devices prepared based on this process have the phenomenon that the thickness of the gate oxide at the bottom of the trench is thinner than the gate oxide at the sidewall of the trench. When the device is turned off, the gate at the bottom of the trench is most likely to bear most of the voltage from the drain, and the gate oxide at the bottom of the trench forms a high electric field, so the gate oxide at this location is most likely to break down.

[0007] In summary, the trench gate SiC MOSFET device in the prior art has the problems of poor quality of the gate oxide layer at the bottom of the trench and poor anti-breakdown capability. Summary of the invention

[0008] In order to solve the above technical problems, the present invention provides a semiconductor device and a method for manufacturing the same to solve the problems raised in the above background technology.

[0009] In a first aspect, an embodiment of the present invention provides the following technical solution: a semiconductor device, comprising a substrate, and an epitaxial layer, a first well region, and a source region sequentially deposited on the substrate, wherein a drain electrode is provided below the substrate, a source region groove is provided on the first well region, and the source region is provided in the source region groove; A groove is provided on the epitaxial layer, the groove extends upward and passes through the first well region and the source region, a gate oxide layer is provided on the bottom and sidewalls of the groove, a first dielectric layer and a gate conductive layer are provided in the groove in sequence, a second dielectric layer is provided on the side of the groove facing away from the epitaxial layer, the second dielectric layer covers the upper surface of the groove, and source electrodes are provided on both sides of the second dielectric layer.

[0010] Compared with the prior art, the beneficial effects of the present application are as follows: the first dielectric layer of the present invention is located between the gate conductive layer and the gate oxide layer at the bottom of the groove, which plays a role in thickening the dielectric layer below the gate conductive layer, while not affecting the gate conductive layer's ability to control the channel region on both sides of the groove. In the pinch-off state, the reverse bias is applied between the gate conductive layer and the drain electrode, and the first dielectric layer plays a role in protecting the gate oxide layer below the groove, reducing the risk of the gate oxide layer in this area being broken down, and improving the reliability of the device. Compared with the trench gate SiC MOSFET device in the prior art, the device structure and manufacturing method proposed in the present invention have conductive channels on both sides of the groove, so the cell size will not be increased and the power density will not be reduced. The device structure and manufacturing method proposed in the present invention do not thicken the gate oxide layer thickness of the sidewall of the groove, so the threshold voltage of the device can still be designed according to the application scenario. At the same time, the device structure and manufacturing method proposed in the present invention do not require a precise P+ protective layer depth injection process, and the process is simple, with high mass production consistency and high process controllability.

[0011] Preferably, the trench extends to the epitaxial layer to a depth of not less than 1 um.

[0012] Preferably, the thickness of the first dielectric layer is greater than three times the thickness of the gate oxide layer.

[0013] Preferably, a well region groove is provided on the first well region, the well region groove is provided on both sides of the source region, and a second well region is provided on the well region groove.

[0014] Preferably, the height difference between the upper surface of the first dielectric layer and the lower surface of the first well region is not less than 0.1 um.

[0015] Preferably, the material of the first dielectric layer is air or polyimide.

[0016] Preferably, the material of the second dielectric layer is SiN.

[0017] Preferably, the material of the gate conductive layer is conductive polysilicon.

[0018] Preferably, the material of the gate oxide layer is SiN or SiO2.

[0019] In a second aspect, an embodiment of the present invention further provides the following technical solution, a method for preparing a semiconductor device, the method comprising the following steps: S1. providing a substrate, and sequentially depositing an epitaxial layer, a first well region, and a source region on the substrate; S2, forming a trench on the epitaxial layer, the first well region, and the source region by etching, and preparing a gate oxide layer at the bottom and sidewall of the trench; S3, preparing a first dielectric layer at the bottom of the trench; S4, preparing a gate conductive layer on the first dielectric layer; S5, depositing a second dielectric layer above the trench, and forming source electrodes on both sides of the second dielectric layer and a drain electrode under the substrate to obtain a finished semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 A structural diagram of a semiconductor device provided in Embodiment 1 of the present invention; Figure 2 A flowchart of a method for preparing a semiconductor device provided in Embodiment 2 of the present invention; Figure 3 A schematic diagram of a semi-finished product produced in step S1 of the method for preparing a semiconductor device provided in the second embodiment of the present invention; Figure 4 A schematic diagram of a semi-finished product produced in step S2 of the method for preparing a semiconductor device provided in the second embodiment of the present invention; Figure 5 A schematic diagram of a semi-finished product of a trench filled with polyimide in step S3 of the method for preparing a semiconductor device provided in the second embodiment of the present invention; Figure 6 A schematic diagram of a semi-finished product produced in step S3 of the method for preparing a semiconductor device provided in the second embodiment of the present invention; Figure 7 A schematic diagram of a semi-finished product produced in step S4 of the method for preparing a semiconductor device provided in the second embodiment of the present invention; Figure 8 A schematic diagram of etching a semi-finished product of solidified polyimide by a dry etching process in step S31 of a method for preparing a semiconductor device provided by another embodiment of the present invention; Fig. 9 A schematic diagram of a semi-finished product of a trench filled with photoresist in step S33 of a method for preparing a semiconductor device provided by another embodiment of the present invention; Fig.10 A schematic diagram of a semi-finished product produced in step S33 of a method for preparing a semiconductor device according to another embodiment of the present invention; Fig.11 A schematic diagram of a semi-finished product of the remaining portion of the photoresist at the bottom of the trench in step S41 of a method for preparing a semiconductor device provided by another embodiment of the present invention; Fig.12 A schematic diagram of a semi-finished product produced in step S41 of a method for preparing a semiconductor device according to another embodiment of the present invention.

[0022] Description of reference numerals:

[0023] The embodiments of the present invention will be further described below with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0025] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0027] In the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0028] Embodiment 1 like Figure 1 As shown, the first embodiment of the present invention provides a semiconductor device, including a substrate 102 and an epitaxial layer 103, a first well region 106, and a source region 108 sequentially deposited on the substrate 102, a drain electrode 101 is provided below the substrate 102, a source region groove is opened on the first well region 106, and the source region 108 is arranged in the source region groove; A trench is provided on the epitaxial layer 103, the trench extends upward and penetrates the first well region 106 and the source region 108, a gate oxide layer 110 is provided on the bottom and sidewalls of the trench, a first dielectric layer 104 and a gate conductive layer 105 are provided in the trench in sequence, a second dielectric layer 109 is provided above the trench, and source electrodes 107 are provided on both sides of the second dielectric layer 109; A gate oxide layer 110 is provided on the bottom and sidewalls of the trench, a first dielectric layer 104 is provided above the gate oxide layer at the bottom of the trench, a gate conductive layer 105 is provided above the first dielectric layer 104, and the gate oxide layer 110, the first dielectric layer 104 and the gate conductive layer 105 fill the entire trench.

[0029] Specifically, the substrate 102 , the epitaxial layer 103 , and the source region 108 are N-type semiconductor layers of the same conductivity type but with different doping concentrations, and the first well region 106 is a P-type semiconductor layer; Among them, the first dielectric layer 104 is located between the gate conductive layer 105 and the gate oxide layer 110, which plays the role of thickening the dielectric under the gate conductive layer 105, while not affecting the control ability of the gate conductive layer 105 on the channel area on both sides of the groove. In the pinch-off state, the reverse bias is applied between the gate conductive layer 105 and the drain electrode 101, and the first dielectric layer 104 plays the role of protecting the gate oxide layer 110 under the groove, reducing the risk of the gate oxide layer 110 in this area being broken down, and improving the reliability of the device.

[0030] In this embodiment, the trench extends to a depth of no less than 1 um in the epitaxial layer 103 .

[0031] In this embodiment, the thickness of the first dielectric layer 104 is greater than three times the thickness of the gate oxide layer 110 .

[0032] In this embodiment, a well region groove is disposed on the first well region 106 , the well region groove is disposed on both sides of the source region 108 , and a second well region 116 is disposed on the well region groove.

[0033] In this embodiment, the height difference between the upper surface of the first dielectric layer 104 and the lower surface of the first well region 106 is not less than 0.1 um.

[0034] In this embodiment, the material of the first dielectric layer 104 is air or polyimide.

[0035] In this embodiment, the material of the second dielectric layer 109 is SiN.

[0036] In this embodiment, the material of the gate conductive layer 105 is conductive polysilicon.

[0037] In this embodiment, the material of the gate oxide layer 110 is SiN or SiO 2 .

[0038] In summary, the advantage of the first embodiment is that the first dielectric layer 104 of the present invention is located between the gate conductive layer 105 and the gate oxide layer 110, and plays a role in thickening the dielectric under the gate conductive layer 105, while not affecting the control ability of the gate conductive layer 105 on the channel regions on both sides of the trench. In the pinch-off state, the reverse bias is applied between the gate conductive layer 105 and the drain electrode 101, and the first dielectric layer 104 plays a role in protecting the gate oxide layer 110 under the trench, reducing the risk of the gate oxide layer 110 in this area being broken down, thereby improving the reliability of the device. Compared with the trench gate SiC MOSFET device in the prior art, the device structure and manufacturing method proposed in the present invention have conductive channels on both sides of the trench, so the cell size will not be increased and the power density will not be reduced. The device structure and manufacturing method proposed in the present invention do not thicken the gate oxide layer 110 thickness of the trench sidewall, so the threshold voltage of the device can still be designed according to the application scenario. At the same time, the device structure and manufacturing method proposed in the present invention do not require a precise P+ protective layer depth implantation process, and the process is simple, with high mass production consistency and high process controllability.

[0039] Embodiment 2 like Figure 2 As shown, the second embodiment of the present invention provides a method for preparing a semiconductor device, the method comprising the following steps: like Figure 3 As shown, S1, providing a substrate 102, and sequentially depositing an epitaxial layer 103, a first well region 106 and a source region 108 on the substrate 102; Specifically, the substrate 102 in the present invention is an 8-inch N-type 4H-SiC substrate with a thickness of 500um and a doping concentration of 1e19cm -3 The epitaxial layer 103 is prepared on the substrate 102 by epitaxy. The epitaxy method is not limited to chemical vapor deposition, molecular beam epitaxial growth, etc. The epitaxial layer 103 is preferably an N-type SiC semiconductor layer with a thickness of 10um and a doping concentration of 1e15cm -3 ; A first well region 106 of a second conductivity type is formed on the epitaxial layer 103 by an ion implantation process. The conductivity type of the first well region 106 is different from that of the epitaxial layer 103. The epitaxial layer 103 is preferably a P-type semiconductor, with an implantation depth of 1 um and a doping concentration of 1e17 cm -3 Then, an injection mask layer is prepared on the well region 106. The commonly used mask layer material is preferably SiN medium. Then, the ion injection opening area and the source region groove of the source region 108 are formed by a combination of photolithography and etching processes. Finally, the source region 108 is transformed into a first conductive type semiconductor by an ion implantation process. The depth of the source region 108 is lower than the depth of the first well region 106. Here, the implantation depth is preferably 0.5um and the doping concentration is 1e20cm -3The implantation profile described here can be uniformly distributed or non-uniformly distributed. After the implantation is completed, the implanted ions need to be activated at high temperature to achieve the purpose of doping. Similarly, the preparation process of the first well region 106 and the source region 108 is also a mature process in the industry. Products of different specifications correspond to different implantation depths and concentration profile requirements, which is not the innovation of the present invention. Therefore, only typical values ​​under characteristic conditions are given here, and all possibilities are not exhausted. Specifically, after the source region 108 is prepared, a corresponding well region groove is etched on the first well region 106 through a mask, and then the second well region 116 is grown in the well region groove.

[0040] like Figure 4 As shown, S2, forming a trench on the epitaxial layer 103, the first well region 106, and the source region 108 by etching, and preparing a gate oxide layer 110 at the bottom and sidewall of the trench; Specifically, a groove penetrating the source region 108, the first well region 106 and extending to a portion of the epitaxial layer 103 is formed by an etching process. The etching mask layer used when etching the groove can be a photoresist with a high etching selectivity ratio with the SiC material, or it can be a hard mask, such as a SiN material. The groove area is exposed by a photolithography process and an etching opening process. The groove can be formed into a deep groove using an anisotropic dry etching method. Common etching processes include inductively coupled plasma etching, reactive ion etching and other process methods. As described above, the groove depth must penetrate the source region 108, the first well region 106 and extend to the epitaxial layer 103, so the groove depth must be greater than the injection depth of the first well region 106. Here, the groove depth is preferably 2um, and the groove width must be greater than twice the sidewall thickness. At the same time, in order to ensure a lower gate resistance, the groove width is preferably 1.2um; After the trench is formed, a gate oxide layer 110 is made on the bottom and sidewalls of the trench. The gate oxide layer 110 can be an insulating medium such as SiN, SiO2, etc., and commercially commonly used SiO2 is preferred. The gate oxide layer 110 is formed by a thermal oxidation process. The thickness of the gate oxide layer 110 is related to the product threshold voltage. In the actual process, it will be designed according to the process capability and product specifications. Here, the thickness is preferably 100nm.

[0041] S3, preparing a first dielectric layer 104 at the bottom of the trench; like Figure 5 , Figure 6As shown, specifically, in this embodiment, the material of the first dielectric layer 104 is polyimide, and the polyimide is spin-coated on the surface of the wafer. Since the polyimide itself has fluidity, the grooves will be filled during the surface spin coating to form a flat surface, and then the polyimide on the surface of the upper wafer and in the grooves is removed by conventional processes such as exposure, development, and degumming. During the process, the thickness of the remaining polyimide at the bottom of the groove can be controlled by controlling the exposure amount of the polyimide. Finally, the polyimide is denatured into the first dielectric layer 104 that meets the requirements through a high-temperature hardening process. As described above, through the control of the exposure process, it can be achieved that the thickness of the first dielectric layer 104 is 3 times or more than the thickness of the gate oxide layer 110, and the height difference between the upper surface of the first dielectric layer 104 and the lower surface of the first well region 106 is greater than or equal to 0.1um.

[0042] like Figure 7 As shown, S4, preparing a gate conductive layer 105 on the first dielectric layer 104; Specifically, a gate conductive layer 105 is manufactured in the groove. The material of the gate conductive layer 105 can be conductive polysilicon, aluminum, copper or other metals. The conductive polysilicon material commonly used in the industry is preferred here. In order to match the material properties of the aforementioned first dielectric layer 104, the polysilicon preparation process here chooses to use a low-temperature chemical deposition process with a typical process temperature of 450°C, and then the gate conductive layer 105 is formed through a photolithography process and an etching process.

[0043] S5, depositing a second dielectric layer 109 above the trench, and forming source electrodes 107 on both sides of the second dielectric layer 109 and forming a drain electrode 101 below the substrate 102, so as to obtain a finished semiconductor device; The second dielectric layer 109 is fabricated on the wafer surface by chemical vapor deposition process. The second dielectric layer 109 is located above the trench, the source region 108 and the first well region 106. Preferably, SiN is selected as the dielectric with a thickness of 1000 nm.

[0044] The opening area of ​​the source electrode 107 is formed on the second dielectric layer 109 by photolithography and etching, and then the source electrode 107 is formed by metal evaporation or electroplating. The preferred process here is metal evaporation. The typical metal layer is Ti / Al alloy. After a high-temperature annealing process, the source electrode 107 forms an ohmic contact with the source region 108 and the first well region 106. The typical annealing temperature is 420° C. Afterwards, a drain electrode 101 is prepared on the lower surface of the substrate 102 , and the drain electrode 101 forms an ohmic contact with the substrate 102 .

[0045] In another embodiment of the present invention, a method for preparing a semiconductor device is provided. This embodiment is different from step S3 of the second embodiment, and specifically includes the following steps: S1, S2, S31, S4, S5. Steps S1, S2, S4, S5 in this embodiment are the same as steps S1, S2, S4, S5 in the second embodiment, and step S31 of this embodiment is specifically as follows: Spin polyimide on the surface of the wafer. Since polyimide is fluid, it will fill the grooves when it is spun on the surface, forming a flat surface on the surface of the wafer. Part of the polyimide on the surface of the wafer is removed by patterned exposure and development, and the remaining polyimide in the grooves and part of the surface of the wafer is then treated at high temperature to solidify the polyimide. Finally, the solidified polyimide is etched by dry etching to form Figure 8 The dry etching process can be used to precisely control the etching amount and the thickness of the remaining polyimide first dielectric layer 104 in the groove. Through process control, the thickness of the first dielectric layer 104 can be 3 times or more than the thickness of the gate oxide layer 110, and the height difference between the upper surface of the first dielectric layer 104 and the lower surface of the first well region 106 can be greater than or equal to 0.1um.

[0046] In yet another embodiment of the present invention, a method for preparing a semiconductor device is provided. This embodiment is different from steps S3 and S4 of the second embodiment, and specifically includes the following steps: S1, S2, S32, S41, S5. Steps S1, S2, S5 in this embodiment are the same as steps S1, S2, S5 in the second embodiment, and step S32 in this embodiment is specifically as follows: like Fig. 9 , Fig.10 As shown, photoresist 304 is spin-coated on the surface of the wafer. Since photoresist 304 has fluidity, it will fill the grooves when it is spin-coated on the surface to form a flat surface. Part of the photoresist 304 on the surface of the wafer is removed through patterned exposure, development, and degumming processes, and part of the photoresist 304 remains at the bottom of the groove. Through process control, the thickness of the photoresist 304 can be 3 times or more of the thickness of the gate oxide layer 110, and the height difference between the upper surface of the photoresist 304 and the lower surface of the first well region 106 can be greater than or equal to 0.1um; Step S41 of this embodiment is specifically as follows: like Fig.11 , Fig.12As shown, a gate conductive layer 105 is manufactured in the groove. The material of the gate conductive layer 105 can be conductive polysilicon, aluminum, copper and other metals. Here, the conductive polysilicon material commonly used in the industry is preferably selected. The polysilicon preparation process here uses a low-temperature chemical deposition process, with a typical process temperature of 450°C, and then the gate conductive layer 105 is formed by a photolithography process and an etching process. Then, the photoresist 304 under the gate conductive layer 105 in the wet stripping process area is formed to form a first dielectric layer 104 similar to an air bridge. Here, the first dielectric layer 104 is air.

[0047] In summary, the first dielectric layer 104 of the present application is located between the gate conductive layer 105 and the gate oxide layer 110, and plays a role in thickening the dielectric under the gate conductive layer 105, while not affecting the control ability of the gate conductive layer 105 on the channel regions on both sides of the trench. In the pinch-off state, the reverse bias is applied between the gate conductive layer 105 and the drain electrode 101, and the first dielectric layer 104 plays a role in protecting the gate oxide layer 110 under the trench, reducing the risk of breakdown of the gate oxide layer 110 in this area, and improving the reliability of the device. Compared with the trench gate SiC MOSFET device in the prior art, the device structure and manufacturing method proposed in the present invention have conductive channels on both sides of the trench, so the cell size will not be increased and the power density will not be reduced. The device structure and manufacturing method proposed in the present invention do not thicken the gate oxide layer 110 thickness of the trench sidewall, so the threshold voltage of the device can still be designed according to the application scenario. At the same time, the device structure and manufacturing method proposed in the present invention do not require a precise P+ protective layer depth implantation process, the process is simple, the mass production consistency is high, and the process controllability is high.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: It comprises a substrate and an epitaxial layer, a first well region, and a source region sequentially deposited on the substrate, wherein a drain electrode is provided below the substrate, a source region groove is provided on the first well region, and the source region is provided in the source region groove; A groove is provided on the epitaxial layer, the groove extends upward and passes through the first well region and the source region, a gate oxide layer is provided on the bottom and sidewalls of the groove, a first dielectric layer and a gate conductive layer are provided in the groove in sequence, a second dielectric layer is provided on the side of the groove facing away from the epitaxial layer, the second dielectric layer covers the upper surface of the groove, and source electrodes are provided on both sides of the second dielectric layer.

2. The semiconductor device according to claim 1, wherein: The trench extends to a depth of not less than 1 um in the epitaxial layer.

3. The semiconductor device according to claim 1, wherein: The thickness of the first dielectric layer is greater than three times the thickness of the gate oxide layer.

4. The semiconductor device according to claim 1, wherein: A well region groove is provided on the first well region, the well region groove is provided on both sides of the source region, and a second well region is provided on the well region groove.

5. The semiconductor device according to claim 1, wherein: A height difference between an upper surface of the first dielectric layer and a lower surface of the first well region is not less than 0.1 um.

6. The semiconductor device according to claim 1, wherein: The material of the first dielectric layer is air or polyimide.

7. The semiconductor device according to claim 1, wherein: The material of the second dielectric layer is SiN.

8. The semiconductor device according to claim 1, wherein: The material of the gate conductive layer is conductive polysilicon.

9. The semiconductor device according to claim 1, wherein: The material of the gate oxide layer is SiN or SiO2.

10. A method for preparing a semiconductor device according to any one of claims 1 to 9, characterized in that: The preparation method comprises the following steps: S1. providing a substrate, and sequentially depositing an epitaxial layer, a first well region, and a source region on the substrate; S2, forming a trench on the epitaxial layer, the first well region, and the source region by etching, and preparing a gate oxide layer at the bottom and sidewall of the trench; S3, preparing a first dielectric layer at the bottom of the trench; S4, preparing a gate conductive layer on the first dielectric layer; S5, depositing a second dielectric layer above the trench, and forming source electrodes on both sides of the second dielectric layer and a drain electrode under the substrate to obtain a finished semiconductor device.

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