Output voltage sampling circuit, output voltage sampling method and flyback converter using output voltage sampling circuit

Abstract

According to the output voltage sampling circuit, the sampling method and the flyback converter applying the output voltage sampling circuit, a two-stage switching circuit is adopted, and when the first stage is in an on state, the first voltage follows the sampling voltage; when the sampling voltage drop rate is relatively high, the first stage is rapidly controlled to be in an open circuit state, and the first voltage drop is controlled to be less; the second stage is controlled to be in an on state after a first time when the first stage starts to be in an off state, and in a stable state, the second voltage is approximately equal to the first voltage when the first stage starts to be in the off state, and the second voltage at the moment can be regarded as inflection point voltage on the auxiliary winding and is used for representing output voltage. According to the invention, after a corresponding triggering condition is reached, the state of the first stage is rapidly switched, and the sampling voltage is updated or stored in time; and after the first stage is in the open-circuit state, the second stage is controlled to be in the closed-circuit state after the first time, so that the problem of error sampling caused by interference signals can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of flyback converters, and in particular to an output voltage sampling circuit and method and a flyback converter using the same. Background Art

[0002] In the prior art, primary-side controlled flyback converters are widely used, such as Figure 1 As shown, it is a schematic diagram of a primary-side controlled flyback converter, which includes a primary winding Np, a secondary winding Ns and an auxiliary winding Naux, and also includes a main switch tube Q1 and a primary controller U1 arranged on the primary side, and a synchronous rectifier Q2 and a synchronous rectifier controller U2 arranged on the secondary side; the primary controller U1 is used to control the conduction or shutoff of the main switch tube Q1; the synchronous rectifier Q2 is used to control the conduction or shutoff of the synchronous rectifier tube Q2, and of course, the synchronous rectifier tube Q2 can also be replaced by a diode. In a primary-side controlled flyback converter, the output voltage of the flyback converter can be fed back through the voltage on the auxiliary winding, such as Figure 2a As shown in FIG. 1 , a waveform diagram of sampling the output voltage through the voltage on the auxiliary winding is shown. At time t2, that is, when the secondary freewheeling current is zero, the voltage on the auxiliary winding is sampled. At this time, the voltage on the auxiliary winding ( Figure 1 V1 (which can also be regarded as the inflection point voltage) is proportional to the output voltage, that is, the output voltage can be represented by the voltage on the auxiliary winding at time t2. In the prior art, the common method for sampling the voltage on the auxiliary winding at time t2 is to use the slope detection method. However, Figure 2b As shown in the figure, during the secondary side freewheeling time, when there is an interference signal (indicated by the waveform in the ta-tb time period), for example, when ESD (electrostatic discharge) or surge occurs, it is easy to cause mis-sampling, which makes the anti-interference performance of the system poor. In addition, when the sampling is more sensitive, the sampling may be performed at the time tm, and the voltage on the auxiliary winding is Vm at this time. Similarly, when the sampling design is not sensitive, the sampling is performed at the time tn, and the voltage on the auxiliary winding is Vn at this time. Figure 2b It can be seen that there is a certain deviation between Vm, Vn and V1, which leads to inaccurate sampling results, and in turn leads to inaccurate output voltage sampling, which has an adverse effect on the stability of the system. Therefore, it is necessary to propose a new output voltage sampling circuit to solve the problems existing in the prior art. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides an output voltage sampling circuit, method and a flyback converter using the same.

[0004] According to a first aspect of the present invention, an output voltage sampling circuit is provided, which is applied to a flyback converter, wherein the flyback converter comprises an auxiliary winding, a main switch tube arranged on a primary side, and a primary side controller, wherein the primary side controller is used to control the on or off of the main switch tube; the sampled voltage on the auxiliary winding is connected to a first pin of the primary side controller; the output voltage sampling circuit is arranged in the primary side controller; and the output voltage sampling circuit comprises:

[0005] A first-stage switch circuit, whose input terminal receives the sampled voltage and whose output terminal outputs a first voltage; when the first-stage switch circuit is in a conducting state, the first voltage changes with the sampled voltage;

[0006] a second-stage switch circuit, whose input terminal receives the first voltage and whose output terminal outputs a second voltage; in a stable working state, when the second-stage switch circuit is in a conducting state, the second voltage is approximately equal to the first voltage at the beginning of the first-stage switch circuit being in an off-circuit state; the second voltage is used to characterize the output voltage;

[0007] A logic control circuit, used for outputting corresponding control signals to control the first-stage switch circuit and the second-stage switch circuit to be in a circuit-on state or a circuit-off state;

[0008] Among them, after the main switch tube is turned off, or after a second time after the main switch tube is turned off, when the decreasing rate of the sampling voltage is greater than a certain value, the logic control circuit quickly controls the first-stage switch circuit to be in an open circuit state, and controls the first voltage not to drop much, otherwise, the first-stage switch circuit is controlled to be in a closed state; the logic control circuit controls the second-stage switch circuit to be in a closed state after a first time from the beginning of the first-stage switch circuit being in the open circuit state.

[0009] Optionally, when the difference between the first voltage and the sampled voltage is greater than a first reference voltage threshold, it is considered that the decreasing rate of the sampled voltage is greater than a certain value.

[0010] Optionally, the logic control circuit includes a third capacitor and a fourth resistor arranged between the first pin and the ground terminal, and a pull-up current source is further arranged at a common node of the third capacitor and the fourth resistor;

[0011] When the voltage on the fourth resistor is less than the second reference voltage threshold, it is considered that the decreasing rate of the sampling voltage is greater than a certain value.

[0012] Optionally, the first-stage switch circuit includes a first switch, a third resistor and a first capacitor, and the first switch, the third resistor and the first capacitor are connected in series between the first pin and the ground terminal;

[0013] The first voltage is outputted at a common node of the third resistor and the first capacitor.

[0014] Optionally, the second-stage switch circuit includes a second switch and a second capacitor, and the second switch and the second capacitor are connected in series between a common node of the third resistor and the first capacitor and a ground terminal;

[0015] The second voltage is outputted at a common node between the second switch and the second capacitor.

[0016] Optionally, the first capacitance is greater than the second capacitance.

[0017] Optionally, after the first-stage switch circuit is in an open state and before the second-stage switch circuit is in an open state, the first voltage remains unchanged.

[0018] Optionally, when the duration of the first-stage switch circuit being in the open circuit state is less than a first time, the second-stage switch circuit is controlled to be in the open circuit state.

[0019] Optionally, the second time is a blanking time.

[0020] Optionally, the first-stage switch circuit and the second-stage switch circuit are not in the on state at the same time.

[0021] Optionally, within a second time after the main switch tube is turned off, the logic control circuit controls the second-stage switch circuit to be in an open circuit state.

[0022] The present invention also provides a flyback converter, the flyback converter includes an auxiliary winding, a main switch tube arranged on the primary side, and a primary side controller, the primary side controller is used to control the on or off of the main switch tube; the sampled voltage on the auxiliary winding is connected to the first pin of the primary side controller; the flyback converter also includes a synchronous rectifier tube and a synchronous rectifier controller arranged on the secondary side, the synchronous rectifier is used to control the on or off of the synchronous rectifier tube;

[0023] It is characterized in that the flyback converter includes the output voltage sampling circuit mentioned above.

[0024] The present invention also provides a primary side controller, which is applied to a flyback converter. The flyback converter includes an auxiliary winding, a main switch tube arranged on the primary side, and a primary side controller. The primary side controller is used to control the conduction or shutdown of the main switch tube; the sampling voltage on the auxiliary winding is connected to the first pin of the primary side controller; the output voltage sampling circuit is arranged in the primary side controller; and it is characterized in that the primary side controller includes the output voltage sampling circuit described above.

[0025] The present invention also provides an output voltage sampling method, which is applied to a flyback converter, wherein the flyback converter includes an auxiliary winding, a main switch tube arranged on the primary side, and a primary side controller, wherein the primary side controller is used to control the on or off of the main switch tube; the sampled voltage on the auxiliary winding is connected to the first pin of the primary side controller; the output voltage sampling method includes:

[0026] When the first-stage switch circuit is in a conducting state, the first voltage changes following the sampling voltage;

[0027] In a stable working state, when the second-stage switch circuit is in a conducting state, the second voltage is approximately equal to the first voltage at the beginning of the first-stage switch circuit being in an off-circuit state; the second voltage is used to characterize the output voltage;

[0028] Among them, after the main switch tube is turned off, or after a second time after the main switch tube is turned off, when the decreasing rate of the sampling voltage is greater than a certain value, the first-stage switch circuit is quickly controlled to be in an open circuit state, and the first voltage is controlled not to drop much, otherwise, the first-stage switch circuit is controlled to be in a closed state; the second-stage switch circuit is controlled to be in a closed state after a first time from the beginning of the first-stage switch circuit being in the open circuit state.

[0029] Optionally, when the difference between the first voltage and the sampled voltage is greater than a first reference voltage threshold, it is considered that the decreasing rate of the sampled voltage is greater than a certain value.

[0030] Optionally, a third capacitor and a fourth resistor are provided between the first pin and the ground terminal, and a pull-up current source is further provided at a common node of the third capacitor and the fourth resistor;

[0031] When the voltage on the fourth resistor is less than the second reference voltage threshold, it is considered that the decreasing rate of the sampling voltage is greater than a certain value.

[0032] Optionally, the first switch, the third resistor and the first capacitor are connected in series between the first pin and the ground terminal;

[0033] The first voltage is outputted at a common node of the third resistor and the first capacitor.

[0034] Optionally, the second switch and the second capacitor are connected in series between a common node of the third resistor and the first capacitor and a ground terminal;

[0035] The second voltage is outputted at a common node between the second switch and the second capacitor.

[0036] The beneficial effects of the present invention include at least:

[0037] The output voltage sampling circuit, sampling method and flyback converter using the same provided in this article, the output voltage sampling circuit adopts a two-stage switch circuit, when the first-stage switch circuit is in the on-state, the first voltage changes with the sampling voltage; when the sampling voltage drops at a faster rate, the first-stage switch circuit is quickly controlled to be in the off-state, and the first voltage is controlled to drop less and remain basically unchanged, so as to save the inflection point voltage of the auxiliary winding; after the first time passes at the beginning of the first-stage switch circuit being in the off-state, the second-stage switch circuit is controlled to be in the on-state, and in a stable state, the second voltage is nearly equal to the first voltage at the beginning of the first-stage switch circuit being in the off-state, and the second voltage at this time can be regarded as the inflection point voltage on the auxiliary winding, which is used to characterize the output voltage. The present invention controls the state of the first-stage switch circuit by controlling the logic circuit, and after reaching the corresponding trigger condition, quickly switches the state of the first-stage switch circuit to timely update or save the sampling voltage; and after the first-stage switch circuit is in the off-state, the second-stage switch circuit is controlled to be in the on-state after the first time passes, and the inflection point voltage on the auxiliary winding is output, which can avoid the problem of mis-sampling caused by interference signals.

[0038] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a primary-side controlled flyback converter is shown;

[0040] Figure 2a A waveform diagram showing the output voltage sampling by the voltage on the auxiliary winding;

[0041] Figure 2b A waveform diagram showing the mis-sampling of the auxiliary winding inflection point voltage when there is an interference signal;

[0042] Figure 3 A schematic diagram of an output voltage sampling circuit provided by the present invention is shown;

[0043] Figure 4 Shown based on Figure 3 A working waveform diagram of the output voltage sampling circuit in;

[0044] Figure 5 Shown based on Figure 3 Another working waveform diagram of the output voltage sampling circuit in FIG.

[0045] Figure 6 Another schematic diagram of an output voltage sampling circuit provided by the present invention is shown;

[0046] Figure 7 Shown based on Figure 6 A working waveform diagram of the output voltage sampling circuit in;

[0047] Figure 8 Shown based on Figure 6 Another working waveform diagram of the output voltage sampling circuit in . DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0049] The present invention is based on Figure 1 The flyback converter in the example is as follows: Figure 1 As shown in , a first resistor R1 and a second resistor R2 connected in series are provided between the two ends of the auxiliary winding Naux, and a common node of the first resistor R1 and the second resistor R2 is connected to a first pin VS of the primary controller U1, and the voltage on the first pin VS is used as a sampling voltage; a DRV pin is also provided in the primary controller U1 for outputting a driving signal GON for controlling the main switch tube Q1. It should be noted that Figure 1 The schematic diagram of the primary-side controlled flyback converter is only an example and does not mean that the present invention is limited to Figure 1 The circuit in the embodiment can also be deformed accordingly, and the present application is also applicable to the deformed flyback converter.

[0050] The output voltage sampling circuit proposed by the present invention is arranged in the primary side controller U1; the output voltage sampling circuit includes a first-stage switch circuit, a second-stage switch circuit and a logic control circuit. The first-stage switch circuit receives the sampling voltage at its input end and outputs the first voltage at its output end; when the first-stage switch circuit is in the on state, the first voltage changes with the sampling voltage. The second-stage switch circuit receives the first voltage at its input end and outputs the second voltage at its output end; in a stable working state, when the second-stage switch circuit is in the on state, the second voltage is nearly equal to the first voltage at the beginning of the first-stage switch circuit being in the off state; the second voltage is used to characterize the output voltage. The logic control circuit is used to output corresponding control signals to control the first-stage switch circuit and the second-stage switch circuit to be in the on state or the off state. Among them, after the main switch tube is turned off, or after the second time after the main switch tube is turned off, when the rate of decrease of the sampling voltage is greater than a certain value, the logic control circuit quickly controls the first-stage switch circuit to be in an open circuit state, and controls the first voltage to drop less, otherwise, the first-stage switch circuit is controlled to be in a closed state (it can be regarded as that the control logic for controlling the first-stage switch circuit has a high sensitivity, and when the corresponding trigger condition is met, the state of the first-stage switch circuit can be quickly switched, and the sensitivity can be set by setting the corresponding delay in the circuit); the logic control circuit controls the second-stage switch circuit to be in a closed state after a first time from the beginning of the first-stage switch circuit being in the open circuit state.

[0051] The present invention sets a two-stage switch circuit, the first-stage switch circuit is used to sample the voltage on the auxiliary winding, and when the sampling voltage drops faster and is greater than a certain value, the first voltage is controlled to drop less and remain basically unchanged, and the first-stage switch circuit is quickly controlled to be in an open circuit state to save the inflection point voltage, otherwise the first-stage switch circuit is controlled to be in a pass state; and the second-stage switch circuit is controlled to be in a pass state after a first time after the first-stage switch circuit is in an open circuit state, and in a stable working state, the second voltage can be nearly equal to the first voltage at the beginning of the first-stage switch circuit being in an open circuit state, and the second voltage is output, that is, the second voltage at this time can be regarded as the inflection point voltage on the auxiliary winding, which can be used to characterize the output voltage. The present invention controls the state of the first-stage switch circuit through control logic, and after reaching the corresponding trigger condition, the state of the first-stage switch circuit is quickly switched to timely update or save the sampling voltage; and after the first-stage switch circuit is in an open circuit state, the second-stage switch circuit is controlled to be in a pass state after a first time, and the inflection point voltage on the auxiliary winding is output, which can avoid the problem of mis-sampling caused by interference signals.

[0052] Further, Figure 3FIG. 1 is a schematic diagram of an output voltage sampling circuit provided by the present invention, which compares the difference between the first voltage and the sampling voltage with the first reference voltage threshold to detect the sampling voltage drop rate. Figure 3 As shown in , the first-stage switch circuit 10 includes a first switch S1, a third resistor R3 and a first capacitor C1, and the first switch S1, the third resistor R3 and the first capacitor C1 are connected in series between the first pin VS and the ground terminal; a first voltage VC1 is output at the common node of the third resistor R3 and the first capacitor C1; wherein, by setting the third resistor R3 and the first capacitor C1, when the rate of decrease of the sampling voltage is greater than a certain value, the first voltage VC1 decreases less and can be basically regarded as unchanged. Since the first voltage VC1 does not decrease much, the sampling accuracy of the output voltage can also be improved compared with the method of directly sampling the VS voltage in the prior art; when the rate of change of the sampling voltage (represented by VS) is small, the first voltage VC1 can follow the change of the sampling voltage. The second-stage switch circuit 20 includes a second switch S2 and a second capacitor C2, and the second switch S2 and the second capacitor C2 are connected in series between the common node of the third resistor R3 and the first capacitor C1 and the ground terminal; a second voltage VSSH is output at the common node of the second switch S2 and the second capacitor C2.

[0053] like Figure 3As shown, the logic control circuit 30 includes a voltage sampling circuit, which is used to sample the difference between the first voltage VC1 and the sampling voltage VS. Sense, input it to the first input terminal of the comparator U1 (in this embodiment, it is the negative terminal), the second input terminal of the comparator U1 (in this embodiment, it is the positive terminal) is connected to the first reference voltage Vref1, the value of the first reference voltage Vref1 can be set according to the actual application, and the output terminal of the comparator U1 is connected to the first input terminal of the AND gate U3; after the main switch tube Q1 is turned off, a certain resonance will be generated due to the existence of leakage inductance, and the blanking time can be set to shield the interference in this time period, and the driving signal GON and the blanking time signal LEB of the main switch tube Q1 are input to the second input terminal of the AND gate U3 after passing through the NOR gate U4; here, the inverted signal of the second switch control signal S2_G is input to the third input terminal of the AND gate U3 (that is, in this embodiment, the first switch and the second switch are controlled not to be turned on at the same time); the first switch control signal S1_G is output at the output terminal of the AND gate U3 as the control signal of the first switch; the output terminal of the AND gate U3 is connected to the input terminal of the falling edge trigger delay module, and the output terminal of the falling edge trigger delay module is connected to The set end S of the RS trigger U4 outputs the second switch control signal S2_G at its output end Q as the control signal of the second switch, that is, after the falling edge triggers the delay module to detect the falling edge (in this embodiment, when S1_G is at a high level, the first switch is controlled to be turned on; when S1_G is at a low level, the first switch is controlled to be turned off; of course, in other embodiments, corresponding changes can be made), and after a delay of the first time td, the second switch S2 is controlled to be turned on, and the system is in a stable state. When the second switch S2 is turned on, the charges on the first capacitor C1 and the second capacitor C2 are redistributed, and finally the second voltage VSSH is nearly equal to the first voltage at the time when the first switch S1 is turned off (here, in the initial state, the VSSH voltage is zero, and it may take multiple switching cycles to make the voltage on VSSH nearly equal to the first voltage at the time when the first switch is turned off, which can be considered as a stable working state). At this time, the second voltage VSSH can be regarded as the inflection point voltage on the auxiliary winding, and it can be used to represent the output voltage of the flyback converter. Figure 3 As shown in the figure, the reset terminal of the RS trigger U4 is connected to the falling edge detection module of GON ( Figure 3 The module is not shown in the figure), when the falling edge of GON arrives, the second switch S2 is controlled to be turned off. The reset terminal of the RS trigger U4 can also be directly connected to GON, and the second switch S2 is controlled when GON is at a high level; of course, other signals can be connected without affecting the circuit function, which will not be explained here one by one.

[0054] Furthermore, the first capacitor C1 may be set to be larger than the second capacitor C2, so that the second voltage VSSH can be updated to the inflection point voltage value on the auxiliary winding as quickly as possible.

[0055] Figure 4 Shown is based on Figure 3 A schematic diagram of a working waveform is shown below. Figure 4 right Figure 3 The principle in is further explained. Between t0 and t1, the main switch tube Q1 is turned on; at t1, the main switch tube Q1 is turned off. Between t1 and t2 (the length of this time period can be regarded as the second time) is the blanking time period. Between t0 and t2, the first switch control signal S1_G is at a low level, and the first switch S1 is in a disconnected state (that is, the first-stage switch circuit is in an open circuit state). After t2, the difference Voltage Sense between the first voltage VC1 and the sampled voltage VS is less than the first reference voltage threshold Vref1, and the first switch S1 is controlled to be turned on (that is, the first-stage switch circuit is in a pass state). At this time, the first voltage VC1 changes with the sampled voltage VS (here, since other circuits are also provided on the VS pin, the sampled voltage VS drops more relative to VC1). At t3, the voltage on the auxiliary winding is the inflection point voltage value. At t4, the difference Voltage between the first voltage VC1 and the sampled voltage VS is detected. Sense is greater than the first reference voltage threshold Vref1, that is, it is detected that the falling rate of the sampling voltage is greater than a certain value. At this time, the logic control circuit outputs the first switch control signal to control the first switch to turn off. Figure 4 It can be seen that at this time, the first voltage VC1 does not drop much, and is not much different from the inflection point voltage; after the first switch is turned off, after the first time td, that is, at time t5, the second switch S2 is turned on (that is, the second-stage switch circuit is in the on state), and after the charge is balanced by the first capacitor and the second capacitor (the balanced second voltage VSSH is nearly equal to the voltage at the time when the first switch is turned off), the second voltage VSSH is finally output to represent the output voltage; the working principle in the time period t6-t7 is the same as t0-t6, which will not be repeated here.

[0056] Figure 5 Shown is based on Figure 3 Another working waveform diagram of Figure 4 The difference is that there is an interference signal (such as Figure 5 Before t2, its working principle is the same as Figure 4As described in, due to the presence of interference signals during the time t2-t5, at time t3, it is detected that the difference Voltage Sense between the first voltage VC1 and the sampled voltage VS is greater than the first reference voltage threshold Vref1, that is, it is detected that the rate of decrease of the sampled voltage is greater than a certain value. At this time, the logic control circuit outputs the first switch control signal to control the first switch to be turned off; at time t4, it is detected that the difference Voltage Sense between the first voltage VC1 and the sampled voltage VS is less than the first reference voltage threshold Vref1. At this time, the logic control circuit outputs the first switch control signal to control the first switch to be turned on. Since the time length corresponding to t3-t4 is less than the first time td, even if the falling edge of the first switch control signal is detected at time t3, the second control signal will not be output to control the second switch to be turned on; at time t6, the voltage on the auxiliary winding is the inflection point voltage value. At time t7, the difference Voltage between the first voltage VC1 and the sampled voltage VS is detected. Sense is greater than the first reference voltage threshold Vref1, that is, it is detected that the rate of decrease of the sampling voltage is greater than a certain value. At this time, the logic control circuit outputs the first switch control signal to control the first switch to turn off. After the first switch is turned off, after the first time td, that is, at time t8, the second switch S2 is turned on, and after the charge is balanced by the first capacitor and the second capacitor, the second voltage VSSH is finally output to characterize the output voltage; the working principle in the t9-t10 time period is the same as described above, and will not be repeated here. It can be seen that during the time of the secondary side freewheeling, even if there is an interference signal, when the off time of the first switch is less than the first time td, the second switch will not be controlled to turn on, that is, mis-sampling is avoided. Among them, the first time td can be set according to the actual application, for example, it can be set according to the interference signal in the actual application to avoid mis-sampling. At the same time, in order to ensure that the first switch can respond quickly, the corresponding delay time in the logic control circuit can be set (for example, the delay of the comparator, etc.) to achieve that when the trigger condition is reached, the first switch can respond quickly.

[0057] Figure 6 FIG. 1 is another schematic diagram of the output voltage sampling circuit provided by the present invention, and FIG. Figure 3 The difference is that, in this embodiment, the detection of the sampling voltage change rate is achieved by comparing the voltage on the resistor with the second reference voltage threshold, that is, the setting of the logic control circuit 30 is different, and the difference is described below. Figure 6As shown in , the logic control circuit 30 includes a third capacitor C3 and a fourth resistor R4 arranged between the first pin VS and the ground terminal, and a pull-up current source I1 is also arranged at the common node of the third capacitor C3 and the fourth resistor R4; the first input terminal of the comparator U1 (in this embodiment, the negative terminal) is connected to the second reference voltage threshold Vref2, and the second input terminal of the comparator U1 (in this embodiment, the positive terminal) is connected to the common node of the third capacitor C3 and the fourth resistor R4, that is, the rate of change of the sampling voltage VS is detected by the voltage value on the fourth resistor R4. Within the time after the main switch tube is turned off, when the voltage on the fourth resistor is less than the second reference voltage threshold, it is considered that the rate of decrease of the sampling voltage is greater than a certain value. At this time, the logic control circuit controls the first switch to turn off. The remaining circuit modules of the logic control circuit 30 are the same as Figure 3 The same as in, no further description is given here.

[0058] Figure 7 Shown is based on Figure 6 A schematic diagram of a working waveform, and Figure 4 The difference is that Figure 7 The sampling voltage drop rate is detected based on the size of VR4 and the second reference voltage threshold Vref2. Between t0 and t1, the main switch tube Q1 is turned on; at t1, the main switch tube Q1 is turned off. The period between t1 and t2 (the length of this period can be regarded as the second time) is the blanking period. Similarly, between t0 and t2, the first switch control signal S1_G is at a low level, and the first switch S1 is in a disconnected state. After t2, the sampling voltage VS drops relatively slowly, VR4 is greater than the second reference voltage threshold Vref2, and the first switch S1 is controlled to be turned on. At this time, the first voltage VC1 changes with the sampling voltage VS. At t3, the voltage on the auxiliary winding is the inflection point voltage value. At t4, it is detected that VR4 is less than the second reference voltage threshold Vref2, that is, it is detected that the sampling voltage drop rate is greater than a certain value. At this time, the logic control circuit outputs the first switch control signal to control the first switch to be turned off. Figure 7 It can be seen that at this time, the first voltage VC1 does not drop much, and is not much different from the inflection point voltage; after the first switch is turned off, after the first time td, that is, at time t5, the second switch S2 is turned on, and after the charge is balanced by the first capacitor and the second capacitor (the balanced second voltage VSSH is nearly equal to the voltage at the time when the first switch is turned off), the second voltage VSSH is finally output to represent the output voltage; the working principle in the time period t6-t7 is the same as t0-t6, which will not be repeated here.

[0059] Figure 8 Shown is based on Figure 6 Another working waveform diagram of Figure 7The difference is that there is an interference signal (such as Figure 8 Before t2, its working principle is the same as Figure 7 As described in the above, due to the presence of interference signals during the time t2-t5, at time t3, it is detected that VR4 is less than the second reference voltage threshold Vref2, at which time the logic control circuit outputs the first switch control signal to control the first switch to be turned off; at time t4, it is detected that VR4 is greater than the second reference voltage threshold Vref2, at which time the logic control circuit outputs the first switch control signal to control the first switch to be turned on; since the time length corresponding to t3-t4 is less than the first time td, even if the falling edge of the first switch control signal is detected at time t3, the second control signal will not be output to control the second switch to be turned on; at time t6, the voltage on the auxiliary winding is the inflection point voltage value, at time t7, it is detected that VR4 is less than the second reference voltage threshold Vref2, that is, it is detected that the falling rate of the sampling voltage is greater than a certain value, at which time the logic control circuit outputs the first switch control signal to control the first switch to be turned off, and the voltage on the auxiliary winding at time t6 is the inflection point voltage value, and at time t7, it is detected that VR4 is less than the second reference voltage threshold Vref2, that is, it is detected that the falling rate of the sampling voltage is greater than a certain value, at which time the logic control circuit outputs the first switch control signal to control the first switch to be turned off, and the voltage on the auxiliary winding at time t8 is the inflection point voltage value, and the voltage on the auxiliary winding at time t9 is the inflection point voltage value, and the voltage on the auxiliary winding at time t10 is the inflection point voltage value, and the voltage on the auxiliary winding at time t11 is the inflection point voltage value, and the voltage on the auxiliary winding at time t12 is the inflection point voltage value, and the voltage on the auxiliary winding at time t13 is the inflection point voltage value, and the voltage on the auxiliary winding at time t14 is the inflection point voltage value, Figure 8 It can be seen that at this time, the first voltage VC1 has not dropped much, and is not much different from the inflection point voltage; after the first switch is turned off, after the first time td, that is, at time t8, the second switch S2 is turned on, and after the charge is balanced by the first capacitor and the second capacitor (the second voltage VSSH after the balance is close to the voltage at the time when the first switch is turned off), the second voltage VSSH is finally output to characterize the output voltage; the working principle in the t9-t10 time period is the same as described above, and will not be repeated here. It can be seen that during the time of secondary side freewheeling, even if there is an interference signal, when the off time of the first switch is less than the first time td, the second switch will not be controlled to turn on, that is, mis-sampling is avoided. Similarly, the first time td can be set according to the actual application, for example, it can be set according to the possible interference signal to avoid mis-sampling. At the same time, in order to ensure that the first switch can respond quickly, the corresponding delay time in the logic control circuit can be set to achieve that when the trigger condition is reached, the first switch can respond quickly.

[0060] This article also provides an output voltage sampling method, which is applied to a flyback converter, including the functions of the output voltage sampling circuit mentioned above, which will not be described in detail here.

[0061] It should be noted that Figure 3 , Figure 6The circuit configuration is only an example of the present invention, and the present invention is not limited thereto, and corresponding deformations may be made to it to achieve the same function. For example, the OR gate U2 may be replaced by a NOT gate, and the input end of the NOT gate receives the drive signal GON, that is, after the main switch tube is turned off, regardless of the influence of the resonant interference, as long as the corresponding conditions are met, the first switch can be controlled to be turned on; at this time, the circuit may be deformed accordingly, so that after the main switch tube is turned off and before the blanking time ends, the second switch is controlled to be in the off state. For another example, multiple switches may be set in the two-stage switch circuit to achieve the same function. Of course, other deformations may also be made.

[0062] In summary, the output voltage sampling circuit, sampling method and flyback converter using the same provided in this article, the output voltage sampling circuit adopts a two-stage switching circuit, when the first-stage switching circuit is in the on state, the first voltage changes with the sampling voltage; when the sampling voltage drops at a faster rate, the first-stage switching circuit is quickly controlled to be in the off state, and the first voltage is controlled to drop less and remain basically unchanged, so as to preserve the inflection point voltage of the auxiliary winding; the second-stage switching circuit is controlled to be in the on state only after a first time has passed from the beginning of the first-stage switching circuit being in the off state, and in a stable state, the second voltage is nearly equal to the first voltage at the beginning of the first-stage switching circuit being in the off state, and the second voltage at this time can be regarded as the inflection point voltage on the auxiliary winding, which is used to characterize the output voltage. The present invention controls the state of the first-stage switch circuit through a control logic circuit. After the corresponding trigger condition is reached, the state of the first-stage switch circuit is quickly switched to timely update or save the sampled voltage; and after the first-stage switch circuit is in an open-circuit state, the second-stage switch circuit is controlled to be in a closed state after a first period of time, and the inflection point voltage on the auxiliary winding is output, thereby avoiding the problem of missampling caused by interference signals.

[0063] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. An output voltage sampling circuit, applied to a flyback converter, the flyback converter comprising an auxiliary winding, a main switch tube arranged on the primary side, and a primary side controller, the primary side controller being used to control the on or off of the main switch tube; connecting the sampling voltage on the auxiliary winding to the first pin of the primary side controller; the output voltage sampling circuit being arranged in the primary side controller; characterized in that: The output voltage sampling circuit comprises: A first-stage switch circuit, whose input terminal receives the sampled voltage and whose output terminal outputs a first voltage; when the first-stage switch circuit is in a conducting state, the first voltage changes with the sampled voltage; a second-stage switch circuit, whose input terminal receives the first voltage and whose output terminal outputs a second voltage; in a stable working state, when the second-stage switch circuit is in a conducting state, the second voltage is approximately equal to the first voltage at the beginning of the first-stage switch circuit being in an off-circuit state; the second voltage is used to characterize the output voltage; A logic control circuit, used for outputting corresponding control signals to control the first-stage switch circuit and the second-stage switch circuit to be in a circuit-on state or a circuit-off state; Among them, after the main switch tube is turned off, or after a second time after the main switch tube is turned off, when the decreasing rate of the sampling voltage is greater than a certain value, the logic control circuit quickly controls the first-stage switch circuit to be in an open circuit state, and controls the first voltage not to drop much, otherwise, the first-stage switch circuit is controlled to be in a closed state; the logic control circuit controls the second-stage switch circuit to be in a closed state after a first time from the beginning of the first-stage switch circuit being in the open circuit state.

2. The output voltage sampling circuit according to claim 1, characterized in that: When the difference between the first voltage and the sampled voltage is greater than a first reference voltage threshold, it is considered that the decreasing rate of the sampled voltage is greater than a certain value.

3. The output voltage sampling circuit according to claim 1, characterized in that: The logic control circuit includes a third capacitor and a fourth resistor arranged between the first pin and the ground terminal, and a pull-up current source is also arranged at a common node of the third capacitor and the fourth resistor; When the voltage on the fourth resistor is less than the second reference voltage threshold, it is considered that the decreasing rate of the sampling voltage is greater than a certain value.

4. The output voltage sampling circuit according to claim 1, characterized in that: The first-stage switch circuit includes a first switch, a third resistor and a first capacitor, wherein the first switch, the third resistor and the first capacitor are connected in series between the first pin and the ground terminal; The first voltage is outputted at a common node of the third resistor and the first capacitor.

5. The output voltage sampling circuit according to claim 4, characterized in that: The second-stage switch circuit includes a second switch and a second capacitor, wherein the second switch and the second capacitor are connected in series between a common node of the third resistor and the first capacitor and a ground terminal; The second voltage is outputted at a common node between the second switch and the second capacitor.

6. The output voltage sampling circuit according to claim 5, characterized in that: The first capacitance is greater than the second capacitance.

7. The output voltage sampling circuit according to claim 1, characterized in that: After the first-stage switch circuit is in an open-circuit state and before the second-stage switch circuit is in an open-circuit state, the first voltage remains unchanged.

8. The output voltage sampling circuit according to claim 1, characterized in that: When the duration of the first-stage switch circuit being in the open circuit state is less than the first time, the second-stage switch circuit is controlled to be in the open circuit state.

9. The output voltage sampling circuit according to claim 1, characterized in that: The second time is a blanking time.

10. The output voltage sampling circuit according to claim 1, characterized in that: The first-stage switch circuit and the second-stage switch circuit are not in the on state at the same time.

11. The output voltage sampling circuit according to claim 1, characterized in that: In a second time after the main switch tube is turned off, the logic control circuit controls the second-stage switch circuit to be in an open circuit state.

12. A flyback converter, comprising an auxiliary winding, a main switch tube arranged on the primary side, and a primary controller, wherein the primary controller is used to control the on or off of the main switch tube; connecting the sampled voltage on the auxiliary winding to the first pin of the primary controller; the flyback converter further comprises a synchronous rectifier tube and a synchronous rectifier controller arranged on the secondary side, wherein the synchronous rectifier is used to control the on or off of the synchronous rectifier tube; It is characterized in that The flyback converter comprises the output voltage sampling circuit according to any one of claims 1-11.

13. A primary side controller, applied to a flyback converter, the flyback converter comprising an auxiliary winding, a main switch tube arranged on the primary side, and a primary side controller, the primary side controller being used to control the on or off of the main switch tube; connecting the sampled voltage on the auxiliary winding to the first pin of the primary side controller; the output voltage sampling circuit being arranged in the primary side controller; characterized in that, The primary side controller comprises the output voltage sampling circuit according to any one of claims 1-11.

14. An output voltage sampling method, applied to a flyback converter, wherein the flyback converter comprises an auxiliary winding, a main switch tube arranged on a primary side, and a primary side controller, wherein the primary side controller is used to control the on or off of the main switch tube; Connecting the sampled voltage on the auxiliary winding to the first pin of the primary controller; characterized in that: The output voltage sampling method comprises: When the first-stage switch circuit is in a conducting state, the first voltage changes following the sampling voltage; In a stable working state, when the second-stage switch circuit is in a conducting state, the second voltage is approximately equal to the first voltage at the beginning of the first-stage switch circuit being in an off-circuit state; the second voltage is used to characterize the output voltage; Among them, after the main switch tube is turned off, or after a second time after the main switch tube is turned off, when the decreasing rate of the sampling voltage is greater than a certain value, the first-stage switch circuit is quickly controlled to be in an open circuit state, and the first voltage is controlled not to drop much, otherwise, the first-stage switch circuit is controlled to be in a closed state; the second-stage switch circuit is controlled to be in a closed state after a first time from the beginning of the first-stage switch circuit being in the open circuit state.

15. The output voltage sampling method according to claim 14, characterized in that: When the difference between the first voltage and the sampled voltage is greater than a first reference voltage threshold, it is considered that the decreasing rate of the sampled voltage is greater than a certain value.

16. The output voltage sampling method according to claim 14, characterized in that: A third capacitor and a fourth resistor are provided between the first pin and the ground terminal, and a pull-up current source is also provided at a common node of the third capacitor and the fourth resistor; When the voltage on the fourth resistor is less than the second reference voltage threshold, it is considered that the decreasing rate of the sampling voltage is greater than a certain value.

17. The output voltage sampling method according to claim 14, characterized in that: Connecting the first switch, the third resistor and the first capacitor in series between the first pin and the ground terminal; The first voltage is outputted at a common node of the third resistor and the first capacitor.

18. The output voltage sampling method according to claim 17, characterized in that: The second switch and the second capacitor are connected in series between a common node of the third resistor and the first capacitor and a ground terminal; The second voltage is outputted at a common node between the second switch and the second capacitor.

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